NDS331N

General Description Features These N-Channel logic level enhancement mode power field effect transistors are produced using ON Semiconductor's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize onstate resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMCIA cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package. 1.3 A, 20 V. RDS(ON) = 0.21 Ω @ VGS= 2.7 V RDS(ON) = 0.16 Ω @ VGS= 4.5 V. Industry standard outline SOT-23 surface mount package using poprietary SuperSOTTM-3 design for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. _______________________________________________________________________________ D S G Absolute Maximum Ratings Symbol T A = 25°C unless otherwise noted Parameter NDS331N Units VDSS Drain-Source Voltage 20 V VGSS Gate-Source Voltage - Continuous 8 V ID Maximum Drain Current - Continuous 1.3 A (Note 1a) - Pulsed PD Maximum Power Dissipation TJ,TSTG Operating and Storage Temperature Range 10 (Note 1a) (Note 1b) 0.5 W 0.46 -55 to 150 °C 250 °C/W 75 °C/W THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient RθJC Thermal Resistance, Junction-to-Case (Note 1a) © 2017 Semiconductor Components Industries, LLC. September-2017, Rev. 5 (Note 1) Publication Order Number: NDS331N/D NDS331N N-Channel Logic Level Enhancement Mode Field Effect Transistor NDS331N N-Channel Logic Level Enhancement Mode Field Effect Transistor Symbol Parameter Conditions Min Typ Max Units 1 µA OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA IDSS Zero Gate Voltage Drain Current VDS = 16 V, VGS= 0 V 20 V 10 µA IGSSF Gate - Body Leakage, Forward VGS = 8 V, VDS = 0 V 100 nA IGSSR Gate - Body Leakage, Reverse VGS = -8 V, VDS = 0 V -100 nA V TJ =125°C ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA TJ =125°C RDS(ON) Static Drain-Source On-Resistance 0.5 0.7 1 0.3 0.53 0.8 0.15 0.21 0.24 0.4 0.11 0.16 VGS = 2.7 V, ID = 1.3 A TJ =125°C VGS = 4.5 V, ID = 1.5 A ID(ON) On-State Drain Current gFS Forward Transconductance VGS = 2.7 V, VDS = 5 V 3 VGS = 4.5 V, VDS = 5 V 4 Ω A VDS = 5 V, ID = 1.3 A, 3.5 S VDS = 10 V, VGS = 0 V, f = 1.0 MHz 162 pF 85 pF 28 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) tD(on) Turn - On Delay Time tr Turn - On Rise Time 5 20 ns 25 40 ns tD(off) tf Turn - Off Delay Time 10 20 ns Turn - Off Fall Time 5 20 ns 3.5 5 nC Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge VDD = 5 V, ID = 1 A, VGS = 5 V, RGen = 6 Ω VDS = 5 V, ID = 1.3 A, VGS = 4.5 V www.onsemi.com 2 0.3 nC 1 nC NDS331N N-Channel Logic Level Enhancement Mode Field Effect Transistor ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units 0.42 A 10 A 1.2 V DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Drain-Source Diode Forward Current ISM Maximum Pulsed Drain-Source Diode Forward Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 0.42 A (Note 2) 0.8 Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. PD(t ) = T J− TA R θJ A(t ) = T J−TA R θJ C+RθCA(t ) = I 2D (t ) × RDS (ON ) TJ Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 250oC/W when mounted on a 0.02 in2 pad of 2oz copper. b. 270oC/W when mounted on a 0.001 in2 pad of 2oz copper. 1a 1b Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. www.onsemi.com 3 NDS331N N-Channel Logic Level Enhancement Mode Field Effect Transistor Electrical Characteristics (TA = 25°C unless otherwise noted) I D , DRAIN-SOURCE CURRENT (A) VGS =4.5V 2.0 2.7 3.0 3 1.75 2.5 R DS(on) , NORMALIZED DRAIN-SOURCE ON-RESISTANCE 4 2 1.5 1 0 0 V DS 1 2 , DRAIN-SOURCE VOLTAGE (V) 1.5 VGS = 2.0V 1.25 2.5 0.5 3 0 RDS(on) , NORMALIZED 1.2 1 0.8 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 DRAIN-SOURCE ON-RESISTANCE R DS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 0.5 1 D 1.5 2 , DRAIN CURRENT (A) VGS = 2.7 V 2.5 3 1.25 25°C 1 -55°C 0.75 0.5 150 0 25°C I D, DRAIN CURRENT (A) V th, NORMALIZED 2 1 0.5 V GS 2.5 3 Figure 4. On-Resistance Variation with Drain Current and Temperature. 125°C 3 1 1.5 2 I , DRAIN CURRENT (A) 1.3 T = -55°C J V DS = 5.0V 0.5 D 1 1.5 2 , GATE TO SOURCE VOLTAGE (V) 2.5 GATE-SOURCE THRESHOLD VOLTAGE 4 TJ = 125°C 1.5 Figure 3. On-Resistance Variation with Temperature. 0 I 4.5 1.75 I D = 1.3A VGS = 2.7V 1.4 0 3.5 Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 1.8 0.6 -50 3.0 0.75 Figure 1. On-Region Characteristics. 1.6 2.7 1 I D = 250µA 1.1 1 0.9 0.8 0.7 0.6 0.5 -50 3 V DS = V GS 1.2 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 Figure 6. Gate Threshold Variation with Temperature. Figure 5. Transfer Characteristics. www.onsemi.com 4 150 NDS331N N-Channel Logic Level Enhancement Mode Field Effect Transistor Typical Electrical Characteristics I D = 250µA I , REVERSE DRAIN CURRENT (A) 1.08 1.04 1 0.96 0.92 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 0.1 TJ = 125°C 25°C 0.01 -55°C 0.001 0.0001 150 5 V GS , GATE-SOURCE VOLTAGE (V) 400 200 C iss 100 C oss 50 10 0.1 0.2 0.4 0.6 0.8 1 V , BODY DIODE FORWARD VOLTAGE (V) C rss f = 1 MHz V GS = 0V 0.2 V DS 0.5 1 2 5 , DRAIN TO SOURCE VOLTAGE (V) 10 3 2 1 0 1 R GEN 2 3 Q g , GATE CHARGE (nC) t d(on) RL tr 5 t off t d(off) tf 90% 90% V OUT VOUT 10% DUT G 4 Figure 10. Gate Charge Characteristics. t on D 10V 15V 4 VDD VGS V DS = 5V ID = 1.3A 0 20 Figure 9. Capacitance Characteristics. V IN 1.2 Figure 8. Body Diode Forward Voltage Variation with Source Current and Temperature. 600 20 0 SD Figure 7. Breakdown Voltage Variation with Temperature. CAPACITANCE (pF) V GS = 0V S BV DSS , NORMALIZED DRAIN-SOURCE BREAKDOWN VOLTAGE 1 1.12 10% 90% V IN S 50% 50% 10% PULSE WIDTH Figure 11. Switching Test Circuit. Figure 12. Switching Waveforms. www.onsemi.com 5 INVERTED NDS331N N-Channel Logic Level Enhancement Mode Field Effect Transistor Typical Electrical Characteristics (continued) VDS = 5.0V THIS AREA IS LIMITED BY rDS(on) 6 25°C 125°C 4 10 ID, DRAIN CURRENT (A) T J = -55°C 2 100 μs 1 ms 1 10 ms SINGLE PULSE TJ = MAX RATED 0.1 g 0 0 1 2 ID , DRAIN CURRENT (A) 3 RθJA = 270 oC/W 0.01 0.1 4 CURVE BENT TO MEASURED DATA 10 60 Figure 14. Maximum Safe Operating Area. 1.8 I D , STEADY-STATE DRAIN CURRENT (A) 1 0.8 1.6 0.6 1a 1.4 1b 0.4 1a 1.2 0.2 0 1 VDS, DRAIN to SOURCE VOLTAGE (V) Figure 13. Transconductance Variation with Drain Current and Temperature. STEADY-STATE POWER DISSIPATION (W) 100 ms TA = 25 oC FS , TRANSCONDUCTANCE (SIEMENS) 50 8 4.5"x5" FR-4 Board TA = 25 oC Still Air 0 0.1 0.2 0.3 2oz COPPER MOUNTING PAD AREA (in 2 ) 0.4 1 Figue 15. SuperSOTTM _ 3 Maximum Steady-State Power Dissipation. versus Copper Mounting Pad Area. 4.5"x5" FR-4 Board TA = 25 oC Still Air VGS = 2.7V 1b 0 0.1 0.2 0.3 2 2oz COPPER MOUNTING PAD AREA (in ) 0.4 Figure 16. Maximum Steady-State Drain Current versus Copper Mounting Pad. Area 2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 NOTES: 0.01 ZθJA(t) = r(t) x RθJA RθJA = 270 oC/W Peak TJ = PDM x ZθJA(t) + TA Duty Cycle, D = t1 / t2 SINGLE PULSE 0.001 -4 10 -3 10 -2 10 -1 10 1 10 t, RECTANGULAR PULSE DURATION (sec) Figure 17. Transient Thermal Response Curve. Note : Thermal characterization performed using the conditions described in note 1b. response will change depending on the circuit board design. www.onsemi.com 6 100 1000 NDS331N N-Channel Logic Level Enhancement Mode Field Effect Transistor Typical Electrical Characteristics (continued) ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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