NDS331N_D87Z

N-Channel Logic Level Enhancement Mode Field Effect Transistor NDS331N General Description These N−Channel logic level enhancement mode power field effect transistors are produced using ON Semiconductor’s proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on−state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMCIA cards, and other battery powered circuits where fast switching, and low in−line power loss are needed in a very small outline surface mount package. www.onsemi.com D G S SOT−23/SUPERSOT−23, 3 LEAD, 1.4x2.9 CASE 527AG Features • 1.3 A, 20 V MARKING DIAGRAM RDS(on) = 0.21  @ VGS = 2.7 V ♦ RDS(on) = 0.16  @ VGS = 4.5 V Industry Standard Outline SOT−23 Surface Mount Package Using Proprietary SUPERSOTt−3 Design for Superior Thermal and Electrical Capabilities High Density Cell Design for Extremely Low RDS(on) Exceptional On−Resistance and Maximum DC Current Capability This is a Pb−Free Device ♦ • • • • Drain 3 331M 1 Gate 2 Source M = Date Code D G S ORDERING INFORMATION Device NDS331N Package Shipping† SOT−23−3/ SUPERSOT−23 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2017 May, 2021 − Rev. 7 1 Publication Order Number: NDS331N/D NDS331N ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise noted. Parameter Symbol Ratings Unit 20 V VDSS Drain−Source Voltage VGSS Gate−Source Voltage − Continuous ±8 V Maximum Drain Current – Continuous (Note 1a) 1.3 A Maximum Drain Current – Pulsed 10 Maximum Power Dissipation (Note 1a) 0.5 Maximum Power Dissipation (Note 1b) 0.46 ID PD TJ, TSTG Operating and Storage Temperature Range −55 to +150 W °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL CHARACTERISTICS Symbol Parameter Ratings Unit RJA Thermal Resistance, Junction−to−Ambient (Note 1a) 250 °C/W RJC Thermal Resistance, Junction−to−Case (Note 1) 75 °C/W 1. RJA is the sum of the junction−to−case and case−to−ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RJC is guaranteed by design while RCA is determined by the user’s board design. P D(t) + TJ * TA R JA(t) + TJ * TA R JC ) R CA(t) + I 2D(t) R DS(on)@T J Typical RJA using the board layouts shown below on 4.5″x5″ FR−4 PCB in a still air environment: a) 250°C/W when mounted on a 0.02 in2 pad of 2oz copper. b) 270°C/W when mounted on a 0.001 in2 pad of 2oz copper. Scale 1:1 on letter size paper www.onsemi.com 2 NDS331N ELECTRICAL CHARACTERISTICS TA = 25°C unless otherwise noted. Symbol Parameter Test Conditions Min Typ Max Unit OFF CHARACTERISTICS BVDSS IDSS Drain–Source Breakdown Voltage VGS = 0 V, ID = 250 A 20 − − V Zero Gate Voltage Drain Current VDS = 16 V, VGS = 0 V − − 1 A VDS = 16 V, VGS = 0 V, TJ = 125°C − − 10 IGSSF Gate–Body Leakage, Forward VGS = 8 V, VDS = 0 V − − 100 nA IGSSR Gate–Body Leakage, Reverse VGS = −8 V, VDS = 0 V − − −100 nA VDS = VGS, ID = 250 A 0.5 0.7 1 V VDS = VGS, ID = 250 A, TJ = 125°C 0.3 0.53 0.8 VGS = 2.7 V, ID = 1.3 A − 0.15 0.21 VGS = 2.7 V, ID = 1.3 A, TJ = 125°C − 0.24 0.4 VGS = 4.5 V, ID = 1.5 A − 0.11 0.16 VGS = 2.7 V, VDS = 5 V 3 − − VGS = 4.5 V, VDS = 5 V 4 − − VDS = 5 V, ID = 1.3 A − 3.5 − S VDS = 10 V, VGS = 0 V, f = 1.0 MHz − 162 − pF ON CHARACTERISTICS (Note 2) VGS(th) RDS(on) ID(on) gFS Gate Threshold Voltage Static Drain–Source On–Resistance On–State Drain Current Forward Transconductance  A DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance − 85 − pF Crss Reverse Transfer Capacitance − 28 − pF − 5 20 ns − 25 40 ns − 10 20 ns − 5 20 ns − 3.5 5 nC SWITCHING CHARACTERISTICS (Note 2) tD(on) Turn–On Delay Time tr Turn–On Rise Time tD(off) Turn–Off Delay Time VDD = 5 V, ID = 1 A, VGS = 5 V, RGEN = 6  tf Turn–Off Fall Time Qg Total Gate Charge Qgs Gate–Source Charge − 0.3 − nC Qgd Gate–Drain Charge − 1 − nC Maximum Continuous Drain–Source Diode Forward Current − − 0.42 A ISM Maximum Pulsed Drain−Source Diode Forward Current − − 10 A VSD Drain–Source Diode Forward Voltage − 0.8 1.2 V VDS = 5 V, ID = 1.3 A, VGS = 4.5 V DRAIN−SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS VGS = 0 V, IS = 0.42 A (Note 2) Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Pulse Test: Pulse Width ≤ 300 s, Duty Cycle ≤ 2.0%. www.onsemi.com 3 NDS331N TYPICAL ELECTRICAL CHARACTERISTICS 2.5 3 2.7 3.0 1.75 VGS = 4.5 V 2.0 RDS(on), Normalized Drain−Source On−Resistance ID, Drain−Source Current (A) 4 2 1.5 1 0 1 0 2 1.5 VGS = 2.0 V 1.25 2.5 1 0.75 2.7 0.5 0 3 1 0.5 Figure 1. On−Region Characteristics RDS(on), Normalized Drain−Source On−Resistance RDS(on), Normalized Drain−Source On−Resistance 1.75 1.4 1.2 1 0.8 0.6 −50 −25 0 25 50 75 100 125 VGS = 2.7 V 25°C 1 −55°C 0.75 0.5 0 150 0.5 1 Vth, Normalized Gate−Source Threshold Voltage ID, Drain Current (A) 25°C 1 1.5 2.5 2 3 Figure 4. On−Resistance Variation with Drain Current and Temperature 2 1 1.5 ID, Drain Current (A) 125°C 0.5 TJ = 125°C 1.3 TJ = −55°C 3 0 0 3 1.25 Figure 3. On−Resistance Variation with Temperature VDS = 5.0 V 2.5 1.5 TJ, Junction Temperature (°C) 4 2 Figure 2. On−Resistance Variation with Drain Current and Gate Voltage ID = 1.3 A VGS = 2.7 V 1.6 1.5 4.5 3.5 ID, Drain Current (A) VDS, Drain−Source Voltage (V) 1.8 3.0 2 2.5 VDS = VGS ID = 250 A 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 −50 3 −25 0 25 50 75 100 TJ, Junction Temperature (°C) VGS, Gate To Source Voltage (V) Figure 5. Transfer Characteristics Figure 6. Gate Threshold Variation with Temperature www.onsemi.com 4 125 150 NDS331N TYPICAL ELECTRICAL CHARACTERISTICS (continued) 1 ID = 250 A IS, Reverse Drain Current (A) BVDSS, Normalized Drain−Source Breakdown Voltage 1.12 1.08 1.04 1 0.1 TJ = 125°C 0.01 −55°C −25 0 25 50 75 100 125 0.0001 150 0 0.2 Figure 7. Breakdown Voltage Variation with Temperature 5 VGS, Gate−Source Voltage (V) Capacitance (pF) Ciss 200 Coss 100 50 Crss f = 1 MHz VGS = 0 V 0.2 2 1 0.5 5 10 VDS = 5 V 2 1 0 1 2 3 5 Figure 10. Gate Charge Characteristics toff ton tr RL td(off) tf 90% 90% VOUT VOUT 10% 10% DUT G 4 Qg, Gate Charge (nC) td(on) RGEN 10 V 15 V VDD VGS 1.2 3 Figure 9. Capacitance Characteristics D 1 0.8 4 0 20 ID = 1.3 A VDS, Drain−Source Voltage (V) VIN 0.6 Figure 8. Body Diode Forward Voltage Variation with Source Current and Temperature 600 400 10 0.1 0.4 VSD, Body Diode Forward Voltage (V) TJ, Junction Temperature (°C) 20 25°C 0.001 0.96 0.92 −50 VGS = 0 V 90% S VIN 10% Figure 11. Switching Test Circuit 50% 50% Pulse Width Figure 12. Switching Waveforms www.onsemi.com 5 Inverted NDS331N TYPICAL ELECTRICAL CHARACTERISTICS (continued) 50 This Area is Limited by rDS(on) VDS = 5.0 V 10 TJ = −55°C 6 ID, Drain Current (A) gFS, Transconductance (Siemens) 8 25°C 4 125°C 2 0 0 2 1 3 100 s 1 ms 1 10 ms 0.1 0.01 0.1 4 60 Figure 14. Maximum Safe Operating Area 1 1.8 ID, Steady−State Drain Current (A) Steady−State Power Dissipation (W) 10 VDS, Drain to Source Voltage (V) Figure 13. Transconductance Variation with Drain Current and Temperature 0.8 0.6 1a 1b 0.4 4.5″x5″ FR−4 Board TA = 25°C Still Air 0.2 0 0.1 0.3 0.2 1.6 1.4 1a 1.2 1 0.4 0 1 0.1 0.1 0.2 0.4 Figure 16. Maximum Steady−State Drain Current versus Copper Mounting Pad Area Duty Cycle−Descending Order D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 NOTES: ZJA(t)= r(t) x RJA RJA = 270°C/W Peak TJ = PDM x ZJA(t) + TA Duty Cycle, D = t1 / t2 0.01 0.001 10−4 0.3 2oz Copper Mounting Pad Area (in2) Figure 15. SUPERSOT−3 Maximum Steady−State Power Dissipation versus Copper Mounting Pad Area 2 4.5″x5″ FR−4 Board TA = 25°C Still Air VGS = 2.7 V 1b 2oz Copper Mounting Pad Area (in2) ZJA, Normalized Thermal Impedance Curve Bent to Measured Date 1 ID, Drain Current (A) 0 100 ms Single Pulse TJ = Max Rated RJA = 270°C/W TA = 25°C Single Pulse 10−3 10−2 10−1 1 10 t, Rectangular Pulse Duration (s) Figure 17. Transient Thermal Response Curve NOTE: Thermal characterization performed using the conditions described in Note 1b. Response will change depending on the circuit board design. www.onsemi.com 6 100 1000 NDS331N SUPERSOT is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 7 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOT−23/SUPERSOTt−23, 3 LEAD, 1.4x2.9 CASE 527AG ISSUE A GENERIC MARKING DIAGRAM* XXXMG G DOCUMENT NUMBER: DESCRIPTION: XXX = Specific Device Code M = Month Code G = Pb−Free Package (Note: Microdot may be in either location) 98AON34319E DATE 09 DEC 2019 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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