NE5534, SA5534, SE5534,
NE5534A, SA5534A,
SE5534A
Operational Amplifier, Low
Noise, Single
The NE/SA/SE5534/5534A are single high-performance low noise
operational amplifiers. Compared to other operational amplifiers,
such as TL083, they show better noise performance, improved output
drive capability, and considerably higher small-signal and power
bandwidths.
This makes the devices especially suitable for application in high
quality and professional audio equipment, in instrumentation and
control circuits and telephone channel amplifiers. The op amps are
internally compensated for gain equal to, or higher than, three. The
frequency response can be optimized with an external compensation
capacitor for various applications (unity gain amplifier, capacitive
load, slew rate, low overshoot, etc.).
http://onsemi.com
SOIC−8
D SUFFIX
CASE 751
8
1
PDIP−8
N SUFFIX
CASE 626
8
1
Features
•
•
•
•
•
•
•
•
•
Small-Signal Bandwidth: 10 MHz
Output Drive Capability: 600 W, 10 VRMS at VS = "18 V
Input Noise Voltage: 4 nVń ǸHz
DC Voltage Gain: 100000
AC Voltage Gain: 6000 at 10 kHz
Power Bandwidth: 200 kHz
Slew Rate: 13 V/ms
Large Supply Voltage Range: "3.0 to "20 V
Pb−Free Packages are Available
July, 2012 − Rev. 3
BALANCE
1
8
BALANCE/
COMPENSATION
INVERTING INPUT
2
7
V+
NON-INVERTING
3
6
OUTPUT
V−
4
5
COMPENSATION
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 8 of this data sheet.
Audio Equipment
Instrumentation and Control Circuits
Telephone Channel Amplifiers
Medical Equipment
© Semiconductor Components Industries, LLC, 2012
D, N Packages
Top View
Applications
•
•
•
•
PIN CONNECTIONS
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
1
Publication Order Number:
NE5534/D
NE5534, SA5534, SE5534, NE5534A, SA5534A, SE5534A
8
1
5
7
2
3
6
4
Figure 1. Equivalent Schematic
MAXIMUM RATINGS
Symbol
Value
Unit
Supply Voltage
Rating
VS
"22
V
Input Voltage
VIN
"V Supply
V
Differential Input Voltage (Note 1)
VDIFF
"0.5
V
Operating Temperature Range
NE
SA
SE
Tamb
Storage Temperature Range
Tstg
−65 to +150
°C
Tj
150
°C
Junction Temperature
Power Dissipation at 25°C
Thermal Resistance, Junction−to−Ambient
PD
N Package
D Package
RqJA
N Package
D Package
Output Short-Circuit Duration (Note 2)
Lead Soldering Temperature (10 sec max)
0 to +70
−40 to +85
−55 to +125
1150
750
130
158
°C
mW
°C/W
−
Indefinite
−
Tsld
230
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Diodes protect the inputs against overvoltage. Therefore, unless current-limiting resistors are used, large currents will flow if the differential input
voltage exceeds 0.6 V. Maximum current should be limited to "10 mA.
2. Output may be shorted to ground at VS = "15 V, Tamb = 25°C. Temperature and/or supply voltages must be limited to ensure dissipation rating
is not exceeded.
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2
NE5534, SA5534, SE5534, NE5534A, SA5534A, SE5534A
DC ELECTRICAL CHARACTERISTICS (Tamb = 25°C; VS = "15 V, unless otherwise noted.) (Notes 3, 4 and 5)
NE/SA5534/5534A
Characteristic
Min
Typ
Max
Min
Typ
Max
Unit
−
0.5
4.0
−
0.5
2.0
mV
−
−
5.0
−
−
3.0
mV
DVOS/DT
−
5.0
−
−
5.0
−
mV/°C
IOS
−
20
300
−
10
200
nA
−
−
400
−
−
500
nA
DIOS/DT
−
200
−
−
200
−
pA/°C
IB
−
500
1500
−
400
800
nA
−
−
2000
−
−
1500
nA
DIB/DT
−
5.0
−
−
5.0
−
nA/°C
ICC
−
−
4.0
−
8.0
10
−
−
4.0
−
6.5
9.0
mA
"12
70
−
"13
100
10
−
−
100
"12
80
−
"13
100
10
−
−
50
V
dB
mV/V
RL ≥ 600 W,
VO = "10 V
Overtemperature
25
100
−
50
100
−
V/mV
15
−
−
25
−
−
RL w 600 W
"12
"13
−
"12
"13
−
Overtemperature
RL w 600 W;
VS = "18 V
RL w 2.0 kW
Overtemperature
"10
"15
"12
"16
−
−
"10
"15
"12
16
−
−
"13
"12
"13.5
"12.5
−
−
"13
"12
"13.5
"12.5
−
−
Symbol
Test Conditions
VOS
Offset Voltage
Overtemperature
Offset Current
Overtemperature
Input Current
Supply Current
Per Op Amp
Common Mode Input Range
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Large-Signal Voltage Gain
Output Swing
SE5534/5534A
Overtemperature
Overtemperature
VCM
CMRR
PSRR
AVOL
VOUT
V
Input Resistance
RIN
30
100
−
50
100
−
kW
Output Short Circuit Current
ISC
−
38
−
−
38
−
mA
3. For NE5534/5534A, TMIN = 0°C, TMAX = 70°C.
4. For SA5534/5534A, TMIN = −40°C, TMAX = +85°C.
5. For SE5534/5534A, TMIN = −55°C, TMAX = +125°C.
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3
NE5534, SA5534, SE5534, NE5534A, SA5534A, SE5534A
AC ELECTRICAL CHARACTERISTICS (Tamb = 25°C; VS = "15 V, unless otherwise noted.)
NE/SA5534/5534A
Characteristic
Output Resistance
SE5534/5534A
Symbol
Test Conditions
Min
Typ
Max
Min
Typ
Max
Unit
ROUT
AV = 30 dB
closed-loop
f = 10 kHz;
RL = 600 W;
CC = 22 pF
−
0.3
−
−
0.3
−
W
Transient Response
Voltage-follower,
VIN = 50 mV
RL = 600 W,
CC = 22 pF,
CL = 100 pF
Rise Time
tR
−
20
−
−
20
−
ns
Overshoot
−
−
20
−
−
20
−
%
Transient Response
VIN = 50 mV,
RL = 600 W,
CC = 47 pF,
CL = 500 pF
Rise Time
tR
−
50
−
−
50
−
ns
Overshoot
−
−
35
−
−
35
−
%
Gain
Gain Bandwidth Product
Slew Rate
Power Bandwidth
AV
f = 10 kHz, CC = 0
f = 10 kHz,
CC = 22 pF
−
−
6.0
2.2
−
−
−
−
6.0
2.2
−
−
V/mV
GBW
CC = 22 pF,
CL = 100 pF
−
10
−
−
10
−
MHz
SR
CC = 0
CC = 22 pF
−
−
13
6.0
−
−
−
−
13
6.0
−
−
V/ms
−
VOUT = "10 V,
CC = 0 pF
VOUT = "10 V,
CC = 22 pF
VOUT = "14 V,
RL = 600 W,
CC = 22 pF,
VCC = "18 V
−
200
−
−
200
−
kHz
−
95
−
−
95
−
−
70
−
−
70
−
ELECTRICAL CHARACTERISTICS (Tamb = 25°C; VS = 15 V, unless otherwise noted.)
NE/SA/SE5534
NE/SA/SE5534A
Symbol
Test Conditions
Min
Typ
Max
Min
Typ
Max
Unit
Input Noise Voltage
VNOISE
fO = 30 Hz
fO = 1.0 kHz
−
−
7.0
4.0
−
−
−
−
5.5
3.5
7.0
4.5
nV/√Hz
Input Noise Current
INOISE
fO = 30 Hz
fO = 1.0 kHz
−
−
2.5
0.6
−
−
−
−
1.5
0.4
−
−
pA/√Hz
Broadband Noise Figure
−
f = 10 Hz to
20 kHz;
RS = 5.0 kW
−
−
−
−
0.9
−
dB
Channel Separation
−
f = 1.0 kHz;
RS = 5.0 kW
−
110
−
−
110
−
dB
Characteristic
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4
NE5534, SA5534, SE5534, NE5534A, SA5534A, SE5534A
TYPICAL PERFORMANCE CHARACTERISTICS
16
TYPICAL VALUES
GAIN (dB)
80
12
CC = 0
CC = 22pF
40
TYPICAL VALUES
5
CC = 0; RF = 10kW; RE = 100W
40
8
S 8
(V/ms)
CC = 0; RF = 9kW; RE = 1kW
20
TYP
0
-40
60
VS = +15V
CC
GAIN (dB)
120
4
102
10
103
104
105
106
0
107
0
40
-20
103
80
Figure 2. Open-Loop
Frequency Response
CC =
0pF
22pF
47pF
VS = +15V
1,2
IO
40
(mA)
II
(mA)
TYP
106
0
-55
107
Figure 5. Large−Signal
Frequency Response
0
-25
0
25
50
75
100
-55
+125
-25
0
TYP
4
10
IP
IN
POS
(mA)
10
100 +125
102
IO = 0
NEG
75
50
Figure 7. Input Bias
Current
6
TYPICAL VALUES
25
Tamb (oC)
Figure 6. Output
Short−Circuit Current
30
VIN (V)
TYP
Tamb (oC)
f (Hz)
20
0,8
0,4
20
10
108
1,4
60
105
107
VS = +15V
30
104
106
Figure 4. Closed−Loop
Frequency Response
80
VS = +15V
TYPICAL VALUES
103
105
f (Hz)
Figure 3. Slew Rate as a
Function of Compensation
Capacitance
40
0
102
104
CC(pF)
f (Hz)
(V)
Vo(p-p) 20
CC = 22pF; RF = 1kW; RE = ∞
0
TYP
(nVń ǸHz) 1
2
10−1
0
0
10
20
Vp; -VN (V)
Figure 8. Input Common−Mode
Voltage Range
0
0
10
20
Vp; -VN (V)
Figure 9. Supply Current
Per Op Amp
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5
10−2
10
102
103
f (Hz)
Figure 10. Input Noise
Voltage Density
104
NE5534, SA5534, SE5534, NE5534A, SA5534A, SE5534A
TYPICAL PERFORMANCE CHARACTERISTICS
102
106
102
TYPICAL VALUES
105
104
10
TYP
10Hz TO 20kHz
1kHz
Vn(rms)
(mV)
200Hz TO 4kHz
10−1
1
THERMAL NOISE
OF SOURCE
RESISTANCE
10−1
10
102
f (Hz)
1
10
10−1
10−2
10
10Hz
Vn(rms) 103
(nVń ǸHz)
102
In(rms)
(pAń ǸHz) 1
TYPICAL VALUES
103
Figure 11. Input Noise
Current Density
104
10−2
10
102
103
104
RS (W)
105
Figure 12. Total Input
Noise Density
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6
106
10−2
0
10
RS (W)
20
Figure 13. Broadband Input
Noise Voltage
NE5534, SA5534, SE5534, NE5534A, SA5534A, SE5534A
TEST LOAD CIRCUITS
V+
CC
22kW
100kW
2
CC
5
5534
3
RS
25W
1
2
8
+
6
RF
8
5
7
6
5534
3
+
VI
RE
100pF
600W
4
V-
Figure 14. Frequency Compensation and
Offset Voltage Adjustment Circuit
CAL
OSC
Figure 15. Closed-Loop Frequency Response
POWER
SUPPLY
+VCC
-VCC
(nVń ǸHz)
CAL
METER
BANDPASS
AT 1kHz
1W
+
DUT
10kW
(nVń ǸHz)
+40dB
BANDPASS
AT 30Hz
100W
TEST BOARD
GND
Figure 16. Noise Test Block Diagram
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7
NE5534, SA5534, SE5534, NE5534A, SA5534A, SE5534A
MARKING DIAGRAMS
8
1
8
N5234
ALYWA
G
1
8
S5234
ALYWA
G
1
NE5234xN
AWL
YYWWG
S5234
ALYW
G
SOIC−8
D SUFFIX
CASE 751
SA5234xN
AWL
YYWWG
SE5234xN
AWL
YYWWG
PDIP−8
N SUFFIX
CASE 626
x
A
WL, L
YY, Y
WW, W
G or G
= Blank or A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Description
Temperature Range
Shipping†
8−Pin Plastic Small Outline (SO−8) Package
0 to +70°C
98 Units / Rail
NE5534ADG
8−Pin Plastic Small Outline (SO−8) Package (Pb−Free)
0 to +70°C
98 Units / Rail
NE5534ADR2
8−Pin Plastic Small Outline (SO−8) Package
0 to +70°C
2500 / Tape & Reel
8−Pin Plastic Small Outline (SO−8) Package (Pb−Free)
0 to +70°C
2500 / Tape & Reel
8−Pin Plastic Dual In−Line Package (PDIP−8)
0 to +70°C
50 Units / Rail
8−Pin Plastic Dual In−Line Package (PDIP−8) (Pb−Free)
0 to +70°C
50 Units / Rail
8−Pin Plastic Small Outline (SO−8) Package
0 to +70°C
98 Units / Rail
8−Pin Plastic Small Outline (SO−8) Package (Pb−Free)
0 to +70°C
98 Units / Rail
Device
NE5534AD
NE5534ADR2G
NE5534AN
NE5534ANG
NE5534D
NE5534DG
NE5534DR2
8−Pin Plastic Small Outline (SO−8) Package
0 to +70°C
2500 / Tape & Reel
8−Pin Plastic Small Outline (SO−8) Package (Pb−Free)
0 to +70°C
2500 / Tape & Reel
8−Pin Plastic Dual In−Line Package (PDIP−8)
0 to +70°C
50 Units / Rail
NE5534NG
8−Pin Plastic Dual In−Line Package (PDIP−8) (Pb−Free)
0 to +70°C
50 Units / Rail
SA5534AD
8−Pin Plastic Small Outline (SO−8) Package
−40 to +85°C
98 Units / Rail
8−Pin Plastic Small Outline (SO−8) Package (Pb−Free)
−40 to +85°C
98 Units / Rail
NE5534DR2G
NE5534N
SA5534ADG
SA5534ADR2
SA5534ADR2G
SA5534AN
SA5534ANG
SA5534N
SA5534NG
SE5534AN
SE5534ANG
SE5534N
SE5534NG
8−Pin Plastic Small Outline (SO−8) Package
−40 to +85°C
2500 / Tape & Reel
8−Pin Plastic Small Outline (SO−8) Package (Pb−Free)
−40 to +85°C
2500 / Tape & Reel
8−Pin Plastic Dual In−Line Package (PDIP−8)
−40 to +85°C
50 Units / Rail
8−Pin Plastic Dual In−Line Package (PDIP−8) (Pb−Free)
−40 to +85°C
50 Units / Rail
8−Pin Plastic Dual In−Line Package (PDIP−8)
−40 to +85°C
50 Units / Rail
8−Pin Plastic Dual In−Line Package (PDIP−8) (Pb−Free)
−40 to +85°C
50 Units / Rail
8−Pin Plastic Dual In−Line Package (PDIP−8)
−55 to +125°C
50 Units / Rail
8−Pin Plastic Dual In−Line Package (PDIP−8) (Pb−Free)
−55 to +125°C
50 Units / Rail
8−Pin Plastic Dual In−Line Package (PDIP−8)
−55 to +125°C
50 Units / Rail
8−Pin Plastic Dual In−Line Package (PDIP−8) (Pb−Free)
−55 to +125°C
50 Units / Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−8
CASE 626−05
ISSUE P
DATE 22 APR 2015
SCALE 1:1
D
A
E
H
8
5
E1
1
4
NOTE 8
b2
c
B
END VIEW
TOP VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
D1
M
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NOTE 6
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN
3. DC − IN
4. AC IN
5. GROUND
6. OUTPUT
7. AUXILIARY
8. VCC
XXXXXXXXX
AWL
YYWWG
XXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42420B
PDIP−8
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
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