ASPM34 Series
Automotive 3-Phase 1200 V
50 A IGBT Intelligent Power
Module
NFVA25012NP2T
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General Description
NFVA25012NP2T is an advanced Auto IPM module providing a
fully−featured, high−performance inverter output stage for hybrid and
electric vehicles. These modules integrate optimized gate drive of the
built−in IGBTs to minimize EMI and losses, while also providing
multiple on−module protection features including under−voltage
lockouts, over−current shutdown, thermal monitoring of drive IC, and
fault reporting. The built−in, high−speed HVIC requires only a single
supply voltage and translates the incoming logic−level gate inputs to
the high−voltage, high−current drive signals required to properly drive
the module’s internal IGBTs. Separate negative IGBT terminals are
available for each phase to support the widest variety of control
algorithms.
Features
• Automotive SPM® in 34 Pin DIP Package
• AEC & AQG324 Qualified and PPAP Capable
• 1200 V − 50 A 3−Phase IGBT Inverter with Integral Gate Drivers
•
•
•
•
•
•
•
•
•
and Protection
Low−Loss, Short−Circuit Rated IGBTs
Very Low Thermal Resistance Using AlN DBC Substrate
Built−In Bootstrap Diodes and Dedicated Vs Pins Simplify PCB
Layout
Separate Open−Emitter Pins from Low−Side IGBTs for Three−Phase
Current Sensing
Single−Grounded Power Supply Supported
Built−In NTC Thermistor for Temperature Monitoring and
Management
Adjustable Over−Current Protection via Integrated Sense−IGBTs
Isolation Rating of 2500 Vrms / 1 min
This is a Pb−Free Device
• Automotive High Voltage Auxiliary Motors
Climate E−Compressors
Oil / Water Pumps
♦ Super / Turbo Chargers
♦ Variety Fans
Motion Control
♦ Industrial Motor
♦
♦
© Semiconductor Components Industries, LLC, 2019
May, 2020 − Rev. 0
DIP34 80x33, AUTOMOTIVE MODULE
CASE MODGL
MARKING DIAGRAM
XXXXXXXXXXXX
ZZZ
AT
Y
W
NNN
Applications
•
3D Package Drawing
(Click to Activate 3D Content)
= Specific Device Code
= Lot ID
= Assembly & Test Location
= Year
= Work Week
= Serial Number
ORDERING INFORMATION
See detailed ordering and shipping information on page 14 of
this data sheet.
1
Publication Order Number:
NFVA25012NP2T/D
NFVA25012NP2T
Related Resources
Integrated Drive, Protection and System Control
Functions
• AN−9075 − Users Guide for 1200V SPM® 2 Series
• AN−9076 − Mounting Guide for New SPM® 2 Package
• AN−9079 − Thermal Performance of 1200 V Motion
•
•
• For inverter high−side IGBTs: gate drive circuit,
SPM® 2
Series by Mounting Torque
Integrated Power Functions
Integrated Drive, Protection, and System Control
Functions
•
Integrated Power Functions
•
• 1200 V - 50 A IGBT inverter for three−phase DC / AC
power conversion (Please refer to Figure 1)
•
high−voltage isolated high−speed level shifting
control circuit Under−Voltage Lock−Out Protection
(UVLO)
For inverter low−side IGBTs: gate drive circuit,
Short−Circuit Protection (SCP)
control supply circuit Under−Voltage Lock−Out
Protection (UVLO)
Fault signaling: corresponding to UVLO (low−side
supply) and SC faults
Input interface: active−HIGH interface, works with 3.3 /
5 V logic, Schmitt−trigger input
PIN CONFIGURATION
(34) V S(W)
(33) V B(W)
(32) V BD(W)
(31) V DD(WH)
(30) IN (WH)
(1) P
(29) V S(V)
(28) V B(V)
(2) W
(27) V BD(V)
(26) V DD(VH)
(25) IN (VH)
(24) V S(U)
(23) V B(U)
(3) V
Case Temperature (TC)
Detecting Point
(22) V BD(U)
(21) V DD(UH)
(20) COM (H)
(19) IN (UH)
(4) U
(18) R SC
(5) N W
(17) C SC
(6) N V
(16) C FOD
(15) V FO
(14) IN (WL)
(13) IN (VL)
(12) IN (UL)
(11) COM (L)
(10) VDD(L)
(7) N U
(8) RTH
(9) VTH
Figure 1. Pin Configuration − Top View
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NFVA25012NP2T
PIN DESCRIPTION
Pin Number
Pin Name
Pin Description
1
P
Positive DC−Link Input
2
W
Output for W Phase
3
V
Output for V Phase
4
U
5
NW
Negative DC−Link Input for W Phase
Output for U Phase
6
NV
Negative DC−Link Input for V Phase
7
NU
Negative DC−Link Input for U Phase
8
RTH
Series Resistor for Thermistor (Temperature Detection)
9
VTH
Thermistor Bias Voltage
10
VDD(L)
Low−Side Bias Voltage for IC and IGBTs Driving
11
COM(L)
Low−Side Common Supply Ground
12
IN(UL)
Signal Input for Low−Side U Phase
13
IN(VL)
Signal Input for Low−Side V Phase
14
IN(WL)
Signal Input for Low−Side W Phase
15
VFO
16
CFOD
Capacitor for Fault Output Duration Selection
17
CSC
Shut Down Input for Short−Circuit Current Detection Input
18
RSC
Resistor for Short−Circuit Current Detection
Fault Output
19
IN(UH)
Signal Input for High−Side U Phase
20
COM(H)
High−Side Common Supply Ground
21
VDD(UH)
High−Side Bias Voltage for U Phase IC
22
VBD(U)
Anode of Bootstrap Diode for U Phase High−Side Bootstrap Circuit
23
VB(U)
High−Side Bias Voltage for U Phase IGBT Driving
24
VS(U)
High−Side Bias Voltage Ground for U Phase IGBT Driving
25
IN(VH)
26
VDD(VH)
Signal Input for High−Side V Phase
27
VBD(V)
Anode of Bootstrap Diode for V Phase High−Side Bootstrap Circuit
28
VB(V)
High−Side Bias Voltage for V Phase IGBT Driving
29
VS(V)
High−Side Bias Voltage Ground for V Phase IGBT Driving
30
IN(WH)
31
VDD(WH)
32
VBD(W)
Anode of Bootstrap Diode for W Phase High−Side Bootstrap Circuit
33
VB(W)
High−Side Bias Voltage for W Phase IGBT Driving
34
VS(W)
High−Side Bias Voltage Ground for W Phase IGBT Driving
High−Side Bias Voltage for V Phase IC
Signal Input for High−Side W Phase
High−Side Bias Voltage for W Phase IC
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NFVA25012NP2T
INTERNAL EQUIVALENT CIRCUIT AND INPUT/OUTPUT PINS
(33) V B(W)
(32) V BD(W)
(31) V DD(WH)
(30) IN (WH)
(34) V S(W)
(28) V B(V)
(27) V BD(V)
(26) V DD(VH)
(25) IN (VH)
(29) V S(V)
(23) V B(U)
(22) V BD(U)
(21) V DD(UH)
(20) COM (H)
(19) IN (UH)
(24) V S(U)
P (1)
VB
VDD
COM
IN
VB
VDD
COM
IN
VDD
COM
IN
OUT
HVIC
VS
U (4)
C FOD
OUT
N W (5)
V FO
(14) IN (WL)
IN
(13) IN (VL)
IN
(12) IN (UL)
IN
(10) V DD(L)
VS
VB
(16) C FOD
(L)
OUT
HVIC
V (3)
C SC
(11) COM
VS
W (2)
(17) C SC
(15) V FO
OUT
HVIC
OUT
LVIC
N V (6)
COM
OUT
VDD
N U (7)
Thermistor
RTH (8)
VTH (9)
(18) R SC
NOTES:
1. nverter low−side is composed of three IGBTs, freewheeling diodes for each IGBT, and one control IC. It has gate drive and protection
functions.
2. nverter power side is composed of four inverter DC−link input terminals and three inverter output terminals.
3. Inverter high−side is composed of three IGBTs, freewheeling diodes, and three drive ICs for each IGBT.
Figure 2. Internal Block Diagram
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NFVA25012NP2T
ABSOLUTE MAXIMUM RATINGS (Tj = 25°C unless otherwise noted)
Symbol
Rating
Conditions
Rating
Unit
INVERTER PART
VPN
VPN(Surge)
VCES
Supply Voltage
Applied between P − NU, NV, NW
900
V
Supply Voltage (Surge)
Applied between P − NU, NV, NW
1000
V
1200
V
Collector − Emitter Voltage
±IC
Each IGBT Collector Current
TC = 100°C, TJ ≤ 150°C, VDD ≥ 15 V (Note 4)
50
A
±ICP
Each IGBT Collector Current (Peak)
TC = 25°C, TJ ≤ 150°C, Under 1 ms Pulse Width
(Note 4)
75
A
PC
Collector Dissipation
TC = 25°C per One Chip (Note 4)
347
W
TJ
Operating Junction Temperature
VCES = 960 V
−40~150
°C
VCES = 1200 V
−40~125
°C
CONTROL PART
VDD
Control Supply Voltage
Applied between VDD(H), VDD(L) − COM
20
V
VBS
High−Side Control Bias Voltage
Applied between VB(U) − VS(U), VB(V) − VS(V),
VB(W) − VS(W)
20
V
VIN
Input Signal Voltage
Applied between IN(UH), IN(VH), IN(WH), IN(UL),
IN(VL), IN(WL) − COM
−0.3~VDD + 0.3
V
VFO
Fault Output Supply Voltage
Applied between VFO − COM
−0.3~VDD + 0.3
V
IFO
Fault Output Current
Sink Current at VFO pin
2
mA
VSC
Current Sensing Input Voltage
Applied between CSC − COM
−0.3~VDD + 0.3
V
1200
V
BOOSTSTRAP DIODE PART
VRRM
Maximum Repetitive Reverse Voltage
IF
Forward Current
TC = 25°C, TJ ≤ 150°C (Note 4)
1.0
A
IFP
Forward Current (Peak)
TC = 25°C, TJ ≤ 150°C, Under 1 ms Pulse Width
(Note 4)
2.0
A
TJ
Operating Junction Temperature (Note 6)
−40~150
°C
3
ms
−40~150
°C
2500
Vrms
TOTAL SYSTEM
tSC
Short Circuit Withstand Time
TSTG
Storage Temperature
VISO
Isolation Voltage
VDD = VBS ≤ 16.5 V, VPN ≤ 800 V,
TJ = 150°C
Non−repetitive
60 Hz, Sinusoidal, AC 1 minute, Connection Pins
to Heat Sink Plate
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
4. These values had been made an acquisition by the calculation considered to design factor.
THERMAL RESISTANCE
Symbol
Rth(j−c)Q
Rth(j−c)F
Ls
Parameter
Junction to Case Thermal
Resistance (Note 5)
Package Stray Inductance
Conditions
Min
Typ
Max
Unit
Inverter IGBT part (per 1 / 6 module)
−
−
0.36
°C/W
Inverter FWD part (per 1 / 6 module)
−
−
0.66
°C/W
P to NU, NV, NW (Note 6)
−
32
−
nH
5. For the measurement point of case temperature (TC), please refer to Figure 1. DBC discoloration and Picker Circle Printing allowed, please
refer to application note AN−9190 (Impact of DBC Oxidation on SPM® Module Performance).
6. Stray inductance per phase measured per IEC 60747−15.
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NFVA25012NP2T
ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Collector −Emitter Saturation VDD = VBS = 15 V, VIN = 5 V, IC = 50 A, TJ = 25°C
Voltage
VDD = VBS = 15 V, VIN = 5 V, IC = 50 A, TJ = 150°C
−
2.20
2.80
V
−
2.75
3.25
V
FWDi Forward Voltage
VIN = 0 V, IF = 50 A, TJ = 25°C
−
2.40
3.00
V
VIN = 0 V, IF = 50 A, TJ = 150°C
−
2.25
2.85
V
0.90
1.40
2.00
ms
−
0.50
0.95
ms
−
1.10
1.70
ms
−
0.15
0.55
ms
INVERTER PART (Tj as specified)
VCE(SAT)
VF
HS
tON
High Side Switching Times
VPN = 600 V, VDD = 15 V, IC = 50 A, TJ = 25°C
VIN = 0 V ↔ 5 V, Inductive Load
See Figure 4
(Note 7)
tC(ON)
tOFF
tC(OFF)
trr
LS
−
0.20
−
ms
0.50
1.00
1.60
ms
−
0.50
0.95
ms
−
1.10
1.70
ms
tC(OFF)
−
0.15
0.55
ms
trr
−
0.25
−
ms
−
−
3
mA
tON
Low Side Switching Times
VPN = 600 V, VDD = 15 V, IC = 50 A, TJ = 25°C
VIN = 0 V ↔ 5 V, Inductive Load
See Figure 4
(Note 7)
tC(ON)
tOFF
ICES
Collector − Emitter Leakage
Current
Tj = 25°C, VCE = VCES
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. tON and tOFF include the propagation delay time of the internal drive IC. tC(ON) and tC(OFF) are the switching time of IGBT itself under the given
gate driving condition internally. For the detailed information, please see Figure 3.
100% IC 100% IC
t rr
VCE
IC
IC
VIN
VIN
t ON
10% IC
VIN(ON)
VCE
t OFF
t C(ON)
90% IC
t C(OFF)
VIN(OFF)
10% VCE
(a) turn-on
10% VCE
(b) turn-off
Figure 3. Switching Time Definition
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10% IC
NFVA25012NP2T
One−Leg Diagram of ASPM34
R BS
P
C BS
VB
VDD
COM
OUT
LS Switching
VS
IN
HS Switching
0V
VPN
U,V,W
V DD
V FO
C FOD
VIN
VDD
4.7 kΩ
600 V
HS Switching
OUT
C SC
V
COM
15 V
V
Inductor
IN
LS Switching
5V
IC
NU,V,W
V
R SC
5V
Figure 4. Example Circuit of Switching Test
Inductive Load, VPN = 600 V, VCC = 15 V, Tj = 1505C
Switching Loss, ESW [mJ]
Switching Loss, ESW [mJ]
Inductive Load, VPN = 600 V, VCC = 15 V, Tj = 255C
Collector Current, IC [A]
Collector Current, IC [A]
Figure 5. Switching Loss Characteristics
R−T Curve
600
550
16
450
400
Resistance [kW]
Resistance [kW]
R−T Curve in 505C ~ 1255C
20
500
350
300
250
200
12
8
4
0
50
60
150
70
80
90 100
Temperature [°C]
110
120
100
50
0
−20 −10
0
10
20
30
40 50 60 70
Temperature [°C]
80
90 100 110 120
Figure 6. R−T Curve of Built−in Thermistor
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NFVA25012NP2T
ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
BOOTSTRAP DIODE PART (Tj as specified)
VF
Forward Voltage
IF = 1.0 A, TJ = 25°C
−
2.2
−
V
trr
Reverse−Recovery Time
IF = 1.0 A, dIF / dt = 50 A/ms, TJ = 25°C
−
80
−
ns
CONTROL PART (Tj = 25°C unless otherwise noted)
IQDDH
Quiescent VDD Supply
Current
IQDDL
IPDDH
Operating VDD Supply
Current
IPDDL
VDD(UH,VH,WH) = 15 V,
IN(UH,VH,WH) = 0 V
VDD(UH) − COM(H),
VDD(VH) − COM(H),
VDD(WH) − COM(H)
−
−
0.15
mA
VDD(L) = 15 V, IN(UL,VL, WL) = 0 V
VDD(L) − COM(L)
−
−
4.80
mA
VDD(UH,VH,WH) = 15 V,
fPWM = 20 kHz, Duty = 50%,
Applied to one PWM Signal Input
for High−Side
VDD(UH) − COM(H),
VDD(VH) − COM(H),
VDD(WH) − COM(H)
−
−
0.30
mA
VDD(L) = 15V, fPWM = 20 kHz,
Duty = 50%, Applied to one PWM
Signal Input for Low−Side
VDD(L) − COM(L)
−
−
15.5
mA
IQBS
Quiescent VBS Supply
Current
VBS = 15 V, IN(UH,VH,WH) = 0 V
VB(U) − VS(U),
VB(V) − VS(V),
VB(W) − VS(W)
−
−
0.30
mA
IPBS
Operating VBS Supply
Current
VDD = VBS = 15 V, fPWM = 20 kHz,
Duty = 50%, Applied to one PWM
Signal Input for High−Side
VB(U) − VS(U),
VB(V) − VS(V),
VB(W) − VS(W)
−
−
12.0
mA
VFOH
Fault Output Voltage
VDD = 15 V, VSC = 0 V, VFO Circuit: 4.7 kW to 5 V Pull−up
4.5
−
−
V
VDD = 15 V, VSC = 1 V, VFO Circuit: 4.7 kW to 5 V Pull−up
−
−
0.5
V
−
43
−
mA
0.43
0.50
0.57
V
−
75
−
A
VFOL
ISEN
Sensing Current of Each
Sense IGBT
VDD = 15 V, VIN = 5 V, RSC = 0 W,
No Connection of Shunt Resistor
at NU,V,W Terminal
IC = 50 A
Short Circuit Trip Level
VDD = 15 V (Note 8)
CSC − COM(L)
ISC
Short Circuit Current Level
for Trip
RSC = 13 W (±1%), No Connection of Shunt Resistor
at NU,V,W Terminal (Note 8)
UVDDD
Supply Circuit
Under−Voltage Protection
Detection Level
10.3
−
12.8
V
VSC(ref)
UVDDR
Reset Level
10.8
−
13.3
V
UVBSD
Detection Level
9.5
−
12.0
V
UVBSR
Reset Level
10.0
−
12.5
V
50
−
−
ms
1.7
−
−
ms
−
−
2.6
V
0.8
−
−
V
−
47
−
kW
−
2.9
−
kW
tFOD
Fault−Out Pulse Width
(Note 9)
CFOD = Open
CFOD = 2.2 nF
VIN(ON)
ON Threshold Voltage
VIN(OFF)
OFF Threshold Voltage
RTH
Resistance of Thermistor
Applied between IN(UH,VH,WH) − COM(H),
IN(UL,VL,WL) − COM(L)
See Figure 6
(Note 10)
at TTH = 25°C
at TTH = 100°C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Short−circuit current protection functions only at the low−sides because the sense current is divided from main current at low−side IGBTs.
Inserting the shunt resistor for monitoring the phase current at NU, NV, NW terminal, the trip level of the short−circuit current is changed.
9. The fault−out pulse width tFOD depends on the capacitance value of CFOD according to the following approximate equation:
tFOD = 0.8 x 106 x CFOD [s].
10. TTH is the temperature of thermistor itself. To know case temperature (TC), conduct experiments considering the application.
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NFVA25012NP2T
RECOMMENDED OPERATING RANGES
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VPN
Supply Voltage
Applied between P − NU, NV, NW
300
600
800
V
VDD
Control Supply Voltage
Applied between VDD(UH,VH,WH) −
COM(H), VDD(L) − COM(L)
14.0
15.0
16.5
V
VBS
High−Side Bias Voltage
Applied between VB(U) − VS(U), VB(V) −
VS(V), VB(W) − VS(W)
13.0
15.0
18.5
V
dVDD / dt,
dVBS / dt
Control Supply Variation
−1
−
1
V/ms
tdead
Blanking Time for Preventing Arm − Short
For Each Input Signal
2.0
−
−
ms
fPWM
PWM Input Signal
−40°C ≤ TC ≤ 125°C, −40°C ≤ TJ ≤ 150°C
−
−
20
kHz
VSEN
Voltage for Current Sensing
Applied between NU, NV, NW − COM(H, L)
(Including Surge Voltage)
−5
−
5
V
PWIN(ON)
Minimum Input Pulse Width
VDD = VBS = 15 V, IC ≤ 75 A, Wiring
Inductance between NU,V,W and DC Link
N < 10 nH (Note 11)
2.5
−
−
ms
2.5
−
−
−40
−
150
PWIN(OFF)
TJ
Junction Temperature
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
11. This product might not make output response if input pulse width is less than the recommended value.
MECHANICAL CHARACTERISTICS AND RATINGS
Parameter
Conditions
Device Flatness
See Figure 7
Mounting Torque
Mounting Screw: M4
See Figure 8
Min
Typ
Max
Unit
0
−
+200
mm
Recommended 1.0 N ⋅ m
0.9
1.0
1.5
N⋅m
Recommended 10.1 kg ⋅ cm
9.1
10.1
15.1
kg ⋅ cm
Terminal Pulling Strength
Load 19.6 N
10
−
−
s
Terminal Bending Strength
Load 9.8 N, 90 degrees Bend
2
−
−
times
−
50
−
g
Weight
(+)
(+)
Figure 7. Flatness Measurement Position
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NFVA25012NP2T
2
Pre − Screwing: 1 → 2
Final Screwing: 2 → 1
1
NOTES:
12. Do not over torque when mounting screws. Too much mounting torque may cause DBC cracks, as well as bolts and Al heat−sink
destruction.
13. Avoid one−sided tightening stress. Figure 8 shows the recommended torque order for the mounting screws. Uneven mounting can cause
the DBC substrate of package to be damaged. The pre−screwing torque is set to 20~30% of maximum torque rating.
Figure 8. Mounting Screws Torque Order
TIME CHARTS OF SPMs PROTECTIVE FUNCTION
Input Signal
Protection
Circuit State
RESET
SET
RESET
UVDDR
Control
Supply Voltage
a1
UVDDD
a2
a6
a3
a7
a4
Output Current
a5
Fault Output Signal
a1: Control supply voltage rises: after the voltage rises UVDDR, the circuits start to operate when the next input is applied.
a2: Normal operation: IGBT ON and carrying current.
a3: Under-voltage detection (UVDDD).
a4: IGBT OFF in spite of control input condition.
a5: Fault output operation starts with a fixed pulse width according to the condition of the external capacitor CFOD.
a6: Under-voltage reset (UVDDR).
a7: Normal operation: IGBT ON and carrying current by triggering next signal from LOW to HIGH.
Figure 9. Under-Voltage Protection (Low-Side)
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NFVA25012NP2T
Input Signal
Protection
Circuit State
RESET
SET
RESET
UVBSR
Control
Supply Voltage
b1
b5
UVBSD
b3
b6
b2
b4
Output Current
Fault Output Signal
High−level (no fault output)
b1: Control supply voltage rises: after the voltage reaches UVBSR, the circuits start to operate when the next input is applied.
b2: Normal operation: IGBT ON and carrying current.
b3: Under-voltage detection (UVBSD).
b4: IGBT OFF in spite of control input condition, but there is no fault output signal.
b5: Under-voltage reset (UVBSR).
b6: Normal operation: IGBT ON and carrying current by triggering next signal from LOW to HIGH.
Figure 10. Under-Voltage Protection (High-Side)
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NFVA25012NP2T
Lower Arms
Control Input
c6
Protection
Circuit state
SET
c7
RESET
c4
Internal IGBT
Gate−Emitter
Input Voltage
c3
c2
Internal delay
at protection circuit
SC current trip level
Output Current
c8
c1
SC reference voltage
Sensing Voltage
of Sense Resistor
RC filter circuit
time constant
delay
Fault Output Signal
c5
(With the external sense resistance and RC filter connection)
c1: Normal operation: IGBT ON and carrying current.
c2: Short-circuit current detection (SC trigger).
c3: All low-side IGBTs gate are hard interrupted.
c4: All low-side IGBTs turn OFF.
c5: Fault output operation starts with a fixed pulse width according to the condition of the external capacitor CFOD.
c6: Input HIGH: IGBT ON state, but during the active period of fault output, the IGBT doesn’t turn ON.
c7: Fault output operation finishes, but IGBT doesn’t turn on until triggering the next signal from LOW to HIGH.
c8: Normal operation: IGBT ON and carrying current.
Figure 11. Short-Circuit Current Protection (Low-Side Operation Only)
INPUT/OUTPUT INTERFACE CIRCUIT
+5 V (MCU or control power)
ASPM
4.7 kW
IN(UH), IN(VH), IN(WH)
IN(UL), IN(VL), IN(WL)
VFO
MCU
COM
NOTE:
14. RC coupling at each input might change depending on the PWM control scheme used in the application and the wiring impedance of the
application’s printed circuit board. The input signal section of the Motion SPM 2 product integrates 5 kW (typ.) pull−down resistor. Therefore,
when using an external filtering resistor, please pay attention to the signal voltage drop at input terminal.
Figure 12. Recommended MCU I/O Interface Circuit
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12
NFVA25012NP2T
P (1)
R1
(30) IN
Gating WH
R2
C4
C4
C3
R1
Gating VH
R2
C3
C4
C4
R1
(31) V
DD(WH)
(32) V
BD(W)
(33) V
B(W)
(34) V
S(W)
(25) IN
(VH)
(26) V
DD(VH)
(27) V
BD(V)
(28) V
B(V)
(29) V
S(V)
(20) COM
C4
C1
C1
R2
C1
C3
C4
(22) V
BD(U)
(23) V
B(U)
(24) V
S(U)
IN
V DD
COM
HVIC
OUT
VB
VS
W (2)
IN
V DD
COM
HVIC
OUT
VB
(19) IN (UH)
(21) V DD(UH)
Gating UH
M
C
U
(WH)
(H)
VS
IN
V DD
COM
V (3)
M
C7
HVIC
V DC
OUT
VB
VS
U (4)
5V line
R3
R1
C5
Fault
C1
C1
Gating WL
Gating VL
Gating UL
(16) C
FOD
(15) V
FO
R1
(14) IN
(WL)
R1
(13) IN
(VL)
R1
(12) IN
(UL)
(10) V
DD(L)
15V line
C1
C1
C1
C2
5V line
C4
(11) COM
OUT
C FOD
V FO
N W (5)
R4
N V (6)
R4
IN
LVIC
IN
OUT
IN
V DD
(L)
COM
Power
GND Line
OUT
(9) V TH
R7
E
Shunt
Resistor
N U (7)
C SC
(8) R TH
Temp.
Monitoring
A
R SC (18)
Thermistor
(17) C
R5
Sense
Resistor
SC
D
C6
R4
R6
B
C
W−Phase Current
V−Phase Current
U−Phase Current
Control
GND Line
NOTES:
15. To avoid malfunction, the wiring of each input should be as short as possible (less than 2 − 3 cm).
16. VFO output is an open−drain type. This signal line should be pulled up to the positive side of the MCU or control power supply with a resistor
that makes IFO up to 2 mA. Please refer to Figure 13.
17. Fault out pulse width can be adjust by capacitor C5 connected to the CFOD terminal.
18. Input signal is active−HIGH type. There is a 5 kW resistor inside the IC to pull−down each input signal line to GND. RC coupling circuits
should be adopted for the prevention of input signal oscillation. R1C1 time constant should be selected in the range 50~ 50 ns
(recommended R1 = 100 W, C1 = 1 nF).
19. Each wiring pattern inductance of point A should be minimized (recommend less than 10 nH). Use the shunt resistor R4 of surface mounted
(SMD) type to reduce wiring inductance. To prevent malfunction, wiring of point E should be connected to the terminal of the shunt resistor
R4 as close as possible.
20. To insert the shunt resistor to measure each phase current at NU, NV, NW terminal, it makes to change the trip level ISC about the
short−circuit current.
21. To prevent errors of the protection function, the wiring of points B, C, and D should be as short as possible. The wiring of B between CSC
filter and RSC terminal should be divided at the point that is close to the terminal of sense resistor R5.
22. For stable protection function, use the sense resistor R5 with resistance variation within 1% and low inductance value.
23. In the short−circuit protection circuit, select the R6C6 time constant in the range 1.0~1.5 ms. R6 should be selected with a minimum of
10 times larger resistance than sense resistor R5. Do enough evaluaiton on the real system because short−circuit protection time may
vary wiring pattern layout and value of the R6C6 time constant.
24. Each capacitor should be mounted as close to the pins of the ASPM34 product as possible.
25. To prevent surge destruction, the wiring between the smoothing capacitor C7 and the P & GND pins should be as short as possible. The
use of a high−frequency non−inductive capacitor of around 0.1~0.22 mF between the P & GND pins is recommended.
26. Relays are used in most systems of electrical equipments in industrial application. In these cases, there should be sufficient distance
between the MCU and the relays.
27. The Zener diode or transient voltage suppressor should be adapted for the protection of ICs from the surge destruction between each pair
of control supply terminals (recommended Zener diode is 22 V / 1 W, which has the lower Zener impedance characteristic than about 15 W).
28. C2 of around seven times larger than bootstrap capacitor C3 is recommended.
29. Please choose the electrolytic capacitor with good temperature characteristic in C3. Choose 0.1~0.2 mF R−category ceramic capacitors
with good temperature and frequency characteristics in C4.
Figure 13. Typical Application Circuit
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13
NFVA25012NP2T
PACKAGE MARKING AND ORDERING INFORMATION
Device
Device Marking
Package
Shipping
NFVA25012NP2T
NFVA25012NP2T
ASPM34−CAA
(Pb−Free)
6 Units/Tube
SPM is registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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14
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DIP34 80x33, AUTOMOTIVE MODULE
CASE MODGL
ISSUE O
GENERIC
MARKING DIAGRAM*
XXXXXXXXXXX
ZZZ ATYWW
NNNNNNN
DOCUMENT NUMBER:
DESCRIPTION:
XXXX
ZZZ
AT
Y
W
NNN
98AON97156G
= Specific Device Code
= Lot ID
= Assembly & Test Location
= Year
= Work Week
= Serial Number
DATE 19 OCT 2018
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DIP34 80x33, AUTOMOTIVE MODULE
PAGE 1 OF 1
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