NID5004NT4G

NID5004N Self−Protected FET with Temperature and Current Limit 40 V, 6.5 A, Single N−Channel, DPAK http://onsemi.com Self–protected FETs are a series of power MOSFETs which utilize ON Semiconductor HDPlust technology. The self–protected MOSFET incorporates protection features such as integrated thermal and current limits. The self−protected MOSFETs include an integrated Drain−to−Gate Clamp that provides overvoltage protection from transients and avalanche. The device is protected from Electrostatic Discharge (ESD) by utilizing an integrated Gate−to−Source Clamp. Features • • • • • • • • • VDSS (Clamped) RDS(on) Typ ID Typ (Limited) 40 V 110 mW @ 10 V 6.5 A Drain Gate Input Short Circuit Protection In Rush Current Limit Thermal Shutdown with Automatic Restart Avalanche Rated Overvoltage Protection ESD Protection (4 kV HBM) Controlled Slew Rate for Low Noise Switching AEC Q101 Qualified This is a Pb−Free Device RG Overvoltage Protection ESD Protection Temperature Limit Current Limit Current Sense Source MARKING DIAGRAM Applications • • • • • • Solenoid Driver Relay Driver Small Motors Lighting Relay Replacement Load Switching 1 DPAK CASE 369C STYLE 2 2 3 D5004N = Device Code Y = Year WW = Work Week G = Pb−Free Device YYW D5 004NG 1 = Gate 2 = Drain 3 = Source ORDERING INFORMATION Device NID5004NT4G Package Shipping † DPAK (Pb−Free) 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2006 April, 2006 − Rev. 1 1 Publication Order Number: NID5004N/D NID5004N MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−to−Source Voltage Internally Clamped VDSS 44 Vdc Gate−to−Source Voltage VGS "14 Vdc Drain Current Continuous ID Total Power Dissipation @ TA = 25°C (Note 1) @ TA = 25°C (Note 2) PD Thermal Resistance Junction−to−Case Junction−to−Ambient (Note 1) Junction−to−Ambient (Note 2) Single Pulse Drain−to−Source Avalanche Energy (VDD = 30 Vdc, VGS = 5.0 Vdc, IL = 1.8 Apk, L = 160 mH, RG = 25 W) (Note 3) Operating and Storage Temperature Range (Note 4) Internally Limited 1.3 2.5 W °C/W RqJC RqJA RqJA 3.0 95 50 EAS 273 mJ TJ, Tstg −55 to 150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface mounted onto minimum pad size (100 sq/mm) FR4 PCB, 1 oz cu. 2. Mounted onto 1″ square pad size (700 sq/mm) FR4 PCB, 1 oz cu. 3. Not subject to Production Test 4. Normal pre−fault operating range. See thermal limit range conditions. http://onsemi.com 2 NID5004N MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 36 40 44 V − 27 100 − 45 200 1.0 − 1.85 5.0 2.2 − − 110 130 − − 130 240 150 270 − 0.9 1.1 OFF CHARACTERISTICS Drain−to−Source Clamped Breakdown Voltage (VGS = 0 V, ID = 2 mA) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 32 V, VGS = 0 V) IDSS Gate Input Current (VGS = 5.0 V, VDS = 0 V) IGSS mA mA ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 150 mA) Threshold Temperature Coefficient VGS(th) Static Drain−to−Source On−Resistance (Note 5) (VGS = 10 V, ID = 2.0 A, TJ @ 25°C) RDS(on) Static Drain−to−Source On−Resistance (Note 5) (VGS = 5.0 V, ID = 2.0 A, TJ @ 25°C) (VGS = 5.0 V, ID = 2.0 A, TJ @ 150°C) RDS(on) Source−Drain Forward On Voltage (IS = 7.0 A, VGS = 0 V) VSD V −mV/°C mW mW V SWITCHING CHARACTERISTICS (Note 6) Turn−on Delay Time RL = 6.6 W, Vin = 0 to 10 V, VDD = 13.8 V, ID = 2.0 A, 10% Vin to 10% ID td(on) − 97 115 ns Turn−on Rise Time RL = 6.6 W, Vin = 0 to 10 V, VDD = 13.8 V, ID = 2.0 A, 10% ID to 90% ID trise − 282 300 ns Turn−off Delay Time RL = 6.6 W, Vin = 0 to 10 V, VDD = 13.8 V, ID = 2.0 A, 90% Vin to 90% ID td(off) − 930 1020 ns Turn−off Fall Time RL = 6.6 W, Vin = 0 to 10 V, VDD = 13.8 V, ID = 2.0 A, 90% ID to 10% ID tfall − 690 750 ns Slew Rate ON RL = 6.6 W, Vin = 0 to 10 V, VDD = 13.8 V, ID = 2.0 A, 70% to 50% VDD dVDS/dTon − 64 − V/ms Slew Rate OFF RL = 6.6 W, Vin = 0 to 10 V, VDD = 13.8 V, ID = 2.0 A, 50% to 70% VDD dVDS/dToff − 28 − V/ms SELF PROTECTION CHARACTERISTICS (TJ = 25°C unless otherwise noted) (Note 7) Current Limit VDS = 10 V, VGS = 5.0 V, TJ = 25°C (Note 8) VDS = 10 V, VGS = 5.0 V, TJ = 100°C (Note 6, 8) VDS = 10 V, VGS = 10 V, TJ = 25°C (Note 6, 8) ILIM 4.0 4.0 − 6.5 5.5 7.9 11 11 − A VGS = 5.0 V (Note 6) TLIM(off) 150 180 200 °C Temperature Limit (Turn−off) Thermal Hysteresis VGS = 5.0 V DTLIM(on) − 10 − °C VGS = 10 V (Note 6) TLIM(off) 150 180 200 °C Thermal Hysteresis VGS = 10 V DTLIM(on) − 20 − °C Input Current during Thermal Fault VDS = 0 V, VGS = 5.0 V, TJ = TJ > T(fault) (Note 6) VDS = 0 V, VGS = 10 V, TJ = TJ > T(fault) (Note 6) Ig(fault) 5.5 12 5.2 11 − mA 4000 400 − − − − Temperature Limit (Turn−off) ESD ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Electrostatic Discharge Capability Human Body Model (HBM) Machine Model (MM) (Note 6) 5. 6. 7. 8. ESD Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. Not subject to Production Test Fault conditions are viewed as beyond the normal operating range of the part. Current limit measured at 380 ms after gate pulse. http://onsemi.com 3 V NID5004N TYPICAL PERFORMANCE CURVES 6 TJ = 25°C 5.0 V 10 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 12 10 V 8 6 4.0 V 4 3.5 V 2 VGS = 3.0 V 0 5.0 10 5 TJ = 25°C 3 2 1 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 1 2 3 4 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0.15 ID = 2 A TJ = 25°C 0.14 0.13 0.12 0.11 0.10 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 0 TJ = 25°C 0.14 0.13 VGS = 5 V 0.12 0.11 VGS = 10 V 0.10 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 ID, DRAIN CURRENT (AMPS) Figure 4. On−Resistance vs. Drain Current VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 1E−03 1.6 1.4 5 0.15 Figure 3. On−Resistance vs. Gate−to−Source Voltage RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) TJ = 100°C 4 0 20 15 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 TJ = −55°C ID = 3.75 A VGS = 10 V TJ = 100°C 8E−04 1.2 6E−04 1.0 4E−04 0.8 2E−04 0.6 0.4 −55 −35 −15 5 25 45 65 85 0E+00 0 5.0 10 15 20 25 30 35 40 45 TJ, JUNCTION TEMPERATURE (°C) IDSS, LEAKAGE (A) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 4 NID5004N zl TYPICAL PERFORMANCE CURVES 12000 VGS = 0 V TJ = 25°C 7 VDS = 0 V TA = 200°C 10000 6 8000 5 IGSS (mA) IS, SOURCE CURRENT (AMPS) 8 4 3 6000 4000 2 2000 1 0 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 1.0 6 7 8 Figure 8. Input Current vs. Gate Voltage Figure 7. Diode Forward Voltage vs. Current DRAIN CURRENT (AMPS) 12 VGS = 10 V 10 8 VGS = 5 V 6 Current Limit 4 Temperature Limit 2 0 0E+0 1E−3 2E−3 9 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 3E−3 4E−3 5E−3 6E−3 7E−3 TIME (seconds) Figure 9. Short Circuit Response* *(Actual thermal cycling response in short circuit dependent on device power level, thermal mounting, and ambient temperature conditions) HDPlus is a trademark of Semiconductor Components Industries, LLC (SCILLC) http://onsemi.com 5 10 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C ISSUE F 4 1 2 DATE 21 JUL 2015 3 SCALE 1:1 A E b3 C A B c2 4 L3 Z D 1 L4 2 3 NOTE 7 b2 e c SIDE VIEW b 0.005 (0.13) TOP VIEW H DETAIL A M BOTTOM VIEW C Z H L2 GAUGE PLANE C L L1 DETAIL A Z SEATING PLANE BOTTOM VIEW A1 ALTERNATE CONSTRUCTIONS ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 8: PIN 1. N/C 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 9: STYLE 10: PIN 1. ANODE PIN 1. CATHODE 2. CATHODE 2. ANODE 3. RESISTOR ADJUST 3. CATHODE 4. CATHODE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.028 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.114 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.72 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.90 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− GENERIC MARKING DIAGRAM* XXXXXXG ALYWW AYWW XXX XXXXXG IC Discrete = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 6.17 0.243 SCALE 3:1 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z XXXXXX A L Y WW G 3.00 0.118 1.60 0.063 STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. 7. OPTIONAL MOLD FEATURE. mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON10527D DPAK (SINGLE GAUGE) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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