NL17SH17
Single Schmitt-Trigger
Buffer
The NL17SH17 is a single gate CMOS Schmitt−trigger
non−inverting buffer fabricated with silicon gate CMOS technology.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
NL17SH17 input structure provides protection when voltages up to 7
V are applied, regardless of the supply voltage. This allows the
NL17SH17 to be used to interface 5 V circuits to 3 V circuits.
The NL17SH17 can be used to enhance noise immunity or to square
up slowly changing waveforms.
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MARKING
DIAGRAM
Features
•
•
•
•
•
•
•
High Speed: tPD = 4.0 ns (Typ) at VCC = 5.0 V
Y
Low Power Dissipation: ICC = 1.0 mA (Max) at TA = 25°C
M
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Y
SOT−953
CASE 527AE
1
= Specific Device Code
(Rotated 90°)
= Month Code
PIN ASSIGNMENT
Chip Complexity: FETs = 101
1
IN A
These Devices are Pb−Free and are RoHS Compliant
2
GND
3
NC
4
OUT Y
5
VCC
IN A
1
GND
2
NC
3
5
VCC
M
FUNCTION TABLE
4
OUT Y
Figure 1. Pinout
Input A
Output Y
L
H
L
H
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
1
IN A
OUT Y
Figure 2. Logic Symbol
© Semiconductor Components Industries, LLC, 2012
September, 2012 − Rev. 0
1
Publication Order Number:
NL17SH17/D
NL17SH17
MAXIMUM RATINGS
Symbol
Parameter
VCC
DC Supply Voltage
VIN
DC Input Voltage
VOUT
DC Input Diode Current
IOK
DC Output Diode Current
IOUT
DC Output Source/Sink Current
ICC
DC Supply Current per Supply Pin
IGND
DC Ground Current per Ground Pin
TSTG
Storage Temperature Range
Unit
−0.5 to +7.0
V
−0.5 to +7.0
V
−0.5 to VCC + 0.5
V
VIN < GND
−20
mA
VOUT < GND, VOUT > VCC
±20
mA
±12.5
mA
±25
mA
DC Output Voltage
IIK
Value
±25
mA
−65 to +150
°C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
260
°C
TJ
Junction Temperature Under Bias
+150
°C
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
Level 1
Oxygen Index: 28 to 34
ESD Withstand Voltage
ILATCHUP
UL 94 V−0 @ 0.125 in
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
Latchup Performance
Above VCC and Below GND at 125°C (Note 5)
>3000
>200
N/A
V
±100
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
Max
Unit
VCC
Positive DC Supply Voltage
1.65
5.5
V
VIN
Digital Input Voltage
0.0
5.5
V
Output Voltage
0.0
VCC
V
Operating Temperature Range
VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V
80
1,032,200
117.8
90
419,300
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
+125
°C
0
0
No Limit
No Limit
ns/V
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TJ = 80°C
Time, Years
−55
TJ = 90°C
Time, Hours
TJ = 110°C
Junction
Temperature °C
NORMALIZED FAILURE RATE
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
TJ = 120°C
Input Transition Rise or Fail Rate
TJ = 130°C
TA
Dt / DV
TJ = 100°C
VOUT
1
1
10
100
1000
TIME, YEARS
Figure 3. Failure Rate vs. Time Junction Temperature
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2
NL17SH17
DC ELECTRICAL CHARACTERISTICS
TA = 255C
VCC
Symbol
Parameter
Min
(V)
Test Conditions
Typ
Max
2.0
3.0
3.6
2.2
3.15
3.85
VT+
Positive Threshold
Voltage
3.0
4.5
5.5
VT−
Negative Threshold
Voltage
3.0
4.5
5.5
0.9
1.35
1.65
1.5
2.3
2.9
VH
Hysteresis Voltage
3.0
4.5
5.5
0.3
0.4
0.5
0.57
0.67
0.74
VIN ≥ VTmin
IOH = −50 mA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
VIN ≥ VTmin
IOH = −4 mA
IOH = −8 mA
3.0
4.5
2.58
3.94
VIN ≤ VTmax
IOL = 50 mA
2.0
3.0
4.5
VIN ≤ VTmax
IOL = 4 mA
IOL = 8 mA
VOH
VOL
High−Level
Output Voltage
Low−Level
Output Voltage
TA v 855C
Min
Max
0.0
0.0
0.0
Min
2.2
3.15
3.85
0.9
1.35
1.65
1.2
1.4
1.6
*555C to 1255C
0.3
0.4
0.5
Max
Unit
2.2
3.15
3.85
V
0.9
1.35
1.65
1.2
1.4
1.6
0.3
0.4
0.5
1.9
2.9
4.4
1.9
2.9
4.4
2.48
3.80
2.34
3.66
V
1.2
1.4
1.6
V
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
V
IIN
Input Leakage Current
VIN = 5.5 V or GND
0 to
5.5
$0.1
$1.0
$1.0
mA
ICC
Quiescent Supply
Current
VIN = VCC or GND
5.5
1.0
20
40
mA
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
Symbol
tPLH,
tPHL
CIN
Parameter
Propagation Delay,
A to Y
VCC
(V)
TA = 255C
Test
Conditions
Min
TA v 855C
*555C to 1255C
Typ
Max
Min
Max
Min
Max
Unit
ns
3.0 to 3.6
CL = 15 pF
CL = 50 pF
7.0
8.5
12.8
16.3
1.0
1.0
15.0
18.5
1.0
1.0
17.0
20.5
4.5 to 5.5
CL = 15 pF
CL = 50 pF
4.0
5.5
8.6
10.6
1.0
1.0
10.0
12.0
1.0
1.0
11.5
13.5
5.0
10
Input Capacitance
10
10
pF
Typical @ 25°C, VCC = 5.0 V
CPD
7.0
Power Dissipation Capacitance (Note 6)
pF
6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
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3
NL17SH17
A or B
TEST POINT
VCC
50%
OUTPUT
GND
tPHL
Y
DEVICE
UNDER
TEST
tPLH
CL*
50% VCC
*Includes all probe and jig capacitance.
Figure 4. Switching Waveform
Figure 5. Test Circuit
ORDERING INFORMATION
Device
NL17SH17P5T5G
Package
Shipping†
SOT−953
(Pb−Free)
8000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−953
CASE 527AE
ISSUE E
DATE 02 AUG 2011
SCALE 4:1
X
Y
D
5
PIN ONE
INDICATOR
A
4
HE
E
1
2 3
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF THE BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
DIM
A
b
C
D
E
e
HE
L
L2
L3
C
TOP VIEW
SIDE VIEW
e
L
5X
5X
L3
5X
L2
MILLIMETERS
MIN
NOM
MAX
0.34
0.37
0.40
0.10
0.15
0.20
0.07
0.12
0.17
0.95
1.00
1.05
0.75
0.80
0.85
0.35 BSC
0.95
1.00
1.05
0.175 REF
0.05
0.10
0.15
−−−
−−−
0.15
GENERIC
MARKING DIAGRAM*
5X
BOTTOM VIEW
XM
b
1
0.08 X Y
X
M
SOLDERING FOOTPRINT*
*This information is generic. Please refer
to device data sheet for actual part
marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
5X
0.35
5X
0.20
= Specific Device Code
= Month Code
PACKAGE
OUTLINE
1.20
1
0.35
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON26457D
SOT−953
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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