NLSX5014DR2G

NLSX5014 4-Bit 100 Mb/s Configurable Dual-Supply Level Translator The NLSX5014 is a 4-bit configurable dual-supply autosensing bidirectional level translator that does not require a direction control pin. The I/O VCC- and I/O VL-ports are designed to track two different power supply rails, VCC and VL respectively. Both the VCC and the VL supply rails are configurable from 0.9 V to 4.5 V. This allows a logic signal on the VL side to be translated to either a higher or a lower logic signal voltage on the VCC side, and vice-versa. The NLSX5014 offers the feature that the values of the VCC and VL supplies are independent. Design flexibility is maximized because VL can be set to a value either greater than or less than the VCC supply. In contrast, the majority of competitive auto sense translators have a restriction that the value of the VL supply must be equal to less than (VCC - 0.4) V. The NLSX5014 has high output current capability, which allows the translator to drive high capacitive loads such as most high frequency EMI filters. Another feature of the NLSX5014 is that each I/O_VLn and I/O_VCCn channel can function as either an input or an output. An Output Enable (EN) input is available to reduce the power consumption. The EN pin can be used to disable both I/O ports by putting them in 3-state which significantly reduces the supply current from both VCC and VL. The EN signal is referenced to the VL supply. Features http://onsemi.com MARKING DIAGRAMS UQFN12 MU SUFFIX CASE 523AE M G = Date Code = Pb−Free Package AAMG G 1 (Note: Microdot may be in either location) 14 14 1 SOIC−14 D SUFFIX CASE 751A 1 14 14 1 TSSOP−14 DT SUFFIX CASE 948G 1 NLSX 5014 ALYWG G NLSX5014G AWLYWW • Wide VCC, VL Operating Range: 0.9 V to 4.5 V • VL and VCC are independent • High 100 pF Capacitive Drive Capability • High−Speed with 140 Mb/s Guaranteed Date Rate • • • • • • − VL may be greater than, equal to, or less than VCC A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) for VCC, VL > 1.8 V Low Bit−to−Bit Skew Overvoltage Tolerant Enable and I/O Pins Non−preferential Powerup Sequencing Power−Off Protection Small packaging: 1.7 mm x 2.0 mm UQFN12, SOIC14, TSSOP14 These are Pb−Free Devices ORDERING INFORMATION Device NLSX5014MUTAG NLSX5014DR2G NLSX5014DTR2G Package Shipping† UQFN12 3000/T ape & Reel (Pb−Free) SO−14 2500/T ape & Reel (Pb−Free) TSSOP14 2500/T ape & Reel (Pb−Free) Typical Applications • Mobile Phones, PDAs, Other Portable Devices Important Information ♦ • ESD Protection for All Pins: HBM (Human Body Model) > 7000 V †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2010 June, 2010 − Rev. 1 1 Publication Order Number: NLSX5014/D NLSX5014 VL +1.8V +3.6V P One−Shot R1 1k VL +1.8 V System NLSX5014 VCC +3.6 V System I/O VL N One−Shot I/O VCC VCC I/O1 I/On GND OE I/O VL1 I/O VCC1 I/O1 I/On GND P One−Shot R2 1k N One−Shot I/O VLn I/O VCCn EN GND Figure 1. Typical Application Circuit Figure 2. Simplified Functional Diagram (1 I/O Line) 2.5 V 3.0 V 2.5 V 1.8 V mC CE SCK SDO SDI ANO VL NLSX5014 VCC Temperature Sensor CE SCK SDI SDO mC CE SCK SDO SDI ANO VL NLSX5014 VCC Temperature Sensor CE SCK SDI SDO I/O VL1 I/O VL2 I/O VL3 I/O VL4 EN I/O VCC1 I/O VCC2 I/O VCC3 I/O VCC4 GND I/O VL1 I/O VL2 I/O VL3 I/O VL4 EN I/O VCC1 I/O VCC2 I/O VCC3 I/O VCC4 GND Figure 3. Application Example for VL < VCC Figure 4. Application Example for VL > VCC http://onsemi.com 2 NLSX5014 VL EN VL I/O VL1 I/O VL2 I/O VL3 I/O VL4 1 2 3 4 5 6 12 11 10 9 8 7 1 2 3 4 5 6 7 TSSOP/SOIC (Top View) 14 13 12 11 10 9 8 VCC I/O VCC1 I/O VCC2 I/O VCC3 I/O VCC4 NC EN I/O VL1 VCC I/O VCC1 I/O VCC2 I/O VCC3 I/O VCC4 I/O VL2 I/O VL3 I/O VL4 NC GND GND UQFN12 (Top View) Figure 1. Pin Assignments EN VL VCC GND I/O VL1 I/O VCC1 I/O VL2 I/O VCC2 I/O VL3 I/O VCC3 I/O VL4 I/O VCC4 Figure 2. Logic Diagram PIN ASSIGNMENT Pins VCC VL GND EN I/O VCCn I/O VLn Description VCC Input Voltage VL Input Voltage Ground Output Enable I/O Port, Referenced to VCC I/O Port, Referenced to VL FUNCTION TABLE EN L H Operating Mode Hi−Z I/O Buses Connected http://onsemi.com 3 NLSX5014 MAXIMUM RATINGS Symbol VCC VL I/O VCC I/O VL VI IIK IOK ICC IL IGND TSTG Parameter High−side DC Supply Voltage Low−side DC Supply Voltage VCC−Referenced DC Input/Output Voltage VL−Referenced DC Input/Output Voltage Enable Control Pin DC Input Voltage DC Input Diode Current DC Output Diode Current DC Supply Current Through VCC DC Supply Current Through VL DC Ground Current Through Ground Pin Storage Temperature Value −0.5 to +5.5 −0.5 to +5.5 −0.5 to +5.5 −0.5 to +5.5 −0.5 to +5.5 −50 −50 $100 $100 $100 −65 to +150 VI < GND VO < GND Condition Unit V V V V V mA mA mA mA mA °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. RECOMMENDED OPERATING CONDITIONS Symbol VCC VL VI VIO TA Dt/DV Parameter High−side Positive DC Supply Voltage Low−side Positive DC Supply Voltage Enable Control Pin Voltage Bus Input/Output Voltage Operating Temperature Range Input Transition Rise or Rate VI, VIO from 30% to 70% of VCC; VCC = 3.3 V $ 0.3 V I/O VCC I/O VL Min 0.9 0.9 GND GND GND −55 0 Max 4.5 4.5 4.5 4.5 4.5 +125 10 Unit V V V V °C ns http://onsemi.com 4 NLSX5014 DC ELECTRICAL CHARACTERISTICS −405C to +855C Symbol VIHC VILC VIHL VILL VIH VIL VOHC VOLC VOHL VOLL IQVCC Parameter I/O VCC Input HIGH Voltage I/O VCC Input LOW Voltage I/O VL Input HIGH Voltage I/O VL Input LOW Voltage Control Pin Input HIGH Voltage Control Pin Input LOW Voltage I/O VCC Output HIGH Voltage I/O VCC Output LOW Voltage I/O VL Output HIGH Voltage I/O VL Output LOW Voltage VCC Supply Current TA = +25°C TA = +25°C I/O VCC source current = 20 mA I/O VCC sink current = 20 mA I/O VL source current = 20 mA I/O VL sink current = 20 mA EN = VL, IO = 0 A, (I/O VCC = 0 V or VCC, I/O VL = float) or (I/O VCC = float, I/O VL = 0 V or VL) TA = +25°C, EN = 0 V (I/O VCC = 0 V or VCC, I/O VL = float) or (I/O VCC = float, I/O VL = 0 V or VL) TA = +25°C, EN = 0V TA = +25°C I/O VCC = 0 to 4.5V, I/O VL = 0 to 4.5 V 1. 2. 3. 4. Test Conditions (Note 1) VCC (V) (Note 2) 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 VL (V) (Note 3) 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 Min 2/3 * VCC − 2/3 * VL − 2/3 * VL − 0.9 * VCC − 0.9 * VL − − Typ (Note 4) − − − − − − − − − − − Max − 1/3 * VCC − 1/3 * VL − 1/3 * VL − 0.2 − 0.2 1 −555C to +1255C Min 2/3 * VCC − 2/3 * VL − 2/3 * VL − 0.9 * VCC − 0.9 * VL − − Max − 1/3 * VCC − 1/3 * VL − 1/3 * VL − 0.2 − 0.2 2.5 Unit V V V V V V V V V V mA IQVL ITS−VCC VL Supply Current VCC Tristate Output Mode Supply Current VL Tristate Output Mode Supply Current I/O Tristate Output Mode Leakage Current Control Pin Input Current Power Off Leakage Current 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 − − − − 1 0.5 − − 2.5 1.5 mA mA ITS−VL 0.9 – 4.5 0.9 – 4.5 − − 0.5 − 1.5 mA IOZ II IOFF 0.9 – 4.5 0.9 – 4.5 0 0.9 – 4.5 0 0.9 – 4.5 0.9 – 4.5 0 0 0.9 – 4.5 − − − − − − − − − − ±1 ±1 1 1 1 − − − − − ±1.5 ±1 1.5 1.5 1.5 mA mA mA Normal test conditions are VI = 0 V, CIOVCC ≤ 15 pF and CIOVL ≤ 15 pF, unless otherwise specified. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design. http://onsemi.com 5 NLSX5014 TIMING CHARACTERISTICS −555C to +1255C Symbol tR−VCC tF−VCC tR−VL tF−VL ZOVCC Parameter I/O VCC Rise Time I/O VCC Fall Time I/O VL Rise Time I/O VL Fall Time I/O VCC One−Shot Output Impedance I/O VL One−Shot Output Impedance Test Conditions (Note 5) CIOVCC = 15 pF CIOVCC = 15 pF CIOVL = 15 pF CIOVL = 15 pF (Note 9) VCC (V) (Note 6) 0.9 – 4.5 1.8 – 4.5 0.9 – 4.5 1.8 – 4.5 0.9 – 4.5 1.8 – 4.5 0.9 – 4.5 1.8 – 4.5 0.9 1.8 4.5 0.9 1.8 4.5 0.9 – 4.5 1.8 – 4.5 CIOVCC = 30 pF CIOVCC = 50 pF CIOVCC = 100 pF tPD_VCC−VL Propagation Delay (Driving I/O VL) CIOVL = 15 pF CIOVL = 30 pF CIOVL = 50 pF CIOVL = 100 pF tSK IIN_PEAK Channel−to−Channel Skew Input Driver Maximum Peak Current CIOVCC = 15 pF, CIOVL = 15 pF (Note 9) EN = VL; I/O_VCC = 1 MHz Square Wave, Amplitude = VCC, or I/O_VL = 1 MHz Square Wave, Amplitude = VL (Note 9) 0.9 – 4.5 1.8 – 4.5 1.0 – 4.5 1.8 – 4.5 1.2 – 4.5 1.8 – 4.5 0.9 – 4.5 1.8 – 4.5 0.9 – 4.5 1.8 – 4.5 1.0 – 4.5 1.8 – 4.5 1.2 – 4.5 1.8 – 4.5 0.9 – 4.5 0.9 – 4.5 VL (V) (Note 7) 0.9 – 4.5 1.8 – 4.5 0.9 – 4.5 1.8 – 4.5 0.9 – 4.5 1.8 – 4.5 0.9 – 4.5 1.8 – 4.5 0.9 – 4.5 Min − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − Typ (Note 8) − − − − − − − − 37 20 6.0 37 20 6.0 − − − − − − − − − − − − − − − − − − Max 8.5 3.5 8.5 3.5 8.5 3.5 8.5 3.5 − − − − − − 35 10 35 10 37 11 40 13 35 10 35 10 37 11 40 13 0.15 5.0 nS mA nS W nS nS nS Unit nS ZOVL (Note 9) 0.9 – 4.5 W tPD_VL−VCC Propagation Delay (Driving I/O VCC) CIOVCC = 15 pF 0.9 – 4.5 1.8 – 4.5 0.9 – 4.5 1.8 – 4.5 1.0 – 4.5 1.8 – 4.5 1.2 – 4.5 1.8 – 4.5 0.9 – 4.5 1.8 – 4.5 0.9 – 4.5 1.8 – 4.5 1.0 – 4.5 1.8 – 4.5 1.2 – 4.5 1.8 – 4.5 0.9 – 4.5 0.9 – 4.5 nS 5. 6. 7. 8. Normal test conditions are VI = 0 V, CIOVCC ≤ 15 pF and CIOVL ≤ 15 pF, unless otherwise specified. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design. 9. Guaranteed by design. http://onsemi.com 6 NLSX5014 TIMING CHARACTERISTICS (continued) −555C to +1255C Symbol tEN−VCC Parameter I/O_VCC Output Enable Time tPZH tPZL tEN−VL I/O_VL Output Enable Time tPZH tPZL tDIS−VCC I/O_VCC Output Disable Time tPHZ tPLZ tDIS−VL I/O_VL Output Disable Time tPHZ tPLZ MDR Maximum Data Rate Test Conditions (Note 10) CIOVCC = 15 pF, I/O_VL = VL CIOVCC = 15 pF, I/O_VL = 0 V CIOVL = 15 pF, I/O_VCC = VCC CIOVL = 15 pF, I/O_VCC = 0 V CIOVCC = 15 pF, I/O_VL = VL CIOVCC = 15 pF, I/O_VL = 0 V CIOVL = 15 pF, I/O_VCC = VCC CIOVL = 15 pF, I/O_VCC = 0 V CIO = 15 pF CIO = 30 pF CIO = 50 pF CIO = 100 pF VCC (V) (Note 11) 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 1.8 – 4.5 0.9 – 4.5 1.8 – 4.5 1.0 – 4.5 1.8 – 4.5 1.2 – 4.5 1.8 – 4.5 VL (V) (Note 12) 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 0.9 – 4.5 1.8 – 4.5 0.9 – 4.5 1.8 – 4.5 1.0 – 4.5 1.8 – 4.5 1.2 – 4.5 1.8 – 4.5 Min − − − − − − − − 50 140 40 120 30 100 20 60 Typ (Note 13) − − − − − − − − − − − − − − − − Max 160 130 160 130 210 175 210 175 − − − − − − − − mbps nS nS nS Unit nS 10. Normal test conditions are VI = 0 V, CIOVCC ≤ 15 pF and CIOVL ≤ 15 pF, unless otherwise specified. 11. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions. 12. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions. 13. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design. http://onsemi.com 7 NLSX5014 DYNAMIC POWER CONSUMPTION (TA = +25°C) Symbol CPD_VL Parameter VL = Input port, VCC = Output Port Test Conditions CLoad = 0, f = 1 MHz, EN = VL (outputs enabled) VCC (V) (Note 14) 0.9 1.5 1.8 1.8 1.8 2.5 2.8 4.5 VCC = Input port, VL = Output Port CLoad = 0, f = 1 MHz, EN = VL (outputs enabled) 0.9 1.5 1.8 1.8 1.8 2.5 2.8 4.5 CPD_VCC VL = Input port, VCC = Output Port CLoad = 0, f = 1 MHz, EN = VL (outputs enabled) 0.9 1.5 1.8 1.8 1.8 2.5 2.8 4.5 VCC = Input port, VL = Output Port CLoad = 0, f = 1 MHz, EN = VL (outputs enabled) 0.9 1.5 1.8 1.8 1.8 2.5 2.8 4.5 VL (V) (Note 15) 4.5 1.8 1.5 1.8 2.8 2.5 1.8 0.9 4.5 1.8 1.5 1.8 2.8 2.5 1.8 0.9 4.5 1.8 1.5 1.8 2.8 2.5 1.8 0.9 4.5 1.8 1.5 1.8 2.8 2.5 1.8 0.9 Typ (Note 16) 39 20 17 14 13 14 13 19 37 30 29 29 29 30 29 19 29 29 29 29 29 30 29 35 21 18 18 14 13 14 13 30 pF pF pF Unit pF 14. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions. 15. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions. 16. Typical values are at TA = +25°C. 17. CPD VL and CPD VCC are defined as the value of the IC’s equivalent capacitance from which the operating current can be calculated for the VL and VCC power supplies, respectively. ICC = ICC (dynamic) + ICC (static) ≈ ICC(operating) ≈ CPD x VCC x fIN x NSW where ICC = ICC_VCC + ICC VL and NSW = total number of outputs switching. http://onsemi.com 8 NLSX5014 STATIC POWER CONSUMPTION (TA = +25°C) Symbol CPD_VL Parameter VL = Input port, VCC = Output Port Test Conditions CLoad = 0, f = 1 MHz, EN = GND (outputs disabled) VCC (V) (Note 18) 0.9 1.5 1.8 1.8 1.8 2.5 2.8 4.5 VCC = Input port, VL = Output Port CLoad = 0, f = 1 MHz, EN = GND (outputs disabled) 0.9 1.5 1.8 1.8 1.8 2.5 2.8 4.5 CPD_VCC VL = Input port, VCC = Output Port CLoad = 0, f = 1 MHz, EN = GND (outputs disabled) 0.9 1.5 1.8 1.8 1.8 2.5 2.8 4.5 VCC = Input port, VL = Output Port CLoad = 0, f = 1 MHz, EN = GND (outputs disabled) 0.9 1.5 1.8 1.8 1.8 2.5 2.8 4.5 VL (V) (Note 19) 4.5 1.8 1.5 1.8 2.8 2.5 1.8 0.9 4.5 1.8 1.5 1.8 2.8 2.5 1.8 0.9 4.5 1.8 1.5 1.8 2.8 2.5 1.8 0.9 4.5 1.8 1.5 1.8 2.8 2.5 1.8 0.9 Typ (Note 20) 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 pF pF pF Unit pF 18. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions. 19. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions. 20. Typical values are at TA = +25°C http://onsemi.com 9 NLSX5014 VL EN Source I/O VL I/O VCC CIOVCC I/O VL CIOVL Source I/O VL 90% 50% 10% tPD_VL−VCC I/O VCC 90% 50% 10% tF−VCC tR−VCC tRISE/FALL v 3 ns I/O VCC 90% 50% 10% tPD_VL−VCC tPD_VCC−VL I/O VL 90% 50% 10% tF−VL tR−VL tPD_VCC−VL tRISE/FALL v 3 ns NLSX5014 VCC VL EN I/O VCC NLSX5014 VCC Figure 3. Driving I/O VL Test Circuit and Timing Figure 4. Driving I/O VCC Test Circuit and Timing VCC R1 CL RL 2xVCC OPEN PULSE GENERATOR RT DUT Test tPZH, tPHZ tPZL, tPLZ Switch Open 2 x VCC CL = 15 pF or equivalent (Includes jig and probe capacitance) RL = R1 = 50 kW or equivalent RT = ZOUT of pulse generator (typically 50 W) Figure 5. Test Circuit for Enable/Disable Time Measurement tR Input tPLH Output 90% 50% 10% 90% 50% 10% tR tPHL tF 50% VL GND HIGH IMPEDANCE 10% 90% VOL VOH HIGH IMPEDANCE VCC GND EN tPZL Output 50% tPZH Output 50% tPLZ tF tPHZ Figure 6. Timing Definitions for Propagation Delays and Enable/Disable Measurement http://onsemi.com 10 NLSX5014 IMPORTANT APPLICATIONS INFORMATION Level Translator Architecture The NLSX5014 auto−sense translator provides bi−directional logic voltage level shifting to transfer data in multiple supply voltage systems. These level translators have two supply voltages, VL and VCC, which set the logic levels on the input and output sides of the translator. When used to transfer data from the I/O VL to the I/O VCC ports, input signals referenced to the VL supply are translated to output signals with a logic level matched to VCC. In a similar manner, the I/O VCC to I/O VL translation shifts input signals with a logic level compatible to VCC to an output signal matched to VL. The NLSX5014 translator consists of bi−directional channels that independently determine the direction of the data flow without requiring a directional pin. One−shot circuits are used to detect the rising or falling input signals. In addition, the one−shots decrease the rise and fall times of the output signal for high−to−low and low−to−high transitions. Input Driver Requirements VL pins to a high impedance state. Normal translation operation occurs when the EN pin is equal to a logic high signal. The EN pin is referenced to the VL supply and has Over−Voltage Tolerant (OVT) protection. Uni−Directional versus Bi−Directional Translation The NLSX5014 translator can function as a non−inverting uni−directional translator. One advantage of using the translator as a uni−directional device is that each I/O pin can be configured as either an input or output. The configurable input or output feature is especially useful in applications such as SPI that use multiple uni−directional I/O lines to send data to and from a device. The flexible I/O port of the auto sense translator simplifies the trace connections on the PCB. Power Supply Guidelines Auto−sense translators such as the NLSX5014 have a wide bandwidth, but a relatively small DC output current rating. The high bandwidth of the bi−directional I/O circuit is used to quickly transform from an input to an output driver and vice versa. The I/O ports have a modest DC current output specification so that the output driver can be over driven when data is sent in the opposite direction. For proper operation, the input driver to the auto−sense translator should be capable of driving 2 mA of peak output current. The bi−directional configuration of the translator results in both input stages being active for a very short time period. Although the peak current from the input signal circuit is relatively large, the average current is small and consistent with a standard CMOS input stage. Enable Input (EN) The NLSX5014 translator has an Enable pin (EN) that provides tri−state operation at the I/O pins. Driving the Enable pin to a low logic level minimizes the power consumption of the device and drives the I/O VCC and I/O The values of the VL and VCC supplies can be set to anywhere between 0.9 and 4.5 V. Design flexibility is maximized because VL may be either greater than or less than the VCC supply. In contrast, the majority of the competitive auto sense translators has a restriction that the value of the VL supply must be equal to less than (VCC − 0.4) V. The sequencing of the power supplies will not damage the device during power−up operation. In addition, the I/O VCC and I/O VL pins are in the high impedance state if either supply voltage is equal to 0 V. For optimal performance, 0.01 to 0.1 mF decoupling capacitors should be used on the VL and VCC power supply pins. Ceramic capacitors are a good design choice to filter and bypass any noise signals on the voltage lines to the ground plane of the PCB. The noise immunity will be maximized by placing the capacitors as close as possible to the supply and ground pins, along with minimizing the PCB connection traces. The NLSX5014 translators have a power down feature that provides design flexibility. The output ports are disabled when either power supply is off (VL or VCC = 0 V). This feature causes all of the I/O pins to be in the power saving high impedance state. http://onsemi.com 11 NLSX5014 PACKAGE DIMENSIONS UQFN12 1.7x2.0, 0.4P CASE 523AE−01 ISSUE A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. MOLD FLASH ALLOWED ON TERMINALS ALONG EDGE OF PACKAGE. FLASH 0.03 MAX ON BOTTOM SURFACE OF TERMINALS. 5. DETAIL A SHOWS OPTIONAL CONSTRUCTION FOR TERMINALS. DIM A A1 A3 b D E e K L L1 L2 MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.127 REF 0.15 0.25 1.70 BSC 2.00 BSC 0.40 BSC 0.20 ---0.45 0.55 0.00 0.03 0.15 REF D PIN 1 REFERENCE AB L1 DETAIL A NOTE 5 2X 2X 0.10 C 0.10 C 0.05 C 12X 0.05 C A3 8X K 5 7 DETAIL A 1 12X L L2 BOTTOM VIEW ÏÏ ÏÏ ÏÏ TOP VIEW A A1 SIDE VIEW e 11 E DETAIL B OPTIONAL CONSTRUCTION DETAIL B C SEATING PLANE MOUNTING FOOTPRINT SOLDERMASK DEFINED 2.00 12X b 0.10 0.05 M M CAB C NOTE 3 1 0.32 2.30 11X 0.40 PITCH 0.22 12X 0.69 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 12 NLSX5014 PACKAGE DIMENSIONS SOIC−14 D SUFFIX CASE 751A−03 ISSUE J −A− 14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −B− P 7 PL 0.25 (0.010) M B M 1 7 G C R X 45 _ F DIM A B C D F G J K M P R −T− SEATING PLANE D 14 PL 0.25 (0.010) K M M S J TB A S MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 SOLDERING FOOTPRINT 7X 7.04 1 0.58 14X 14X 1.52 1.27 PITCH DIMENSIONS: MILLIMETERS http://onsemi.com 13 NLSX5014 PACKAGE DIMENSIONS TSSOP−14 DT SUFFIX CASE 948G−01 ISSUE B 14X K REF 0.10 (0.004) 0.15 (0.006) T U S M TU S V S N 2X L/2 14 8 0.25 (0.010) M L PIN 1 IDENT. 1 7 B −U− N F DETAIL E K K1 J J1 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. MILLIMETERS INCHES MIN MAX MIN MAX 4.90 5.10 0.193 0.200 4.30 4.50 0.169 0.177 −−− 1.20 −−− 0.047 0.05 0.15 0.002 0.006 0.50 0.75 0.020 0.030 0.65 BSC 0.026 BSC 0.50 0.60 0.020 0.024 0.09 0.20 0.004 0.008 0.09 0.16 0.004 0.006 0.19 0.30 0.007 0.012 0.19 0.25 0.007 0.010 6.40 BSC 0.252 BSC 0_ 8_ 0_ 8_ SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE D G H DETAIL E DIM A B C D F G H J J1 K K1 L M SOLDERING FOOTPRINT 7.06 1 0.36 14X 14X 1.26 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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