NLX1G11AMX1TCG

NLX1G11 3-Input AND Gate The NLX1G11 is an advanced high−speed 3−input CMOS AND gate in ultra−small footprint. The NLX1G11 input structures provide protection when voltages up to 7.0 V are applied, regardless of the supply voltage. Features http://onsemi.com MARKING DIAGRAMS E ULLGA6 1.0 x 1.0 CASE 613AD M G • • • • • • • • High Speed: tPD = 2.4 ns (Typ) @ VCC = 5.0 V Designed for 1.65 V to 5.5 V VCC Operation Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C 24 mA Balanced Output Source and Sink Capability Balanced Propagation Delays Overvoltage Tolerant (OVT) Input Pins Ultra−Small Packages These are Pb−Free Devices 1 1 A 1 6 C ULLGA6 1.2 x 1.0 CASE 613AE M G 5 1 GND 2 5 VCC X M G ULLGA6 1.45 x 1.0 CASE 613AF = Device Marking = Date Code = Pb−Free Package AH M G B 3 4 Y Pin PIN ASSIGNMENT Function A GND B Y VCC C 1 2 3 4 Figure 1. Pinout (Top View) A B C & Y 5 6 FUNCTION TABLE Figure 2. Logic Symbol A L X X H Input B X L X H C X X L H Output Y L L L H H − HIGH Logic Level L − LOW Logic Level X = Either LOW or HIGH Logic Level ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2010 March, 2010 − Rev. 0 1 Publication Order Number: NLX1G11/D NLX1G11 MAXIMUM RATINGS Symbol VCC VIN VOUT IIK IOK IO ICC IGND TSTG TL TJ qJA PD MSL FR VESD DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature Under Bias Thermal Resistance (Note 1) Power Dissipation in Still Air @ 85°C Moisture Sensitivity Flammability Rating Oxygen ESD Withstand Voltage Index: 28 to 34 Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) VIN < GND VOUT < GND Parameter Value −0.5 to +7.0 −0.5 to +7.0 −0.5 to +7.0 −50 −50 ±50 ±100 ±100 −65 to +150 260 150 496 252 Level 1 UL 94 V−0 @ 0.125 in >2000 >200 N/A ±500 V Unit V V V mA mA mA mA mA °C °C °C °C/W mW ILATCHUP Latchup Performance Above VCC and Below GND at 125 °C (Note 5) mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow. 2. Tested to EIA/JESD22−A114−A. 3. Tested to EIA/JESD22−A115−A. 4. Tested to JESD22−C101−A. 5. Tested to EIA / JESD78. RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN VOUT TA Dt/DV Positive DC Supply Voltage Digital Input Voltage (Note 6) Output Voltage Operating Free−Air Temperature Input Transition Rise or Fall Rate VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5.0 V ± 0.5 V Parameter Operating Data Retention Only Min 1.65 1.5 0 0 −55 0 0 0 0 Max 5.5 5.5 5.5 5.5 +125 20 20 10 5 Unit V V V °C ns/V 6. Unused inputs may not be left open. All inputs must be tied to a high or low−logic input voltage level. http://onsemi.com 2 NLX1G11 DC ELECTRICAL CHARACTERISTICS Symbol VIH Parameter Low−Level Input Voltage Low−Level Input Voltage High− Level Output Voltage VIN = VIH or VIL IOH = −100 mA VIN = VIH or VIL IOH = −4 mA IOH = −8 mA IOH = −12 mA IOH = −16 mA IOH = −24 mA IOH = −32 mA VIN = VIH or VIL IOL = 100 mA VIN = VIH or VIL IOH = 4 mA IOH = 8 mA IOH = 12 mA IOH = 16 mA IOH = 24 mA IOH = 32 mA 0 v VIN v 5.5V Conditions VCC (V) 1.65 2.3 to 5.5 1.65 2.3 − 5.5 1.65 − 5.5 VCC−0.1 VCC TA = 25 5C Min 0.75 x VCC 0.70 x VCC 0.25 x VCC 0.30 x VCC VCC−0.1 Typ Max TA = −555C to +1255C Min 0.75 x VCC 0.70 x VCC 0.25 x VCC 0.30 x VCC V V Max Unit V VIL VOH 1.65 2.3 2.7 3.0 3.0 4.5 1.65 − 5.5 1.29 1.9 2.2 2.4 2.3 3.8 1.52 2.15 2.4 2.8 2.68 4.2 0.1 1.29 1.9 2.2 2.4 2.3 3.8 0.1 V VOL Low−Level Output Voltage 1.65 2.3 2.7 3.0 3.0 4.5 0 to 5.5 0.08 0.1 0.12 0.15 0.22 0.22 0.24 0.3 0.4 0.4 0.55 0.55 ±0.1 0.24 0.3 0.4 0.4 0.55 0.55 ±1.0 mA IIN Input Leakage Current Power−Off Output Leakage Current Quiescent Supply Current IOFF VIN or VOUT = 5.5 V 0 1.0 10 mA ICC 0 v VIN v VCC 5.5 1.0 10 mA http://onsemi.com 3 NLX1G11 AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 2.5 nS) VCC (V) 1.65−1.95 2.3−2.7 3.0−3.6 Test Condition RL = 1 MW, CL = 15 pF RL = 1 MW, CL = 15 pF RL = 1 MW, CL = 15 pF RL = 500 W, CL = 50 pF 4.5−5.5 RL = 1 MW, CL = 15 pF RL = 500 W, CL = 50 pF CIN CPD Input Capacitance Power Dissipation Capacitance (Note 7) 5.5 3.3 5.5 VIN = 0 V or VCC 10 MHz VIN = 0 V or VCC TA = 25 5C Min 2.0 0.8 0.5 1.5 0.5 0.8 Typ 5.5 3.0 2.6 3.0 2.2 2.4 4.0 20 26 Max 18.5 11 7.5 8.5 5.5 7.0 TA = −555C to +1255C Min 2.0 0.8 0.5 1.5 0.5 0.8 Max 19 11.5 8.0 9.0 6.0 7.5 pF pF Unit ns Symbol tPLH, tPHL Parameter Propagation Delay, Input to Output 7. CPD is defined as the value of the internal equivalent capacitance which is calculated from the dynamic operating current consumption without load. Average operating current can be obtained by the equation ICC(OPR) = CPD • VCC • fin + ICC. CPD is used to determine the no−load dynamic power consumption: PD = CPD • VCC2 • fin + ICC • VCC. http://onsemi.com 4 NLX1G11 A and B VCC 50% GND tPLH Y 50% VCC tPHL INPUT RL CL OUTPUT tR = tF = 2.5 ns, 10% to 90%, f = 1 MHz, tW = 500 ns A 1 MHz square input wave is recommended for propagation delay tests Figure 3. Switching Waveforms Figure 4. Test Circuit ORDERING INFORMATION Device NLX1G11AMX1TCG NLX1G11BMX1TCG NLX1G11CMX1TCG Package ULLGA6, 1.45 x 1.0, 0.5P (Pb−Free) ULLGA6, 1.2 x 1.0, 0.4P (Pb−Free) ULLGA6, 1.0 x 1.0, 0.35P (Pb−Free) Shipping† 3000 / Tape & Reel 3000 / Tape & Reel 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 NLX1G11 PACKAGE DIMENSIONS ULLGA6 1.0x1.0, 0.35P CASE 613AD−01 ISSUE A D A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM THE TERMINAL TIP. 4. A MAXIMUM OF 0.05 PULL BACK OF THE PLATED TERMINAL FROM THE EDGE OF THE PACKAGE IS ALLOWED. DIM A A1 b D E e L L1 SEATING PLANE MILLIMETERS MIN MAX −−− 0.40 0.00 0.05 0.12 0.22 1.00 BSC 1.00 BSC 0.35 BSC 0.25 0.35 0.30 0.40 PIN ONE REFERENCE 0.10 C 0.10 C 0.05 C 6X 0.05 C L1 1 ÉÉ ÉÉ ÉÉ 1 6 E TOP VIEW A SIDE VIEW A1 e 5X 3 C MOUNTING FOOTPRINT SOLDERMASK DEFINED* 0.48 5X 0.22 6X L NOTE 4 1.18 0.53 4 6X b 0.10 C A B 0.05 C NOTE 3 PKG OUTLINE 0.35 PITCH DIMENSIONS: MILLIMETERS BOTTOM VIEW *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 NLX1G11 PACKAGE DIMENSIONS ULLGA6 1.2x1.0, 0.4P CASE 613AE−01 ISSUE A D A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM THE TERMINAL TIP. 4. A MAXIMUM OF 0.05 PULL BACK OF THE PLATED TERMINAL FROM THE EDGE OF THE PACKAGE IS ALLOWED. DIM A A1 b D E e L L1 SEATING PLANE MILLIMETERS MIN MAX −−− 0.40 0.00 0.05 0.15 0.25 1.20 BSC 1.00 BSC 0.40 BSC 0.25 0.35 0.35 0.45 PIN ONE REFERENCE 0.10 C 0.10 C 0.05 C 6X 0.05 C L1 ÉÉ ÉÉ ÉÉ 1 6 E TOP VIEW A SIDE VIEW A1 e 3 C MOUNTING FOOTPRINT SOLDERMASK DEFINED* 0.49 5X 0.26 6X 5X L NOTE 4 1.24 4 0.53 6X 1 PKG OUTLINE b 0.10 C A B 0.05 C NOTE 3 0.40 PITCH DIMENSIONS: MILLIMETERS BOTTOM VIEW *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 NLX1G11 PACKAGE DIMENSIONS ULLGA6 1.45x1.0, 0.5P CASE 613AF−01 ISSUE A D A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM THE TERMINAL TIP. 4. A MAXIMUM OF 0.05 PULL BACK OF THE PLATED TERMINAL FROM THE EDGE OF THE PACKAGE IS ALLOWED. DIM A A1 b D E e L L1 MILLIMETERS MIN MAX −−− 0.40 0.00 0.05 0.15 0.25 1.45 BSC 1.00 BSC 0.50 BSC 0.25 0.35 0.30 0.40 PIN ONE REFERENCE 0.10 C 0.10 C 0.05 C 6X 0.05 C L1 1 PKG OUTLINE MiniGate is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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