NTB18N06LG

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Other names and brands may be claimed as the property of others. NTP18N06L, NTB18N06L Power MOSFET 15 Amps, 60 Volts, Logic Level N−Channel TO−220 and D2PAK http://onsemi.com Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. 15 AMPERES, 60 VOLTS RDS(on) = 100 mW Features • Pb−Free Packages are Available N−Channel D Typical Applications • • • • Power Supplies Converters Power Motor Controls Bridge Circuits G S MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating 4 Symbol Value Unit Drain−to−Source Voltage VDSS 60 Vdc Drain−to−Gate Voltage (RGS = 10 mW) VDGR 60 Vdc Gate−to−Source Voltage − Continuous − Non−Repetitive (tp v 10 ms) Drain Current − Continuous @ TC = 25°C − Continuous @ TC = 100°C − Single Pulse (tp v 10 ms) Total Power Dissipation @ TC = 25°C Derate above 25°C Operating and Storage Temperature Range Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 25 Vdc, VGS = 5.0 Vdc, VDS = 60 Vdc, IL(pk) = 11 A, L = 1.0 mH, RG = 25 W) Thermal Resistance − Junction−to−Case − Junction−to−Ambient Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds VGS ID ID 1 "10 "20 1 Adc Adc Apk PD 48.4 0.32 W W/°C TJ, Tstg −55 to +175 °C EAS 61 mJ D2PAK CASE 418AA STYLE 2 TO−220AB CASE 221A STYLE 5 2 3 MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain 4 Drain NTx 18N06LG AYWW NTx18N06LG AYWW 1 Gate °C/W RqJC RqJA 3.1 72.5 TL 260 1 Gate °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 2 3 Vdc 15 8.0 45 IDM 4 2 Drain 3 Source NTx18N06L x A Y WW G 2 Drain 3 Source = Device Code = B or P = Assembly Location = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2005 August, 2005 − Rev. 4 1 Publication Order Number: NTP18N06L/D NTP18N06L, NTB18N06L ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Characteristic Min Typ Max Unit 60 − 70 63.2 − − − − − − 1.0 10 − − ± 100 1.0 − 1.6 4.2 2.0 − − 85 100 − − 1.46 1.2 1.8 − gFS − 9.4 − mhos Ciss − 310 440 pF Coss − 106 150 Crss − 37 70 td(on) − 11 20 OFF CHARACTERISTICS V(BR)DSS Drain−to−Source Breakdown Voltage (Note 1) (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 60 Vdc) (VGS = 0 Vdc, VDS = 60 Vdc, TJ = 150°C) IDSS Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C mAdc nAdc ON CHARACTERISTICS (Note 1) Gate Threshold Voltage (Note 1) (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (Note 1) (VGS = 5.0 Vdc, ID = 7.5 Adc) RDS(on) Static Drain−to−Source On−Voltage (Note 1) (VGS = 5.0 Vdc, ID = 15 Adc) (VGS = 5.0 Vdc, ID = 7.5 Adc, TJ = 150°C) VDS(on) Forward Transconductance (Note 1) (VDS = 7.0 Vdc, ID = 6.0 Adc) Vdc mV/°C mW Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Gate Charge (VDD = 30 Vdc, ID = 15 Adc, VGS = 5.0 Vdc, RG = 9.1 W) (Note 1) (VDS = 48 Vdc, ID = 15 Adc, VGS = 5.0 Vdc) (Note 1) ns tr − 121 210 td(off) − 11 40 tf − 42 80 Qt − 7.3 20 Q1 − 1.9 − Q2 − 4.3 − VSD − − 0.96 0.83 1.2 − Vdc trr − 35 − ns ta − 23 − tb − 12 − QRR − 0.043 − nC SOURCE−DRAIN DIODE CHARACTERISTICS Diode Forward On−Voltage (IS = 15 Adc, VGS = 0 Vdc) (Note 1) (IS = 15 Adc, VGS = 0 Vdc, TJ = 150°C) Reverse Recovery Time Reverse Recovery Stored Charge (IS = 15 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) (Note 1) mC 1. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. 2. Switching characteristics are independent of operating junction temperature. ORDERING INFORMATION Package Shipping † NTP18N06L TO−220AB 50 Units/Rail NTP18N06LG TO−220AB (Pb−Free) 50 Units/Rail NTB18N06L D2PAK 50 Units/Rail NTB18N06LG D2PAK 50 Units/Rail Device (Pb−Free) NTB18N06LT4 D2PAK 800/Tape & Reel NTB18N06LT4G D2PAK 800/Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 2 NTP18N06L, NTB18N06L 32 32 8V 24 5V 4.5 V 16 4V 3.5 V 8 3V 0 0 VDS ≥ 10 V 6V ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) VGS = 10 V 2 4 6 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 24 16 TJ = 25°C 8 TJ = 100°C 0 8 1 VGS = 5 V 0.24 TJ = 100°C 0.16 TJ = 25°C TJ = −55°C 0 0 8 16 24 ID, DRAIN CURRENT (AMPS) 32 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.32 0.08 7 0.32 VGS = 10 V 0.24 TJ = 100°C 0.16 TJ = 25°C 0.08 TJ = −55°C 0 0 Figure 3. On−Resistance versus Gate−to−Source Voltage 8 16 24 ID, DRAIN CURRENT (AMPS) 32 Figure 4. On−Resistance versus Drain Current and Gate Voltage 2 1.8 2 3 4 5 6 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 2. Transfer Characteristics 10,000 VGS = 0 V ID = 7.5 A VGS = 5 V IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) Figure 1. On−Region Characteristics TJ = −55°C 1.6 1.4 1.2 1 TJ = 150°C 1000 100 TJ = 100°C 10 0.8 0.6 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) 1 175 0 Figure 5. On−Resistance Variation with Temperature 20 10 30 40 50 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 3 60 NTP18N06L, NTB18N06L POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted The capacitance (Ciss) is read from the capacitance curve at by recognizing that the power MOSFET is charge a voltage corresponding to the off−state condition when controlled. The lengths of various switching intervals (Dt) calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). are determined by how fast the FET input capacitance can At high switching speeds, parasitic circuit elements be charged by current from the generator. complicate the analysis. The inductance of the MOSFET The published capacitance data is difficult to use for source lead, inside the package and in the circuit wiring calculating rise and fall because drain−gate capacitance which is common to both the drain and gate current paths, varies greatly with applied voltage. Accordingly, gate produces a voltage at the source which reduces the gate drive charge data is used. In most cases, a satisfactory estimate of current. The voltage is determined by Ldi/dt, but since di/dt average input current (IG(AV)) can be made from a is a function of drain current, the mathematical solution is rudimentary analysis of the drive circuit so that complex. The MOSFET output capacitance also t = Q/IG(AV) complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the During the rise and fall time interval when switching a resistance of the driving source, but the internal resistance resistive load, VGS remains virtually constant at a level is difficult to measure and, consequently, is not specified. known as the plateau voltage, VSGP. Therefore, rise and fall The resistive switching time variation versus gate times may be approximated by the following: resistance (Figure 9) shows how typical switching tr = Q2 x RG/(VGG − VGSP) performance is affected by the parasitic circuit elements. If tf = Q2 x RG/VGSP the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. where The circuit used to obtain the data is constructed to minimize VGG = the gate drive voltage, which varies from zero to VGG common inductance in the drain and gate circuit loops and RG = the gate drive resistance is believed readily achievable with board mounted and Q2 and VGSP are read from the gate charge curve. components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which During the turn−on and turn−off delay times, gate current is approximates an optimally snubbed inductive load. Power not constant. The simplest calculation uses appropriate MOSFETs may be safely operated into an inductive load; values from the capacitance curves in a standard equation for however, snubbing reduces switching losses. voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 1200 VDS = 0 V VGS = 0 V TJ = 25°C C, CAPACITANCE (pF) 1000 Ciss 800 600 Crss 400 Ciss 200 Coss Crss 0 10 5 0 VGS 5 10 15 20 25 VDS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 4 1000 6 VDS = 30 V ID = 15 A VGS = 5 V QT Q2 Q1 4 t, TIME (ns) VGS , GATE−TO−SOURCE VOLTAGE (VOLTS) NTP18N06L, NTB18N06L VGS 2 tr 100 tf td(off) 10 td(on) ID = 15 A TJ = 25°C 0 1 0 2 4 6 QG, TOTAL GATE CHARGE (nC) 8 1 Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge 10 RG, GATE RESISTANCE (W) 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS IS, SOURCE CURRENT (AMPS) 16 VGS = 0 V 12 8 4 TJ = 150°C TJ = 25°C 0 0.3 0.4 0.5 0.8 0.9 0.6 0.7 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 1 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance The Forward Biased Safe Operating Area curves define dissipated in the transistor while in avalanche must be less the maximum simultaneous drain−to−source voltage and than the rated limit and adjusted for operating conditions drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak differing from those specified. Although industry practice is junction temperature and a case temperature (TC) of 25°C. to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an Peak repetitive pulsed power limits are determined by using increase of peak current in avalanche and peak junction the thermal response data in conjunction with the procedures temperature. discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.” Although many E−FETs can withstand the stress of Switching between the off−state and the on−state may drain−to−source avalanche at currents up to rated pulsed traverse any load line provided neither rated peak current current (IDM), the energy rating is specified at rated (IDM) nor rated voltage (VDSS) is exceeded and the continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown transition time (tr,tf) do not exceed 10 ms. In addition the total in the accompanying graph (Figure 12). Maximum energy at power averaged over a complete switching cycle must not currents below rated continuous ID can safely be assumed to exceed (TJ(MAX) − TC)/(RqJC). equal the values indicated. A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 5 NTP18N06L, NTB18N06L I D, DRAIN CURRENT (AMPS) 100 VGS = 15 V SINGLE PULSE TC = 25°C 10 ms 100 ms 10 1 ms 10 ms 1 dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 10 1 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 100 EAS , SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) SAFE OPERATING AREA r(t), TRANSIENT THERMAL RESISTANCE Figure 11. Maximum Rated Forward Biased Safe Operating Area 70 ID = 11 A 60 50 40 30 20 10 0 25 175 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature 1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 SINGLE PULSE 0.000001 0.00001 0.0001 0.001 t, TIME (s) 0.01 0.1 Figure 13. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 6 1 10 NTP18N06L, NTB18N06L PACKAGE DIMENSIONS D2PAK CASE 418AA−01 ISSUE O C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E V W −B− 4 DIM A B C D E F G J K M S V A 1 2 S 3 −T− SEATING PLANE K W J G D 3 PL 0.13 (0.005) T B M STYLE 2: PIN 1. 2. 3. 4. M VARIABLE CONFIGURATION ZONE U M INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.036 0.045 0.055 0.310 −−− 0.100 BSC 0.018 0.025 0.090 0.110 0.280 −−− 0.575 0.625 0.045 0.055 M M F F F VIEW W−W 1 VIEW W−W 2 VIEW W−W 3 SOLDERING FOOTPRINT* 8.38 0.33 1.016 0.04 10.66 0.42 5.08 0.20 3.05 0.12 17.02 0.67 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 GATE DRAIN SOURCE DRAIN MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.92 1.14 1.40 7.87 −−− 2.54 BSC 0.46 0.64 2.29 2.79 7.11 −−− 14.60 15.88 1.14 1.40 NTP18N06L, NTB18N06L PACKAGE DIMENSIONS TO−220 CASE 221A−09 ISSUE AA −T− B SEATING PLANE C F T S 4 DIM A B C D F G H J K L N Q R S T U V Z A Q 1 2 3 U H K Z L R V J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. G D N INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 −−− −−− 0.080 STYLE 5: PIN 1. 2. 3. 4. MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 −−− −−− 2.04 GATE DRAIN SOURCE DRAIN ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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