NTB30N06LG

NTP30N06L, NTB30N06L Power MOSFET 30 Amps, 60 Volts, Logic Level, N−Channel TO−220 and D2PAK Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. http://onsemi.com 30 AMPERES, 60 VOLTS RDS(on) = 46 mW Features • Pb−Free Packages are Available D Typical Applications • • • • Power Supplies Converters Power Motor Controls Bridge Circuits N−Channel G S MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−to−Source Voltage VDSS 60 Vdc Drain−to−Gate Voltage (RGS = 10 MW) VDGR 60 Vdc Gate−to−Source Voltage − Continuous − Non−Repetitive (tpv10 ms) Drain Current − Continuous @ TA = 25°C − Continuous @ TA = 100°C − Single Pulse (tpv10 ms) MARKING DIAGRAMS 4 Drain 4 Vdc VGS VGS TO−220 CASE 221A STYLE 5 NTx30N06LG AYWW 30 15 90 Adc PD 88.2 0.59 W W/°C Operating and Storage Temperature Range TJ, Tstg −55 to +175 °C 2 Drain Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 50 Vdc, VGS = 5.0 Vdc, L = 0.3 mH IL(pk) = 26 A, VDS = 60 Vdc) EAS 101 mJ 4 Drain Thermal Resistance, Junction−to−Case RqJC 1.7 °C/W TL 260 °C Total Power Dissipation @ TA = 25°C Derate above 25°C Maximum Lead Temperature for Soldering Purposes, 1/8 in from case for 10 seconds ID ID "15 "20 IDM Apk 1 2 1 Gate 3 4 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 2 1 D2PAK CASE 418B STYLE 2 3 Source NTx 30N06LG AYWW 3 2 1 3 Drain Gate Source NTx30N06L x A Y WW G = Device Code = P or B = Assembly Location = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2006 January, 2006 − Rev. 4 1 Publication Order Number: NTP30N06L/D NTP30N06L, NTB30N06L ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Drain−to−Source Breakdown Voltage (Note 1) (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) V(BR)DSS Unit 60 − 71.8 69 − − − − − − 1.0 10 − − ±100 1.0 − 1.7 4.8 2.0 − − 38 46 − − 1.3 1.06 1.7 − gFS − 21 − mhos Ciss − 810 1150 pF Coss − 260 370 Crss − 80 115 td(on) − 10 20 OFF CHARACTERISTICS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) IDSS Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C mAdc nAdc ON CHARACTERISTICS (Note 1) Gate Threshold Voltage (Note 1) (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (Note 1) (VGS = 5.0 Vdc, ID = 15 Adc) RDS(on) Static Drain−to−Source On−Voltage (Note 1) (VGS = 5.0 Vdc, ID = 30 Adc) (VGS = 5.0 Vdc, ID = 15 Adc, TJ = 150°C) VDS(on) Forward Transconductance (Note 1) (VDS = 7.0 Vdc, ID = 15 Adc) Vdc mV/°C mW Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = 30 Vdc, ID = 30 Adc, VGS = 5.0 Vdc, RG = 9.1 W) (Note 1) Fall Time Gate Charge (VDS = 48 Vdc, ID = 30 Adc, VGS = 5.0 Vdc) (Note 1) ns tr − 200 400 td(off) − 15.6 30 tf − 62 120 QT − 16 32 Q1 − 3.9 − Q2 − 10 − VSD − − 1.01 1.03 1.2 − Vdc trr − 50 − ns ta − 32 − tb − 17 − QRR − 0.082 − nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 30 Adc, VGS = 0 Vdc) (Note 1) (IS = 30 Adc, VGS = 0 Vdc, TJ = 150°C) Reverse Recovery Time (IS = 30 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) (Note 1) Reverse Recovery Stored Charge 1. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 2. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 mC NTP30N06L, NTB30N06L 60 60 50 8V 40 6V VDS ≥ 10 V 5.5 V ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) VGS = 10 V 5V 4.5 V 30 4V 20 3.5 V 10 3V 50 40 30 20 TJ = 25°C 10 TJ = 100°C TJ = −55°C 0 1.5 0 0 1 2 3 4 5 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 6 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) VGS = 5 V 0.08 TJ = 100°C 0.06 TJ = 25°C 0.04 TJ = −55°C 0.02 0 0 10 20 30 40 50 60 0.1 VGS = 10 V 0.08 0.06 TJ = 100°C 0.04 TJ = 25°C TJ = −55°C 0.02 0 0 10 20 30 40 50 60 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Gate−to−Source Voltage Figure 4. On−Resistance versus Drain Current and Gate Voltage 10000 2 VGS = 0 V ID = 15 A VGS = 5 V IDSS, LEAKAGE (nA) 1.8 6.5 Figure 2. Transfer Characteristics 0.1 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) Figure 1. On−Region Characteristics 3.5 2.5 4.5 5.5 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 1.6 1.4 1.2 1 TJ = 150°C 1000 100 TJ = 100°C 0.8 0.6 −50 −25 10 0 25 50 75 100 125 150 175 0 10 20 30 40 50 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 3 60 2800 VDS = 0 V VGS = 0 V TJ = 25°C C, CAPACITANCE (pF) 2400 2000 Ciss 1600 1200 Crss Ciss 800 Coss 400 Crss 0 10 5 VGS 0 VDS 5 10 15 20 25 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) NTP30N06L, NTB30N06L 6 QT 5 Q1 Q2 4 VGS 3 2 1 ID = 30 A TJ = 25°C 0 0 4 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) 20 IS, SOURCE CURRENT (AMPS) 32 tr t, TIME (ns) 16 Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge 1000 100 tf 10 td(off) VDS = 30 V ID = 30 A VGS = 5 V td(on) 1 10 VGS = 0 V TJ = 25°C 24 16 8 0 0.6 100 1000 TC = 25°C TJ = 175°C SINGLE PULSE 10 ms 10 1 ms 100 ms 10 ms 1 RDS(on) Limit Thermal Limit Package Limit 0.1 0.1 1 0.76 0.84 0.92 1 1.08 dc 10 100 Figure 10. Diode Forward Voltage versus Current EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) Figure 9. Resistive Switching Time Variation versus Gate Resistance 100 0.68 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) RG, GATE RESISTANCE (W) ID, DRAIN CURRENT (AMPS) 12 Qg, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation 1 8 120 ID = 26 A 100 80 60 40 20 0 25 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 50 75 100 125 150 175 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 4 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) NTP30N06L, NTB30N06L 1 D = 0.5 0.2 P(pk) 0.1 0.05 t1 0.01 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 0.1 0.0001 0.001 0.01 RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RqJC(t) 0.1 1 10 t, TIME (s) Figure 13. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform ORDERING INFORMATION Package Shipping † TO−220 50 Units / Rail TO−220 (Pb−Free) 50 Units / Rail NTB30N06L D2PAK 50 Units / Rail NTB30N06LG D2PAK 50 Units / Rail Device NTP30N06L NTP30N06LG (Pb−Free) NTB30N06LT4 D2PAK 800 Tape & Reel NTB30N06LT4G D2PAK 800 Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TO−220 CASE 221A ISSUE AK DATE 13 JAN 2022 SCALE 1:1 STYLE 1: PIN 1. 2. 3. 4. BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. BASE EMITTER COLLECTOR EMITTER STYLE 3: PIN 1. 2. 3. 4. CATHODE ANODE GATE ANODE STYLE 4: PIN 1. 2. 3. 4. MAIN TERMINAL 1 MAIN TERMINAL 2 GATE MAIN TERMINAL 2 STYLE 5: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN STYLE 6: PIN 1. 2. 3. 4. ANODE CATHODE ANODE CATHODE STYLE 7: PIN 1. 2. 3. 4. CATHODE ANODE CATHODE ANODE STYLE 8: PIN 1. 2. 3. 4. CATHODE ANODE EXTERNAL TRIP/DELAY ANODE STYLE 9: PIN 1. 2. 3. 4. GATE COLLECTOR EMITTER COLLECTOR STYLE 10: PIN 1. 2. 3. 4. GATE SOURCE DRAIN SOURCE STYLE 11: PIN 1. 2. 3. 4. DRAIN SOURCE GATE SOURCE STYLE 12: PIN 1. 2. 3. 4. MAIN TERMINAL 1 MAIN TERMINAL 2 GATE NOT CONNECTED DOCUMENT NUMBER: DESCRIPTION: 98ASB42148B TO−220 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS D2PAK 3 CASE 418B−04 ISSUE L DATE 17 FEB 2015 SCALE 1:1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 418B−01 THRU 418B−03 OBSOLETE, NEW STANDARD 418B−04. C E −B− V W 4 1 2 A S 3 −T− SEATING PLANE K W J G D DIM A B C D E F G H J K L M N P R S V H 3 PL 0.13 (0.005) M T B M VARIABLE CONFIGURATION ZONE N R P L M STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR L M F F F VIEW W−W 1 VIEW W−W 2 VIEW W−W 3 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 7.87 8.89 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 1.32 1.83 7.11 8.13 5.00 REF 2.00 REF 0.99 REF 14.60 15.88 1.14 1.40 U L M INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.310 0.350 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.052 0.072 0.280 0.320 0.197 REF 0.079 REF 0.039 REF 0.575 0.625 0.045 0.055 STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 5: STYLE 6: PIN 1. CATHODE PIN 1. NO CONNECT 2. ANODE 2. CATHODE 3. CATHODE 3. ANODE 4. ANODE 4. CATHODE MARKING INFORMATION AND FOOTPRINT ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42761B D2PAK 3 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com D2PAK 3 CASE 418B−04 ISSUE L DATE 17 FEB 2015 GENERIC MARKING DIAGRAM* xx xxxxxxxxx AWLYWWG xxxxxxxxG AYWW AYWW xxxxxxxxG AKA IC Standard Rectifier xx A WL Y WW G AKA = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package = Polarity Indicator *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. SOLDERING FOOTPRINT* 10.49 8.38 16.155 2X 3.504 2X 1.016 5.080 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98ASB42761B D2PAK 3 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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