NTGS4111PT2G

NTGS4111P, NVGS4111P MOSFET – Power, Single, P-Channel, TSOP-6 -30 V, -4.7 A Features • • • • • • Leading −30 V Trench Process for Low RDS(on) Low Profile Package Suitable for Portable Applications Surface Mount TSOP−6 Package Saves Board Space Improved Efficiency for Battery Applications NV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable Pb−Free Package is Available http://onsemi.com V(BR)DSS RDS(on) TYP ID MAX 38 mW @ −10 V −30 V −4.7 A 68 mW @ −4.5 V P−Channel 1 2 5 6 Applications • Battery Management and Switching • Load Switching • Battery Protection 3 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Symbol Value Unit Drain−to−Source Voltage VDSS −30 V Gate−to−Source Voltage VGS ±20 V ID −3.7 A Rating Continuous Drain Current (Note 1) Steady State TA = 25°C t≤5s TA = 25°C Power Dissipation (Note 1) Steady State TA = 25°C TA = 85°C Steady State −4.7 PD Power Dissipation (Note 2) Pulsed Drain Current ID TA = 85°C TA = 25°C W −2.6 A −1.9 PD 0.63 W IDM −15 A TJ, TSTG −55 to 150 °C Source Current (Body Diode) IS −1.7 A Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C tp = 10 ms Operating Junction and Storage Temperature Drain Drain Source 6 5 4 1 1.25 2.0 TA = 25°C MARKING DIAGRAM & PIN ASSIGNMENT −2.7 t≤5s Continuous Drain Current (Note 2) 4 TSOP−6 CASE 318G STYLE 1 XX M G XX M G G 1 2 3 Drain Drain Gate = Specific Device Code = Date Code* = Pb−Free Package (Note: Microdot may be in either location) *Date Code orientation may vary depending upon manufacturing location. ORDERING INFORMATION See detailed ordering and shipping information ion page 6 of this data sheet. THERMAL RESISTANCE RATINGS Rating Symbol Max Unit Junction−to−Ambient – Steady State (Note 1) RqJA 100 °C/W Junction−to−Ambient – t ≤ 5 s (Note 1) RqJA 62.5 Junction−to−Ambient – Steady State (Note 2) RqJA 200 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces). © Semiconductor Components Industries, LLC, 2014 May, 2019 − Rev. 4 1 Publication Order Number: NTGS4111P/D NTGS4111P, NVGS4111P 2. Surface−mounted on FR4 board using the minimum recommended pad size (Cu area = 0.006 in sq). http://onsemi.com 2 NTGS4111P, NVGS4111P ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = −250 mA −30 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current V −17 VGS = 0 V, VDS = −24 V mV/°C TJ = 25°C −1.0 TJ = 125°C −100 IGSS VDS = 0 V, VGS = ±20 V VGS(TH) VGS = VDS, ID = −250 mA mA ±100 nA −3.0 V ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient −1.0 VGS(TH)/TJ Drain−to−Source On Resistance Forward Transconductance RDS(on) gFS 5.0 VGS = −10 V, ID = −3.7 A mV/°C mW 38 60 VGS = −4.5 V, ID = −2.7 A 68 110 VDS = −10 V, ID = −3.7 A 6.0 S 750 pF CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance VGS = 0 V, f = 1.0 MHz, VDS = −15 V CRSS Total Gate Charge QG(TOT) Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD 140 105 15.25 32 nC ns 0.8 VGS = −10 V, VDD = −15 V, ID = −3.7 A 2.6 3.4 SWITCHING CHARACTERISTICS, VGS = −10 V (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(ON) 9.0 17 tr 9.0 18 38 85 22 45 11 20 15 28 28 56 22 50 Typ Max Unit TJ = 25°C −0.76 −1.2 V TJ = 125°C −0.60 40 ns VGS = −10 V, VDD = −15 V, ID = −1.0 A, RG = 6.0 W td(OFF) tf SWITCHING CHARACTERISTICS, VGS = −4.5 V (Note 4) Turn−On Delay Time Rise Time td(ON) tr Turn−Off Delay Time Fall Time VGS = −4.5 V, VDD = −15 V, ID = −1.0 A, RG = 6.0 W td(OFF) tf ns DRAIN − SOURCE DIODE CHARACTERISTICS Characteristic Forward Diode Voltage Reverse Recovery Time Symbol VDS VGS = 0 V, IS = −1.0 A tRR Charge Time ta Discharge Time tb Reverse Recovery Charge Test Condition Min 17 VGS = 0 V dIS/dt = 100 A/ms, IS = −1.0 A QRR 9.0 8.0 8.0 nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 3 NTGS4111P, NVGS4111P TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) −4.5 V −4.2 V −10V 11 10 9 12 −4 V −ID, DRAIN CURRENT (AMPS) −ID, DRAIN CURRENT (AMPS) 12 −8 V −6 V 8 7 −3.8 V −5.5 V −5 V 6 −3.6 V 5 4 3 −3.4 V −3.2 V 2 1 0 −3 V TJ = 25°C 0 0.8 0.4 1.2 1.6 2 2.4 2.8 3.2 3.6 4 VDS ≥ −10 V 11 10 9 8 7 6 5 4 100°C 3 2 1 0 25°C TJ = −55°C 1 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ = 25°C ID = −3.7 A 0.2 0.1 0 2 3 4 5 6 7 9 8 10 −VGS, GATE VOLTAGE (VOLTS) 0.1 TJ = 25°C VGS = −4.5 V 0.05 VGS = −10 V 0 2.0 −IDSS, LEAKAGE CURRENT (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 4.0 Figure 4. On−Resistance vs. Drain Current and Gate Voltage 100000 ID = −3.7 A VGS = −10 V 3.0 −ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance vs. Gate−to−Source Voltage 1.5 5 Figure 2. Transfer Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) Figure 1. On−Region Characteristics 1.5 2 2.5 3 3.5 4 4.5 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) VGS = 0 V TJ = 150°C 10000 1.0 0.5 −50 −25 0 25 50 75 100 125 150 1000 TJ = 100°C 100 TJ, JUNCTION TEMPERATURE (°C) 15 10 20 25 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage 5 http://onsemi.com 4 30 NTGS4111P, NVGS4111P TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) C, CAPACITANCE (pF) 20 12 TJ = 25°C QT 10 Ciss 20 25 30 VDS 8 10 6 QGS 4 0 ID = −3.7 A TJ = 25°C 0 1 2 0 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Qg, TOTAL GATE CHARGE (nC) Figure 8. Gate−to−Source Voltage vs. Total Gate Charge Figure 7. Capacitance Variation 100 10 10 100 ms 1 ms 1 VGS = −20 V SINGLE PULSE TC = 25°C 0.1 0.01 0.1 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT dc 10 1 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS = 0 V −IS, SOURCE CURRENT (AMPS) −I D, DRAIN CURRENT (AMPS) QGD 2 −GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ = 150°C 1 0.1 0.3 100 1 0.1 TJ = 100°C TJ = 25°C TJ = −55°C 0.4 0.5 0.6 0.7 0.8 0.9 1.1 1.0 −VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 9. Maximum Rated Forward Biased Safe Operating Area Rthja(t), EFFECTIVE TRANSIENT THERMAL RESPONSE VGS −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 1400 Ciss 1300 1200 C rss 1100 1000 900 800 700 600 500 400 300 Coss 200 100 VDS = 0 V VGS = 0 V Crss 0 10 0 10 5 5 15 −VGS −VDS Figure 10. Diode Forward Voltage vs. Current D = 0.5 0.2 0.1 0.05 0.02 0.01 0.01 0.001 0.0001 1E−07 Single Pulse 1E−06 1E−05 1E−04 1E−03 1E−02 1E−01 t, TIME (s) Figure 11. FET Thermal Response http://onsemi.com 5 1E+00 1E+01 1E+02 1E+03 NTGS4111P, NVGS4111P Table 1. ORDERING INFORMATION Marking (XX) Package Shipping† NTGS4111PT1 TG SC−88 3000 / Tape & Reel NTGS4111PT1G TG SC−88 (Pb−Free) 3000 / Tape & Reel NVGS4111PT1G VTG SC−88 (Pb−Free) 3000 / Tape & Reel Part Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSOP−6 CASE 318G−02 ISSUE V 1 SCALE 2:1 D H ÉÉ ÉÉ 6 E1 1 NOTE 5 5 2 L2 4 GAUGE PLANE E 3 L b SEATING PLANE C DETAIL Z e DIM A A1 b c D E E1 e L L2 M c A 0.05 M DATE 12 JUN 2012 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H. 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE. A1 DETAIL Z MIN 0.90 0.01 0.25 0.10 2.90 2.50 1.30 0.85 0.20 0° MILLIMETERS NOM MAX 1.00 1.10 0.06 0.10 0.38 0.50 0.18 0.26 3.00 3.10 2.75 3.00 1.50 1.70 0.95 1.05 0.40 0.60 0.25 BSC 10° − STYLE 1: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN STYLE 2: PIN 1. EMITTER 2 2. BASE 1 3. COLLECTOR 1 4. EMITTER 1 5. BASE 2 6. COLLECTOR 2 STYLE 3: PIN 1. ENABLE 2. N/C 3. R BOOST 4. Vz 5. V in 6. V out STYLE 4: PIN 1. N/C 2. V in 3. NOT USED 4. GROUND 5. ENABLE 6. LOAD STYLE 5: PIN 1. EMITTER 2 2. BASE 2 3. COLLECTOR 1 4. EMITTER 1 5. BASE 1 6. COLLECTOR 2 STYLE 6: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. EMITTER 5. COLLECTOR 6. COLLECTOR STYLE 7: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. N/C 5. COLLECTOR 6. EMITTER STYLE 8: PIN 1. Vbus 2. D(in) 3. D(in)+ 4. D(out)+ 5. D(out) 6. GND STYLE 9: PIN 1. LOW VOLTAGE GATE 2. DRAIN 3. SOURCE 4. DRAIN 5. DRAIN 6. HIGH VOLTAGE GATE STYLE 10: PIN 1. D(OUT)+ 2. GND 3. D(OUT)− 4. D(IN)− 5. VBUS 6. D(IN)+ STYLE 11: PIN 1. SOURCE 1 2. DRAIN 2 3. DRAIN 2 4. SOURCE 2 5. GATE 1 6. DRAIN 1/GATE 2 STYLE 12: PIN 1. I/O 2. GROUND 3. I/O 4. I/O 5. VCC 6. I/O STYLE 13: PIN 1. GATE 1 2. SOURCE 2 3. GATE 2 4. DRAIN 2 5. SOURCE 1 6. DRAIN 1 STYLE 14: PIN 1. ANODE 2. SOURCE 3. GATE 4. CATHODE/DRAIN 5. CATHODE/DRAIN 6. CATHODE/DRAIN STYLE 15: PIN 1. ANODE 2. SOURCE 3. GATE 4. DRAIN 5. N/C 6. CATHODE STYLE 16: PIN 1. ANODE/CATHODE 2. BASE 3. EMITTER 4. COLLECTOR 5. ANODE 6. CATHODE STYLE 17: PIN 1. EMITTER 2. BASE 3. ANODE/CATHODE 4. ANODE 5. CATHODE 6. COLLECTOR GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 6X 0.60 XXXAYWG G 1 6X 3.20 XXX A Y W G 0.95 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98ASB14888C TSOP−6 1 IC 0.95 XXX MG G = Specific Device Code =Assembly Location = Year = Work Week = Pb−Free Package STANDARD XXX = Specific Device Code M = Date Code G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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