NTHS5441

NTHS5441 Power MOSFET −20 V, −5.3 A, P−Channel ChipFET] Features • • • • • Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Miniature ChipFET Surface Mount Package Pb−Free Package is Available http://onsemi.com V(BR)DSS −20 V RDS(on) TYP 46 mW @ −4.5 V S ID MAX −5.3 A Applications • Power Management in Portable and Battery−Powered Products; i.e., Cellular and Cordless Telephones and PCMCIA Cards MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Rating Drain−Source Voltage Gate−Source Voltage Continuous Drain Current (TJ = 150°C) (Note 1) TA = 25°C TA = 85°C Pulsed Drain Current Continuous Source Current (Note 1) Maximum Power Dissipation (Note 1) TA = 25°C TA = 85°C Operating Junction and Storage Temperature Range Symbol VDS VGS ID −5.3 −3.8 IDM IS PD 2.5 1.3 TJ, Tstg 1.3 0.7 °C −5.3 "20 −3.9 −3.9 −2.8 A A W D D D S 8 7 6 5 1 2 3 4 G 5 sec Steady State −20 Unit V V A 8 D P−Channel MOSFET "12 ChipFET CASE 1206A STYLE 1 1 PIN CONNECTIONS D D D G 1 2 3 4 MARKING DIAGRAM 8 A3 MG G 7 6 5 −55 to +150 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces). A3 = Specific Device Code M = Month Code G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device NTHS5441T1 NTHS5441T1G Package ChipFET ChipFET (Pb−Free) Shipping† 3000/Tape & Reel 3000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2005 1 July, 2005 − Rev. 13 Publication Order Number: NTHS5441T1/D NTHS5441 THERMAL CHARACTERISTICS Characteristic Maximum Junction−to−Ambient (Note 2) t v 5 sec Steady State Maximum Junction−to−Foot (Drain) Steady State Symbol RqJA Typ 40 80 15 Max 50 95 20 °C/W Unit °C/W RqJF ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Static Gate Threshold Voltage Gate−Body Leakage Zero Gate Voltage Drain Current VGS(th) IGSS IDSS VDS = VGS, ID = −250 mA VDS = 0 V, VGS = "12 V VDS = −16 V, VGS = 0 V VDS = −16 V, VGS = 0 V, TJ = 85°C On−State Drain Current (Note 3) Drain−Source On−State Resistance (Note 3) ID(on) rDS(on) VDS v −5.0 V, VGS = −4.5 V VGS = −3.6 V, ID = −3.7 A VGS = −4.5 V, ID = −3.9 A VGS = −2.5 V, ID = −3.1 A Forward Transconductance (Note 3) Diode Forward Voltage (Note 3) Dynamic (Note 4) Total Gate Charge Gate−Source Charge Gate−Drain Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Source−Drain Reverse Recovery Time QG QGS QGD Ciss Coss Crss td(on) tr td(off) tf trr IF = −1.1 A, di/dt = 100 A/ms VDD = −10 V, RL = 10 W ID ^ −1.0 A, VGEN = −4.5 V, RG = 6 W VDS = −5.0 Vdc, VGS = 0 Vdc, f = 1.0 MHz VDS = −10 V, VGS = −4.5 V, ID = −3.9 A 9.7 1.2 3.6 710 400 140 14 22 42 35 30 30 55 100 70 60 ns pF 22 nC gfs VSD VDS = −10 V, ID = −3.9 A IS = −2.1 A, VGS = 0 V −20 − − 0.050 0.046 0.070 12 −0.8 −1.2 0.06 − 0.083 mhos V −0.6 −1.2 "100 −1.0 −5.0 A W V nA mA Symbol Test Condition Min Typ Max Unit 2. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces). 3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%. 4. Guaranteed by design, not subject to production testing. http://onsemi.com 2 NTHS5441 TYPICAL ELECTRICAL CHARACTERISTICS 20 −ID, DRAIN CURRENT (AMPS) −5 V −3.5 V −3 V −ID, DRAIN CURRENT (AMPS) TJ = 25°C 20 TJ = −55°C 16 25°C 12 125°C 16 −4.5 V −4 V 12 −2.5 V 8 −2 V 4 0 0 0.5 1 1.5 2 VGS = −1.5 V 8 4 0 2.5 3 0 0.5 1 1.5 2 2.5 3 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.2 ID = −3.9 A TJ = 25°C 0.15 0.2 Figure 2. Transfer Characteristics TJ = 25°C 0.15 VGS = 2.5 V 0.1 VGS = 3.6 V 0.05 VGS = 4.5 V 0.1 0.05 0 0 1 2 3 4 5 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 0 2 6 10 14 18 20 −ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Gate−to−Source Voltage 1.6 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) ID = −3.9 A VGS = −4.5 V 1.4 Figure 4. On−Resistance versus Drain Current and Gate Voltage 1.2 1 0.8 0.6 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 5. On−Resistance Variation with Temperature http://onsemi.com 3 NTHS5441 TYPICAL ELECTRICAL CHARACTERISTICS −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 1500 TJ = 25°C VGS = 0 5 11 QG 4 10 9 8 7 C, CAPACITANCE (pF) 1200 900 3 Ciss Coss QGS 2 6 600 QGD ID = −3.9 A TJ = 25°C QGD/QGS = 3.0 0 1 2 3 4 5 6 7 8 9 5 4 3 2 1 0 10 300 0 0 1 Crss 0 4 8 12 16 20 −VDS, DRAIN−TO−SOURCE VOLTAGE () QG, TOTAL GATE CHARGE (nC) Figure 6. Capacitance Variation Figure 7. Gate−to−Source and Drain−to−Source Voltage versus Total Charge NORMALIZED EFFECTIVE TRANSIENT THERMAL IMPEDANCE 1 Duty Cycle = 0.5 0.2 0.1 0.05 0.02 Single Pulse 0.0001 0.001 0.01 0.1 1 10 100 1000 t2 DUTY CYCLE, D = t1/t2 t1 PDM PER UNIT BASE = RqJA = 80°C/W TJM − TA = PDMZqJA(t) SURFACE MOUNTED 0.1 0.01 SQUARE WAVE PULSE DURATION (sec) Figure 8. Normalized Thermal Transient Impedance, Junction−to−Ambient 5 −IS, SOURCE CURRENT (AMPS) 4 VGS = 0 V TJ = 25°C 3 2 1 0 0.1 0.3 0.5 0.7 0.9 −VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 9. Diode Forward Voltage versus Current http://onsemi.com 4 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) NTHS5441 PACKAGE DIMENSIONS ChipFET] CASE 1206A−03 ISSUE G D 8 7 6 5 q L 5 6 3 7 2 8 1 HE 1 2 3 4 E 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE. 4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL AND VERTICAL SHALL NOT EXCEED 0.08 MM. 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS. 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE. DIM A b c D E e e1 L HE q MIN 1.00 0.25 0.10 2.95 1.55 MILLIMETERS NOM MAX 1.05 1.10 0.30 0.35 0.15 0.20 3.05 3.10 1.65 1.70 0.65 BSC 0.55 BSC 0.28 0.35 0.42 1.80 1.90 2.00 5° NOM MIN 0.039 0.010 0.004 0.116 0.061 INCHES NOM 0.041 0.012 0.006 0.120 0.065 0.025 BSC 0.022 BSC 0.014 0.011 0.071 0.075 5° NOM MAX 0.043 0.014 0.008 0.122 0.067 e1 e b c A 0.05 (0.002) 0.017 0.079 SOLDERING FOOTPRINT* 2.032 0.08 0.457 0.018 0.635 0.025 1.727 0.068 2.032 0.08 0.457 0.018 0.711 0.028 0.66 0.026 SCALE 20:1 mm inches 0.178 0.007 0.711 0.028 0.66 0.026 SCALE 20:1 mm inches Basic Styles 1 and 4 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 5 NTHS5441 ChipFET is a trademark of Vishay Siliconix. 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