NTMD5836NLR2G

NTMD5836NL Power MOSFET 40 V, Dual N−Channel, SOIC−8 Features • • • • • Asymmetrical N Channels Low RDS(on) Low Capacitance Optimized Gate Charge These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant ID Max (Notes 1 and 2) 11 A G1 http://onsemi.com N−Channel 1 D1 N−Channel 2 D2 V(BR)DSS Channel 1 40 V RDS(on) Max 12 mW @ 10 V 16 mW @ 4.5 V G2 S1 S2 Channel 2 40 V 25 mW @ 10 V 30.8 mW @ 4.5 V 6.5 A 1. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces) 2. Only selected channel is been powered 1W applied on channel 1: TJ = 1 W * 85°C/W + 25°C = 110°C MARKING DIAGRAM* AND PIN ASSIGNMENT 8 1 SOIC−8 CASE 751 D1 D1 D2 D2 8 5836NL AYWW G G 1 S1 G1 S2 G2 A Y WW G = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device NTMD5836NLR2G Package SOIC−8 (Pb−Free) Shipping† 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D © Semiconductor Components Industries, LLC, 2011 March, 2011 − Rev. 0 1 Publication Order Number: NTMD5836NL/D NTMD5836NL MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) Parameter Drain−to−Source Voltage Gate−to−Source Voltage Continuous Drain Current RθJA (Notes 3 and 4) Power Dissipation RθJA (Notes 3 and 4) Continuous Drain Current RθJA (Notes 3 and 4) Power Dissipation RθJA (Notes 3 and 4) Pulsed Drain Current Operating Junction and Storage Temperature Source Current (Body Diode) Single Pulse Drain−to−Source Avalanche Energy (VDD = 40 V, VGS = 10 V, L = 0.1 mH) Lead Temperature for Soldering Purposes (1/8” from case for 10s) tp = 10 ms t v 10s Steady State TA = 25°C TA = 70°C TA = 25°C TA = 70°C TA = 25°C TA = 70°C TA = 25°C TA = 70°C IDM TJ, TSTG IS EAS IAS TL PD ID PD Symbol VDSS VGS ID Ch 1 40 $20 9.0 7.2 1.5 0.9 11 8.6 2.1 1.3 43 Ch 2 40 $20 5.7 4.6 1.5 0.9 6.5 4.6 1.9 1.2 26 A °C A mJ A °C W A W Unit V V A −55 to +150 10 76 39 260 7.0 22 21 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces) 4. Only selected channel is been powered 1W applied on channel 1: TJ = 1 W * 85°C/W + 25°C = 110°C THERMAL RESISTANCE RATINGS Parameter Junction−to−Ambient Steady State (Notes 5 and 7) Junction−to−Ambient – t v 10 s (Notes 5 and 7) Junction−to−Ambient Steady State (Notes 5 and 8) Junction−to−Ambient Steady State (Notes 6 and 7) Symbol RθJA RθJA RθJA RθJA 136 Ch 1 85 60 59 136 Ch 2 86 65 Unit °C/W 5. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces) 6. Surface−mounted on FR4 board using 0.155 in sq (100 mm2) pad size 7. Only selected channel is been powered 1W applied on channel 1: TJ = 1 W * 85°C/W + 25°C = 110°C 8. Both channels receive equivalent power dissipation 1 W applied on each channel: TJ = 2 W * 59°C/W + 25°C = 143°C http://onsemi.com 2 NTMD5836NL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage Drain−to−Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current V(BR)DSS V(BR)DSS / TJ IDSS VGS = 0 V, VDS = 40 V TJ = 25°C TJ = 125°C Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = $20 V VGS = 0 V, ID = 250 mA Ch 1 Ch 2 Ch 1 Ch 2 Ch 1 Ch 2 Ch 1 Ch 2 Ch 1 Ch 2 $100 nA 100 146 25 1.0 mV/ °C mA 40 V Symbol Test Condition Ch Min Typ Max Unit ON CHARACTERISTICS (Note 9) Gate Threshold Voltage VGS(TH) VGS(TH) / TJ RDS(on) VGS = 10 V, ID = 10 A VGS = 10 V, ID = 7 A VGS = 4.5 V, ID = 10 A VGS = 4.5 V, ID = 7 A Forward Transconductance gFS VDS = 15 V, ID = 10 A VDS = 15 V, ID = 7 A CHARGES, CAPACITANCES & GATE RESISTANCE Input Capacitance CISS COSS CRSS Ch 1 Ch 2 Output Capacitance VGS = 0 V, f = 1 MHz, VDS = 20 V Ch 1 Ch 2 Ch 1 Ch 2 9. Pulse Test: pulse width v 300 ms, duty cycle v 2% 10. Switching characteristics are independent of operating junction temperatures 2120 730 315 123 225 84 pF VGS = VDS, ID = 250 mA Ch 1 Ch 2 Ch 1 Ch 2 Ch 1 Ch 2 Ch 1 Ch 2 Ch 1 Ch 2 1.0 1.0 1.8 1.8 6.0 6.0 9.5 20.5 13 25.0 10.5 6.0 12 25 16 30.8 S mW mW 3.0 3.0 mV/°C V Negative Threshold Temperature Coefficient Drain−to−Source On Resistance Reverse Transfer Capacitance http://onsemi.com 3 NTMD5836NL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Ch Min Typ Max Unit CHARGES, CAPACITANCES & GATE RESISTANCE Total Gate Charge QG(TOT) VGS = 10V, VDS = 20V, ID = 10A VGS = 10 V, VDS = 20 V, ID = 7 A Ch 1 Ch 2 Ch 1 Ch 2 Threshold Gate Charge QG(TH) QGS QGD VGP RG Ch 1 Ch 2 Gate−to−Source Charge VGS = 4.5 V, VDS = 20 V, CH1: ID = 10 A, CH2: ID = 7 A Ch 1 Ch 2 Ch 1 Ch 2 Plateau Voltage Ch 1 Ch 2 Gate Resistance Ch 1 Ch 2 SWITCHING CHARACTERISTICS (Note 10) Turn−On Delay Time td(ON) tr td(OFF) tf VGS = 4.5 V, VDD = 20 V, CH1: ID = 10 A, CH2: ID = 7 A, RG = 2.5 W Ch 1 Ch 2 Rise Time Ch 1 Ch 2 Ch 1 Ch 2 Fall Time Ch 1 Ch 2 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD VGS = 0 V, CH1: ID = 10 A, CH2: ID =7A TJ = 25°C TJ = 125°C Ch 1 Ch 2 Ch 1 Ch 2 Ch 1 Ch 2 Charge Time Ta Tb QRR VGS = 0 V, dISD/dt = 100 A/ms, CH1: ID = 10 A, CH2: ID = 7 A Ch 1 Ch 2 Ch 1 Ch 2 Reverse Recovery Charge Ch 1 Ch 2 9. Pulse Test: pulse width v 300 ms, duty cycle v 2% 10. Switching characteristics are independent of operating junction temperatures 0.9 0.85 0.65 0.73 27 17 14 11 13 6.0 19 9.0 nC ns 1.2 1.2 V 16 11.5 22 14 26 15.5 8.5 3.5 ns 36 16 15 8.5 2.4 1.0 6.9 2.8 7.2 4.0 3.2 3.3 1.2 2.1 W V 23 11 50 nC Gate−to−Drain Charge Turn−Off Delay Time Reverse Recovery Time tRR Discharge Time http://onsemi.com 4 NTMD5836NL TYPICAL PERFORMANCE CURVES 70 60 ID, DRAIN CURRENT (A) 50 40 30 20 3.1 V 10 0 0 1 2 3 VGS = 2.5 V 4 5 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 70 60 ID, DRAIN CURRENT (A) 50 40 30 20 10 0 2 3 4 5 VGS, GATE−TO−SOURCE VOLTAGE (V) TJ = 125°C TJ = 25°C TJ = −55°C VDS ≥ 20 V 10V 6.5 V 8.5 V 4.5 V 5.5 V 3.9 V TJ = 25°C 3.5 V Figure 1. On−Region Characteristics − Channel 1 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.035 0.03 0.025 0.02 0.015 0.01 TJ = 25°C ID = 10 A RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.02 Figure 2. Transfer Characteristics − Channel 1 TJ = 25°C 0.015 VGS = 4.5 V VGS = 10 V 0.01 2 3 4 5 6 7 8 9 10 0.005 2 6 10 14 18 VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage − Channel 1 1.6 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 100000 ID = 10 A VGS = 4.5 V IDSS, LEAKAGE (nA) Figure 4. On−Resistance vs. Drain Current and Gate Voltage − Channel 1 VGS = 0 V 1.4 TJ = 150°C TJ = 125°C 1.2 10000 1 0.8 −50 −25 0 25 50 75 100 125 150 1000 10 20 30 40 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature − Channel 1 Figure 6. Drain−to−Source Leakage Current vs. Voltage − Channel 1 http://onsemi.com 5 NTMD5836NL TYPICAL PERFORMANCE CURVES 3000 TJ = 25°C VGS, GATE−TO−SOURCE (V) 2500 C, CAPACITANCE (pF) Ciss 2000 1500 1000 500 0 Crss 0 10 Coss 20 30 40 VGS = 0 V 8 6 4 2 0 10 QT VDS, DRAIN−TO−SOURCE (V) 40 1 150 QGS QGD VGS = 20 V ID = 10 A TJ = 25°C 0 5 10 15 20 25 30 35 DRAIN−TO−SOURCE VOLTAGE (V) QG, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation − Channel 1 Figure 8. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge − Channel 1 20 IS, SOURCE CURRENT (A) VGS = 0 V TJ = 25°C 1000 VDD = 20 V ID = 10 A VGS = 4.5 V t, TIME (ns) tr 100 15 10 td(off) tf td(on) 5 10 1 10 RG, GATE RESISTANCE (W) 100 0 0.4 0.5 0.6 0.7 0.8 0.9 VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance − Channel 1 100 EAS, SINGLE PULSE DRAIN−TO− SOURCE AVALANCHE ENERGY (mJ) 10 1 0.1 0.01 VGS = 20 V SINGLE PULSE TC = 25°C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 80 Figure 10. Diode Forward Voltage vs. Current − Channel 1 ID = 39 A 60 ID, DRAIN CURRENT (A) 1 ms 10 ms 100 ms 1 ms dc 40 20 0.001 0.1 100 0 25 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area − Channel 1 Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature − Channel 1 http://onsemi.com 6 NTMD5836NL TYPICAL PERFORMANCE CURVES 50 40 30 3.6 V 20 10 0 0 1 2 3 50 4.5 V 4V ID, DRAIN CURRENT (A) 40 30 20 10 0 5 2 3 4 5 VGS, GATE−TO−SOURCE VOLTAGE (V) 10V 8.5 V 6.5 V 5.5 V VDS ≥ 5 V ID, DRAIN CURRENT (A) TJ = 125°C TJ = 25°C TJ = −55°C VGS = 3 V TJ = 25°C 4 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics − Channel 2 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.05 TJ = 25°C ID = 7 A 0.04 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.03 Figure 2. Transfer Characteristics − Channel 2 TJ = 25°C VGS = 4.5 V 0.025 0.03 0.02 0.02 VGS = 10 V 0.01 2 3 4 5 6 7 8 9 VGS, GATE−TO−SOURCE VOLTAGE (V) 10 0.015 2 6 10 14 ID, DRAIN CURRENT (A) 18 Figure 3. On−Resistance vs. Gate−to−Source Voltage − Channel 2 1.6 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 1.4 1.2 1 0.8 0.6 −50 VGS = 4.5 V ID = 7 A IDSS, LEAKAGE (nA) 10000 100000 Figure 4. On−Resistance vs. Drain Current and Gate Voltage − Channel 2 VGS = 0 V TJ = 150°C 1000 TJ = 125°C −25 0 25 50 75 100 125 150 100 5 15 25 35 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature − Channel 2 Figure 6. Drain−to−Source Leakage Current vs. Voltage − Channel 2 http://onsemi.com 7 NTMD5836NL TYPICAL PERFORMANCE CURVES 1200 VGS, GATE−TO−SOURCE (V) 1000 C, CAPACITANCE (pF) 800 600 400 200 0 Coss Crss 0 10 20 30 40 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Ciss TJ = 25°C VGS = 0 V 10 QT 8 6 4 2 0 QGD VDS, DRAIN−TO−SOURCE (V) 1 150 QGS VDS = 20 V ID = 7 A TJ = 25°C 0 5 10 15 QG, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation − Channel 2 1000 IS, SOURCE CURRENT (A) VDD = 20 V ID = 7 A VGS = 4.5 V t, TIME (ns) 100 tr td(off) 12 10 8 6 4 2 0 1 10 RG, GATE RESISTANCE (W) 100 0.2 Figure 8. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge VGS = 0 V TJ = 25°C 10 td(on) tf 1 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance − Channel 2 EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) 100 10 1 0.1 0.01 0.001 0.1 VGS = 20 V SINGLE PULSE TC = 25°C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 1 ms 10 ms dc 100 ms 1 ms 20 Figure 10. Diode Forward Voltage vs. Current − Channel 2 ID = 21 A 15 ID, DRAIN CURRENT (A) 10 5 0 25 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area − Channel 2 Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 8 NTMD5836NL TYPICAL PERFORMANCE CURVES 100 D = 0.5 10 R(t) (°C/W) 0.2 0.1 0.05 0.02 0.01 0.1 SINGLE PULSE 0.01 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 1 t, PULSE TIME (s) Figure 13. Thermal Response http://onsemi.com 9 NTMD5836NL PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK −X− A 8 5 B 1 S 4 0.25 (0.010) M Y M −Y− G K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 C −Z− H D 0.25 (0.010) M SEATING PLANE N X 45 _ 0.10 (0.004) M J ZY S X S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 10 NTMD5836NL/D