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NTMD5838NL

NTMD5838NL

  • 厂商:

    ONSEMI(安森美)

  • 封装:

  • 描述:

    NTMD5838NL - Power MOSFET 30 V, 11.6 A, N−Channel, SO−8 Optimized Gate Charge - ON Semiconductor

  • 数据手册
  • 价格&库存
NTMD5838NL 数据手册
NTMD5838NL Power MOSFET Features 40 V, 8.9 A, 25 mW, Dual N−Channel SO−8 • • • • Low RDS(on) Low Capacitance Optimized Gate Charge These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) Parameter Drain−to−Source Voltage Gate−to−Source Voltage Continuous Drain Current RqJA (Note 1) Power Dissipation RqJA (Note 1) Continuous Drain Current RqJA (Note 1) Power Dissipation RqJA (Note 1) Pulsed Drain Current TA = 25°C Steady State TA = 70°C TA = 25°C TA = 70°C TA = 25°C t ≤10 s TA = 70°C TA = 25°C TA = 70°C tp = 10 ms IDM TJ, TSTG IS EAS IAS TL PD ID PD Symbol VDSS VGS ID Value 40 ±20 7.4 5.9 2.1 1.3 8.9 7.1 3.0 1.9 35 −55 to +150 7.0 20 21 260 A °C A mJ A °C A Y WW G W A S S W G G Unit V V A N−CHANNEL MOSFET D D http://onsemi.com V(BR)DSS 40 V RDS(ON) MAX 25 mW @ 10 V 30.8 mW @ 4.5 V ID MAX 8.9 A MARKING DIAGRAM/ PIN ASSIGNMENT D1 D1 D2 D2 8 SO−8 CASE 751 STYLE 11 D5838N AYWW G Operating Junction and Storage Temperature Source Current (Body Diode) Single Pulse Drain−to−Source Avalanche Energy (L = 0.1 mH) Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) 1 S1 G1 S2 G2 (Top View) = Assembly Location = Year = Work Week = Pb−Free Package Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. (Note: Microdot may be in either location) THERMAL RESISTANCE MAXIMUM RATINGS Parameter Junction−to−Ambient Steady State (Notes 1 & 3) Junction−to−Ambient − t ≤10 s (Note 1) Junction−to−Ambient Steady State (Note 2) Symbol RqJA RqJA RqJA Value 58 40 106 °C/W Unit ORDERING INFORMATION Device NTMD5838NLR2G Package Shipping† SO−8 2500/Tape & Reel (Pb−Free) 1. Surface−mounted on FR4 board using 1 sq−in pad (Cu area = 1.127 in sq [2 oz] including traces). 2. Surface−mounted on FR4 board using 0.155 in sq (100mm2) pad size. 3. Both channels receive equivalent power dissipation 1 W applied on each channel: TJ = 2 W * 58°C/W + 25°C = 141°C †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2011 April, 2011 − Rev. 0 1 Publication Order Number: NTMD5838NL/D NTMD5838NL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage Drain−to−Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current V(BR)DSS V(BR)DSS/ TJ IDSS IGSS VGS(TH) VGS(TH)/TJ RDS(on) gFS CISS COSS CRSS QG(TOT) QG(TH) QGS QGD VGP RG td(ON) tr td(OFF) tf VSD tRR ta tb QRR VGS = 0 V, dIS/dt = 100 A/ms, IS = 7 A TJ = 25°C TJ = 125°C VGS = 4.5 V, VDS = 20 V, ID = 7 A, RG = 2.5 W VGS = 4.5 V, VDS = 20 V; ID = 7 A VGS = 10 V, VDS = 20 V; ID = 7 A VGS = 0 V, f = 1 MHz, VDS = 20 V VGS = 10 V, ID = 7 A VGS = 4.5 V, ID = 7 A Forward Transconductance VDS = 15 V, ID = 7 A CHARGES, CAPACITANCES & GATE RESISTANCE Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge 785 123 90 17 8.6 Threshold Gate Charge Gate−to−Source Charge Gate−to−Drain Charge Plateau Voltage Gate Resistance SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VGS = 0 V, IS = 7 A 0.84 0.7 17 11 6.0 10 nC ns 1.2 V 11 23 17 4.0 ns 0.8 2.8 4.0 3.2 1.8 V W 11 nC pF VGS = 0 V, VDS = 40 V TJ = 25 °C TJ = 125°C VGS = 0 V, ID = 250 mA 40 32 1.0 100 ±100 V mV/°C mA nA Symbol Test Condition Min Typ Max Unit Gate−to−Source Leakage Current ON CHARACTERISTICS (Note 4) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain−to−Source On Resistance VDS = 0 V, VGS = ±20 V VGS = VDS, ID = 250 mA 1.0 1.8 6.0 20.5 25.0 4.0 3.0 V mV/°C 25 30.8 mW S Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge 4. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 5. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 NTMD5838NL TYPICAL PERFORMANCE CURVES 50 10 V ID, DRAIN CURRENT (A) 40 30 20 10 3V 0 0 1 2 3 4 5 0 2 3 5.5 V 7.5 V 4V 4.4 V TJ = 25°C ID, DRAIN CURRENT (A) 50 VDS ≥ 5 V 40 30 20 10 3.6 V TJ = 125°C TJ = 25°C TJ = −55°C 4 5 VDS, DRAIN−TO−SOURCE VOLTAGE (V) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics 0.06 0.05 0.04 0.03 0.02 0.01 TJ = 25°C ID = 7 A RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.035 Figure 2. Transfer Characteristics TJ = 25°C 0.025 VGS = 4.5 V VGS = 10 V 0.015 2 3 4 5 6 7 8 9 10 0.005 2 6 10 14 18 VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage 1.6 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 1.4 1.2 1 0.8 0.6 −50 VGS = 4.5 V ID = 7 A IDSS, LEAKAGE (nA) 10000 100000 Figure 4. On−Resistance vs. Drain Current and Gate Voltage VGS = 0 V TJ = 150°C 1000 TJ = 125°C −25 0 25 50 75 100 125 150 100 5 15 25 35 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 3 NTMD5838NL TYPICAL PERFORMANCE CURVES 1200 VGS, GATE−TO−SOURCE (V) 1000 C, CAPACITANCE (pF) 800 600 400 200 0 Crss 0 10 20 30 40 0 0 1 2 3 4 5 6 7 Coss Ciss TJ = 25°C VGS = 0 V 6 VDS, DRAIN−TO−SOURCE (V) 10 1 150 QT 4 QGS QGD 2 VGS = 10 V ID = 7 A TJ = 25°C 8 9 QG, TOTAL GATE CHARGE (nC) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 7. Capacitance Variation Figure 8. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge 1000 IS, SOURCE CURRENT (A) VDS = 20 V ID = 7 A VGS = 4.5 V 100 t, TIME (ns) tr 10 td(off) tf td(on) 12 10 8 6 4 2 0 VGS = 0 V TJ = 25°C 1 1 10 RG, GATE RESISTANCE (W) 100 0.2 0.4 0.6 0.8 VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance 100 EAS, SINGLE PULSE DRAIN−TO− SOURCE AVALANCHE ENERGY (mJ) 10 1 0.1 0.01 0.001 VGS = 10 V SINGLE PULSE TC = 25°C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 1 ms 10 ms 100 ms 10 ms dc 20 Figure 10. Diode Forward Voltage vs. Current ID = 20 A 15 ID, DRAIN CURRENT (A) 10 5 100 0 25 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 4 NTMD5838NL TYPICAL PERFORMANCE CURVES 100 D = 0.5 10 R(t) (°C/W) 0.2 0.1 0.05 0.02 0.01 0.1 SINGLE PULSE 0.00001 0.0001 0.001 0.01 t, TIME (s) 0.1 1 10 100 1000 1 0.01 0.000001 Figure 13. Thermal Response http://onsemi.com 5 NTMD5838NL PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK −X− A 8 5 B 1 S 4 0.25 (0.010) M Y M −Y− G K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 C −Z− H D 0.25 (0.010) M SEATING PLANE N X 45 _ 0.10 (0.004) M J ZY S X S SOLDERING FOOTPRINT* 1.52 0.060 STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 6 NTMD5838NL/D
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