NTMFS4707N
Power MOSFET
30 V, 17 A, Single N−Channel,
SOIC−8 Flat Lead
Features
•
•
•
•
•
Fast Switching Times
Low Gate Charge
Low RDS(on)
Low Inductance SOIC−8 Package
These are Pb−Free Devices
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V(BR)DSS
RDS(on) Typ
ID Max
10 mW @ 10 V
30 V
Applications
17 A
13.5 mW @ 4.5 V
• Notebooks, Graphics Cards
• DC−DC Converters
• Synchronous Rectification
N−Channel
D
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
30
V
Gate−to−Source Voltage
VGS
±20
V
ID
10.2
A
Continuous Drain Current
(Note 1)
Power Dissipation (Note 1)
Steady
State
TA = 25°C
TA = 85°C
7.4
t ≤ 10 s
TA = 25°C
17
Steady
State
PD
Power Dissipation (Note 2)
Steady
State
Pulsed Drain Current
MARKING DIAGRAM &
PIN ASSIGNMENT
W
2.3
D
6.25
ID
TA = 25°C
TA = 85°C
TA = 25°C
tp ≤ 10 ms
Operating Junction and Storage Temperature
Single Pulse Drain−to−Source Avalanche Energy
(VDD = 25 V, VGS = 10 V, IPK = 7.0 A,
L = 10 mH, RG = 25 W)
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
A
6.9
4.9
PD
1.0
W
IDM
51
A
TJ,
TSTG
−55 to
150
°C
Source Current (Body Diode)
IS
6.25
A
EAS
245
mJ
TL
260
°C
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Junction−to−Ambient – Steady State (Note 1)
RqJA
55
°C/W
Junction−to−Ambient – t ≤ 10 s (Note 1)
RqJA
20
Junction−to−Ambient – Steady State (Note 2)
RqJA
122.5
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 in sq pad size
(Cu area = 1.127 in sq [1 oz] including traces).
2. Surface−mounted on FR4 board using the minimum recommended pad size
(Cu area = 0.412 in sq).
© Semiconductor Components Industries, LLC, 2012
May, 2012 − Rev. 4
S
TA = 25°C
t ≤ 10 s
Continuous Drain Current
(Note 2)
G
1
S
S
S
G
1
SOIC−8 FLAT LEAD
CASE 488AA
STYLE 1
4707N
A
Y
W
ZZ
D
4707N
AYWZZ
D
D
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Lot Traceability
ORDERING INFORMATION
Device
Package
Shipping†
NTMFS4707NT1G SOIC−8 FL 1500 / Tape & Reel
(Pb−Free)
NTMFS4707NT3G SOIC−8 FL 5000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NTMFS4707N/D
NTMFS4707N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Parameter
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
6.5
VGS = 0 V, VDS = 24 V
mV/°C
TJ = 25°C
1.0
TJ = 125°C
50
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
±100
mA
nA
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
Negative Threshold
Temperature Coefficient
Drain−to−Source On Resistance
VGS(TH)/TJ
2.5
5.0
RDS(on)
Forward Transconductance
1.0
gFS
V
mV/°C
VGS = 10 V, ID = 10 A
10
13
mW
VGS = 4.5 V, ID = 8.0 A
13.5
17
VDS = 15 V, ID = 10 A
20
S
735
pF
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
80
Total Gate Charge
QG(TOT)
7.5
Threshold Gate Charge
QG(TH)
1.1
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
3.6
RG
2.4
W
td(on)
6.0
ns
tr
5.0
Gate Resistance
VGS = 0 V, f = 1.0 MHz, VDS = 24 V
VGS = 4.5 V, VDS = 15 V; ID = 10 A
295
15
nC
2.0
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(off)
VGS = 10 V, VDD = 15 V, ID = 1.0 A,
RG = 3.0 W
tf
19
11
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
VSD
Reverse Recovery Time
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V, IS = 6.25 A
TJ = 25°C
0.79
TJ = 125°C
0.59
26
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 6.25 A
QRR
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2
V
ns
14
12
19
3. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
1.0
nC
NTMFS4707N
TYPICAL CHARACTERIZATIONS
36
TJ = 25°C
VGS = 10 V
4.5 V
25
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
30
4V
20
3.8 V
3.4 V
15
3V
2.8 V
10
2.6 V
5
VDS ≥ 10 V
30
24
18
TJ = 125°C
12
TJ = 25°C
TJ = −55°C
6
2.4 V
0
0
1
2
3
0
5
4
0
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.020
VGS = 10 V
TJ = 125°C
0.015
TJ = 25°C
0.010
TJ = −55°C
0.005
0
0
5
10
20
15
ID, DRAIN CURRENT (AMPS)
25
30
0.018
VGS = 4.5 V
VGS = 10 V
0.010
0.006
0.002
0
12
16
20
24
ID, DRAIN CURRENT (AMPS)
100000
VGS = 0 V
IDSS, LEAKAGE (nA)
ID = 17 A
VGS = 10 V
1.6
8
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
2.0
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
TJ = 25°C
0.014
Figure 3. On−Resistance vs. Drain Current and
Temperature
1.8
5
Figure 2. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
Figure 1. On−Region Characteristics
1
2
3
4
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
10000
1.4
1.2
1.0
TJ = 150°C
1000
TJ = 125°C
0.8
0.6
−50
−25
0
25
50
75
100
125
150
100
0
TJ, JUNCTION TEMPERATURE (°C)
5
10
15
20
25
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
30
NTMFS4707N
1600
VDS = 0 V
C, CAPACITANCE (pF)
1400
VGS, GATE−TO−SOURCE VOLTAGE (V)
TYPICAL CHARACTERIZATIONS
TJ = 25°C
VGS = 0 V
CISS
1200
CRSS
1000
CISS
800
COSS
600
400
CRSS
200
0
10
5
0
VGS
5
10
15
20
25
5
VGS = 4.5 V
4
QGS
2
1
0
ID = 10 A
TJ = 25°C
0
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
100
18
IS, SOURCE CURRENT (AMPS)
t, TIME (ns)
10
tr
tf
1
1
10
RG, GATE RESISTANCE (OHMS)
9
6
3
0
10 ms
100 ms
10
1 ms
10 ms
1
0.1
0.01
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
1
dc
10
0.4
0.2
0.6
0.8
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
1
Figure 10. Diode Forward Voltage vs. Current
100
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
ID, DRAIN CURRENT (AMPS)
100
VGS = 20 V
SINGLE PULSE
TC = 25°C
10
12
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
1000
4
6
8
QG, TOTAL GATE CHARGE (nC)
VGS = 0 V
TJ = 25°C
15
0
100
2
Figure 8. Gate−To−Source and
Drain−To−Source Voltage vs. Total Charge
Figure 7. Capacitance Variation
td(off)
td(on)
QGD
3
VDS
VDD = 15 V
ID = 1 A
VGS = 4.5 V
QT
350
300
ID = 7 A
250
200
150
100
50
0
25
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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4
150
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE N
1
DATE 25 JUN 2018
SCALE 2:1
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
0.20 C
D
A
2
B
D1
2X
0.20 C
4X
E1
2
q
E
c
1
2
3
A1
4
TOP VIEW
C
DETAIL A
0.10 C
SEATING
PLANE
A
0.10 C
SIDE VIEW
MILLIMETERS
MIN
NOM
MAX
0.90
1.00
1.10
0.00
−−−
0.05
0.33
0.41
0.51
0.23
0.28
0.33
5.00
5.15
5.30
4.70
4.90
5.10
3.80
4.00
4.20
6.00
6.30
6.15
5.70
5.90
6.10
3.45
3.65
3.85
1.27 BSC
0.51
0.575
0.71
1.20
1.35
1.50
0.51
0.575
0.71
0.125 REF
3.00
3.40
3.80
0_
−−−
12 _
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
q
GENERIC
MARKING DIAGRAM*
DETAIL A
1
0.10
b
C A B
0.05
c
8X
XXXXXX
AYWZZ
e/2
e
L
1
4
K
RECOMMENDED
SOLDERING FOOTPRINT*
E2
PIN 5
(EXPOSED PAD)
L1
M
2X
0.495
4.560
2X
1.530
G
D2
2X
BOTTOM VIEW
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
0.475
3.200
4.530
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
1.330
STYLE 2:
2X
PIN 1. ANODE
0.905
2. ANODE
3. ANODE
4. NO CONNECT
0.965
5. CATHODE
1
4X
1.000
4X 0.750
1.270
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON14036D
DFN5 5x6, 1.27P (SO−8FL)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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