NUP2114UPXV5T1G

NUP2114 Series, SNUP2114 ESD Protection Diode Low Capacitance ESD Protection for High Speed Data The NUP2114 surge protection is designed to protect high speed data lines from ESD. Ultra−low capacitance and high level of ESD protection makes this device well suited for use in USB 2.0 applications. www.onsemi.com Features • • • • • • • • • Low Capacitance 0.8 pF Low Clamping Voltage Stand Off Voltage: 5 V Low Leakage ESD Rating of Class 3B (Exceeding 8 kV) per Human Body model and Class C (Exceeding 400 V) per Machine Model Protection for the Following IEC Standards: IEC 61000−4−2 Level 4 ESD Protection UL Flammability Rating of 94 V−0 S Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Typical Applications • • • • • • • VP I/O I/O VN MARKING DIAGRAMS 1 High Speed Communication Line Protection USB 2.0 High Speed Data Line and Power Line Protection Monitors and Flat Panel Displays MP3 Gigabit Ethernet Notebook Computers Digital Video Interface (DVI) and HDMI TSOP−6 CASE 318G SOT−553 CASE 463B P2M MG G P2MG G 1 SOT−553 TSOP−6 P2, P2M = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit VP 1 Operating Junction Temperature Range TJ −40 to +125 °C VN 2 Storage Temperature Range Tstg −55 to +150 °C Lead Solder Temperature − Maximum (10 Seconds) TL 260 °C Human Body Model (HBM) Machine Model (MM) IEC 61000−4−2 Contact IEC61000−4−2 Air ESD 16000 400 13000 15000 V 5 I/O NC 3 4 I/O SOT−553 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. See Application Note AND8308/D for further description of survivability specs. I/O 1 6 I/O VN 2 5 VP NC 3 4 NC TSOP−6 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. © Semiconductor Components Industries, LLC, 2012 October, 2017 − Rev. 3 1 Publication Order Number: NUP2114/D NUP2114 Series, SNUP2114 ELECTRICAL CHARACTERISTICS I (TA = 25°C unless otherwise noted) Symbol IF Parameter IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM IR VBR Working Peak Reverse Voltage Test Current IF Forward Current VF Forward Voltage @ IF Ppk Peak Power Dissipation V IR VF IT Breakdown Voltage @ IT IT C VC VBR VRWM Maximum Reverse Leakage Current @ VRWM IPP Max. Capacitance @ VR = 0 and f = 1.0 MHz Uni−Directional *See Application Note AND8308/D for detailed explanations of datasheet parameters. ELECTRICAL CHARACTERISTICS (TJ=25°C unless otherwise specified) Parameter Reverse Working Voltage Breakdown Voltage Symbol VRWM VBR Conditions Min Typ (Note 1) IT = 1 mA, (Note 2) 5.5 Max Unit 5.0 V 7.5 V Reverse Leakage Current IR VRWM = 5 V 0.01 Clamping Voltage VC IPP = 5 A (Note 3) 9.0 V Clamping Voltage VC IPP = 8 A (Note 3) 10 V Maximum Peak Pulse Current IPP 8x20 ms Waveform Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins and GND Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins Clamping Voltage VC @ IPP = 1 A (Note 4) Clamping Voltage VC Per IEC 61000−4−2 (Note 5) 0.8 1.0 mA 12 A 1.0 pF 0.5 pF 12 V Figures 1 and 2 V 1. Surge protection devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater than the DC or continuous peak operating voltage level. 2. VBR is measured at pulse test current IT. 3. Nonrepetitive current pulse (Pin 5 to Pin 2) 4. Surge current waveform per Figure 5. 5. Typical waveform. For test procedure see Figures 3 and 4 and Application Note AND8307/D. 6. Include S-prefix devices where applicable. Figure 1. ESD Clamping Voltage Screenshot Positive 8 kV Contact per IEC61000−4−2 Figure 2. ESD Clamping Voltage Screenshot Negative 8 kV Contact per IEC61000−4−2 www.onsemi.com 2 NUP2114 Series, SNUP2114 IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 3. IEC61000−4−2 Spec Device ESD Gun Under Oscilloscope Test 50 W 50 W Cable Figure 4. Diagram of ESD Test Setup The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger % OF PEAK PULSE CURRENT 100 PEAK VALUE IRSM @ 8 ms tr 90 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 0 20 40 t, TIME (ms) 60 Figure 5. 8 x 20 ms Pulse Waveform www.onsemi.com 3 80 NUP2114 Series, SNUP2114 Figure 6. 500 MHz Data Pattern ORDERING INFORMATION Marking Package Shipping† NUP2114UPXV5T1G P2 SOT−553 (Pb−Free) 4,000 / Tape & Reel NUP2114UCMR6T1G P2M TSOP−6 (Pb−Free) 3,000 / Tape & Reel SNUP2114UCMR6T1G* P2M TSOP−6 (Pb−Free) 3,000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *S Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable. www.onsemi.com 4 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSOP−6 CASE 318G−02 ISSUE V 1 SCALE 2:1 D H ÉÉ ÉÉ 6 E1 1 NOTE 5 5 2 L2 4 GAUGE PLANE E 3 L b SEATING PLANE C DETAIL Z e DIM A A1 b c D E E1 e L L2 M c A 0.05 M DATE 12 JUN 2012 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H. 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE. A1 DETAIL Z MIN 0.90 0.01 0.25 0.10 2.90 2.50 1.30 0.85 0.20 0° MILLIMETERS NOM MAX 1.00 1.10 0.06 0.10 0.38 0.50 0.18 0.26 3.00 3.10 2.75 3.00 1.50 1.70 0.95 1.05 0.40 0.60 0.25 BSC 10° − STYLE 1: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN STYLE 2: PIN 1. EMITTER 2 2. BASE 1 3. COLLECTOR 1 4. EMITTER 1 5. BASE 2 6. COLLECTOR 2 STYLE 3: PIN 1. ENABLE 2. N/C 3. R BOOST 4. Vz 5. V in 6. V out STYLE 4: PIN 1. N/C 2. V in 3. NOT USED 4. GROUND 5. ENABLE 6. LOAD STYLE 5: PIN 1. EMITTER 2 2. BASE 2 3. COLLECTOR 1 4. EMITTER 1 5. BASE 1 6. COLLECTOR 2 STYLE 6: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. EMITTER 5. COLLECTOR 6. COLLECTOR STYLE 7: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. N/C 5. COLLECTOR 6. EMITTER STYLE 8: PIN 1. Vbus 2. D(in) 3. D(in)+ 4. D(out)+ 5. D(out) 6. GND STYLE 9: PIN 1. LOW VOLTAGE GATE 2. DRAIN 3. SOURCE 4. DRAIN 5. DRAIN 6. HIGH VOLTAGE GATE STYLE 10: PIN 1. D(OUT)+ 2. GND 3. D(OUT)− 4. D(IN)− 5. VBUS 6. D(IN)+ STYLE 11: PIN 1. SOURCE 1 2. DRAIN 2 3. DRAIN 2 4. SOURCE 2 5. GATE 1 6. DRAIN 1/GATE 2 STYLE 12: PIN 1. I/O 2. GROUND 3. I/O 4. I/O 5. VCC 6. I/O STYLE 13: PIN 1. GATE 1 2. SOURCE 2 3. GATE 2 4. DRAIN 2 5. SOURCE 1 6. DRAIN 1 STYLE 14: PIN 1. ANODE 2. SOURCE 3. GATE 4. CATHODE/DRAIN 5. CATHODE/DRAIN 6. CATHODE/DRAIN STYLE 15: PIN 1. ANODE 2. SOURCE 3. GATE 4. DRAIN 5. N/C 6. CATHODE STYLE 16: PIN 1. ANODE/CATHODE 2. BASE 3. EMITTER 4. COLLECTOR 5. ANODE 6. CATHODE STYLE 17: PIN 1. EMITTER 2. BASE 3. ANODE/CATHODE 4. ANODE 5. CATHODE 6. COLLECTOR GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 6X 0.60 XXXAYWG G 1 6X 3.20 XXX A Y W G 0.95 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98ASB14888C TSOP−6 1 IC 0.95 XXX MG G = Specific Device Code =Assembly Location = Year = Work Week = Pb−Free Package STANDARD XXX = Specific Device Code M = Date Code G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOT−553, 5 LEAD CASE 463B ISSUE C SCALE 4:1 D −X− 5 A 4 1 2 3 b e NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. L E −Y− DATE 20 MAR 2013 HE DIM A b c D E e L HE c 5 PL 0.08 (0.003) M X Y RECOMMENDED SOLDERING FOOTPRINT* INCHES NOM 0.022 0.009 0.005 0.063 0.047 0.020 BSC 0.004 0.008 0.061 0.063 MIN 0.020 0.007 0.003 0.061 0.045 MAX 0.024 0.011 0.007 0.065 0.049 0.012 0.065 GENERIC MARKING DIAGRAM* 0.3 0.0118 XXMG G 0.45 0.0177 XX = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) 1.0 0.0394 1.35 0.0531 MILLIMETERS NOM MAX 0.55 0.60 0.22 0.27 0.13 0.18 1.60 1.65 1.20 1.25 0.50 BSC 0.10 0.20 0.30 1.55 1.60 1.65 MIN 0.50 0.17 0.08 1.55 1.15 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 0.5 0.5 0.0197 0.0197 SCALE 20:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLE 1: PIN 1. BASE 2. EMITTER 3. BASE 4. COLLECTOR 5. COLLECTOR STYLE 2: PIN 1. CATHODE 2. COMMON ANODE 3. CATHODE 2 4. CATHODE 3 5. CATHODE 4 STYLE 3: PIN 1. ANODE 1 2. N/C 3. ANODE 2 4. CATHODE 2 5. CATHODE 1 STYLE 4: PIN 1. SOURCE 1 2. DRAIN 1/2 3. SOURCE 1 4. GATE 1 5. GATE 2 STYLE 6: PIN 1. EMITTER 2 2. BASE 2 3. EMITTER 1 4. COLLECTOR 1 5. COLLECTOR 2/BASE 1 STYLE 7: PIN 1. BASE 2. EMITTER 3. BASE 4. COLLECTOR 5. COLLECTOR STYLE 8: PIN 1. CATHODE 2. COLLECTOR 3. N/C 4. BASE 5. EMITTER STYLE 9: PIN 1. ANODE 2. CATHODE 3. ANODE 4. ANODE 5. ANODE DOCUMENT NUMBER: STATUS: 98AON11127D ON SEMICONDUCTOR STANDARD 1 © Semiconductor Components Industries, LLC, 2002 January, 2002 − Rev. 01O NEW STANDARD: © Semiconductor Components Industries, LLC, 2002 October, DESCRIPTION: 2002 − Rev. 0 SOT−553, 5 LEAD http://onsemi.com 1 STYLE 5: PIN 1. ANODE 2. EMITTER 3. BASE 4. COLLECTOR 5. CATHODE Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled exceptCase when stamped Outline Number: 463B “CONTROLLED COPY” in red. Case Outline Number: PAGE 1 OFXXX 2 DOCUMENT NUMBER: 98AON11127D PAGE 2 OF 2 ISSUE REVISION DATE A ADDED STYLES 3−9. REQ. BY D. BARLOW 11 NOV 2003 B ADDED NOMINAL VALUES AND UPDATED GENERIC MARKING DIAGRAM. REQ. BY HONG XIAO 27 MAY 2005 C UPDATED DIMENSIONS D, E, AND HE. REQ. BY J. LETTERMAN. 20 MAR 2013 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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