NVB6410ANT4G

NTB6410AN, NTP6410AN, NVB6410AN MOSFET – Power, N-Channel 100 V, 76 A, 13 mW www.onsemi.com Features • • • • • Low RDS(on) High Current Capability 100% Avalanche Tested NVB Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant V(BR)DSS 100 V D Symbol Value Unit Drain−to−Source Voltage VDSS 100 V Gate−to−Source Voltage − Continuous VGS $20 V ID 76 A Continuous Drain Current RqJC Steady State Power Dissipation RqJC Steady State TC = 25°C TC = 100°C W IDM 305 A TJ, Tstg −55 to +175 °C IS 76 A Single Pulse Drain−to−Source Avalanche Energy (VDD = 50 Vdc, VGS = 10 Vdc, IL(pk) = 57.7 A, L = 0.3 mH, RG = 25 W) EAS 500 mJ Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 Seconds TL 260 °C Symbol Max Unit Junction−to−Case (Drain) Steady State RqJC 0.8 °C/W Junction−to−Ambient (Note 1) RqJA 32 Operating Junction and Storage Temperature Range Source Current (Body Diode) S 4 4 188 tp = 10 ms G 54 PD Pulsed Drain Current TC = 25°C 1 2 3 1 2 D2PAK CASE 418B STYLE 2 TO−220AB CASE 221A STYLE 5 3 4 Drain MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain THERMAL RESISTANCE RATINGS Parameter 76 A 13 mW @ 10 V N−Channel MAXIMUM RATINGS (TJ = 25°C Unless otherwise specified) Parameter ID MAX (Note 1) RDS(ON) MAX Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Surface mounted on FR4 board using 1 sq in pad size, (Cu Area 1.127 sq in [2 oz] including traces). NTB 6410ANG AYWW NTP 6410ANG AYWW 1 Gate 3 Source 2 Drain 1 Gate 2 Drain 3 Source 6410AN = Specific Device Code G = Pb−Free Device A = Assembly Location Y = Year WW = Work Week ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2015 May, 2019 − Rev. 2 1 Publication Order Number: NTB6410AN/D NTB6410AN, NTP6410AN, NVB6410AN ELECTRICAL CHARACTERISTICS (TJ = 25°C Unless otherwise specified) Characteristics Symbol Test Condition Min V(BR)DSS VGS = 0 V, ID = 250 mA 100 Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage Drain−to−Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate−to−Source Leakage Current V(BR)DSS/TJ IDSS V 94 VGS = 0 V, VDS = 100 V mV/°C TJ = 25°C 1.0 TJ = 150°C 100 IGSS VDS = 0 V, VGS = $20 V VGS(th) VGS = VDS, ID = 250 mA $100 mA nA ON CHARACTERISTICS (Note 2) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain−to−Source On−Resistance VGS(th)/TJ 4.0 9.0 RDS(on) Forward Transconductance 2.0 gFS V mV/°C VGS = 10 V, ID = 76 A 11 13 mW VGS = 10 V, ID = 20 A 10 12 VDS = 5 V, ID = 20 A 40 S 4500 pF CHARGES, CAPACITANCES & GATE RESISTANCE Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss 250 Total Gate Charge QG(TOT) 120 Threshold Gate Charge QG(TH) VDS = 25 V, VGS = 0 V, f = 1 MHz 650 nC 5.2 VGS = 10 V, VDS = 80 V, ID = 76 A Gate−to−Source Charge QGS 20 Gate−to−Drain Charge QGD Plateau Voltage VGP 5.1 V Gate Resistance RG 2.4 W 17 ns 57 SWITCHING CHARACTERISTICS, VGS = 10 V (Note 3) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(on) tr td(off) VGS = 10 V, VDD = 80 V, ID = 76 A, RG = 6.2 W tf 170 120 190 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD Reverse Recovery Time trr Charge Time ta Discharge Time Reverse Recovery Charge IS = 76 A TJ = 25°C 1.0 TJ = 125°C 0.9 93 VGS = 0 V, IS = 76 A, dISD/dt = 100 A/ms tb QRR www.onsemi.com 2 V ns 69 24 300 2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 3. Switching characteristics are independent of operating junction temperatures. 1.3 nC NTB6410AN, NTP6410AN, NVB6410AN TJ = 25°C ID, DRAIN CURRENT (A) 140 160 7.0 V 10 V 120 6.0 V 100 80 60 5.4 V 40 5.0 V 0 1 2 3 4 100 80 60 3 4 5 6 7 8 Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics ID = 76 A TJ = 25°C 5 6 7 8 9 10 VGS, GATE−TO−SOURCE VOLTAGE (V) 0.030 IDSS, LEAKAGE (nA) 1.5 1 0 TJ = 125°C 0.020 0.015 TJ = 25°C 0.010 TJ = −55°C 0.005 0.000 10 25 50 75 100 125 150 20 30 40 50 60 70 80 ID, DRAIN CURRENT (A) 100000 2 TJ = 175°C Figure 4. On−Region versus Drain Current and Gate Voltage VGS = 10 V ID = 76 A −25 VGS = 10 V 0.025 Figure 3. On−Region versus Gate Voltage 0.5 −50 2 VGS, GATE−TO−SOURCE VOLTAGE (V) 0.015 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) TJ = −55°C VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0.025 2.5 TJ = 25°C TJ = 125°C 40 0 5 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) VGS = 4.4 V 0.035 0.005 120 20 20 0 VDS w 10 V 140 6.5 V ID, DRAIN CURRENT (A) 160 175 VGS = 0 V TJ = 150°C 10000 TJ = 125°C 1000 100 10 TJ, JUNCTION TEMPERTURE (°C) 20 30 40 50 60 70 80 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature 90 Figure 6. Drian−to−Source Leakage Current versus Voltage www.onsemi.com 3 10 TJ = 25°C VGS = 0 V C, CAPACITANCE (pF) 7000 6000 5000 Ciss 4000 3000 2000 1000 0 Coss Crss 0 10 20 30 40 50 60 70 80 90 10 100 8 VDS 6 2 0 VDS = 80 V ID = 76 A TJ = 25°C 0 20 40 60 80 100 20 0 120 Qg, TOTAL GATE CHARGE (nC) Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge IS, SOURCE CURRENT (A) t, TIME (ns) 100 60 40 80 tf tr Qgd 4 Figure 7. Capacitance Variation VDS = 80 V ID = 76 A VGS = 10 V 80 VGS Qgs VDS, DRAIN−TO−SOURCE VOLTAGE (V) 1000 100 QT VDS, DRAIN−TO−SOURCE VOLTAGE (V) 8000 VGS, GATE−TO−SOURCE VOLTAGE (V) NTB6410AN, NTP6410AN, NVB6410AN td(on) td(off) 10 TJ = 25°C VGS = 0 V 70 60 50 40 30 20 10 1 1 10 100 0 0.4 0.5 0.6 0.7 0.8 0.9 1.0 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current 1.1 500 1000 10 ms 100 100 ms 1 ms 10 10 ms dc 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 VGS = 10 V SINGLE PULSE TC = 25°C 10 100 VDS, DRAIN−TO−SOURCE VOLTAGE (V) AVALANCHE ENERGY (mJ) ID, DRAIN CURRENT (A) ID = 57.7 A 1000 400 300 200 100 0 25 50 75 100 125 150 175 TJ, STARTING JUNCTION TEMPERATURE Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature Figure 11. Maximum Rated Forward Biased Safe Opeating Area www.onsemi.com 4 NTB6410AN, NTP6410AN, NVB6410AN 1 D = 0.5 R(t) (°C/W) 0.2 0.1 0.1 0.05 0.02 0.01 0.01 0.001 0.000001 SINGLE PULSE 0.00001 0.0001 0.001 0.01 0.1 t, PULSE TIME (s) 1.0 10 100 1000 Figure 13. Thermal Response ORDERING INFORMATION Package Shipping† NTB6410ANG D2PAK (Pb−Free) 50 Units / Rail NTB6410ANT4G D2PAK (Pb−Free) 800 / Tape & Reel NTP6410ANG TO−220 (Pb−Free) 50 Units / Rail NVB6410ANT4G D2PAK (Pb−Free) 800 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TO−220 CASE 221A ISSUE AK DATE 13 JAN 2022 SCALE 1:1 STYLE 1: PIN 1. 2. 3. 4. BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. BASE EMITTER COLLECTOR EMITTER STYLE 3: PIN 1. 2. 3. 4. CATHODE ANODE GATE ANODE STYLE 4: PIN 1. 2. 3. 4. MAIN TERMINAL 1 MAIN TERMINAL 2 GATE MAIN TERMINAL 2 STYLE 5: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN STYLE 6: PIN 1. 2. 3. 4. ANODE CATHODE ANODE CATHODE STYLE 7: PIN 1. 2. 3. 4. CATHODE ANODE CATHODE ANODE STYLE 8: PIN 1. 2. 3. 4. CATHODE ANODE EXTERNAL TRIP/DELAY ANODE STYLE 9: PIN 1. 2. 3. 4. GATE COLLECTOR EMITTER COLLECTOR STYLE 10: PIN 1. 2. 3. 4. GATE SOURCE DRAIN SOURCE STYLE 11: PIN 1. 2. 3. 4. DRAIN SOURCE GATE SOURCE STYLE 12: PIN 1. 2. 3. 4. MAIN TERMINAL 1 MAIN TERMINAL 2 GATE NOT CONNECTED DOCUMENT NUMBER: DESCRIPTION: 98ASB42148B TO−220 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS D2PAK 3 CASE 418B−04 ISSUE L DATE 17 FEB 2015 SCALE 1:1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 418B−01 THRU 418B−03 OBSOLETE, NEW STANDARD 418B−04. C E −B− V W 4 1 2 A S 3 −T− SEATING PLANE K W J G D DIM A B C D E F G H J K L M N P R S V H 3 PL 0.13 (0.005) M T B M VARIABLE CONFIGURATION ZONE N R P L M STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR L M F F F VIEW W−W 1 VIEW W−W 2 VIEW W−W 3 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 7.87 8.89 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 1.32 1.83 7.11 8.13 5.00 REF 2.00 REF 0.99 REF 14.60 15.88 1.14 1.40 U L M INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.310 0.350 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.052 0.072 0.280 0.320 0.197 REF 0.079 REF 0.039 REF 0.575 0.625 0.045 0.055 STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 5: STYLE 6: PIN 1. CATHODE PIN 1. NO CONNECT 2. ANODE 2. CATHODE 3. CATHODE 3. ANODE 4. ANODE 4. CATHODE MARKING INFORMATION AND FOOTPRINT ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42761B D2PAK 3 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com D2PAK 3 CASE 418B−04 ISSUE L DATE 17 FEB 2015 GENERIC MARKING DIAGRAM* xx xxxxxxxxx AWLYWWG xxxxxxxxG AYWW AYWW xxxxxxxxG AKA IC Standard Rectifier xx A WL Y WW G AKA = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package = Polarity Indicator *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. SOLDERING FOOTPRINT* 10.49 8.38 16.155 2X 3.504 2X 1.016 5.080 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98ASB42761B D2PAK 3 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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