NVMFD5877NLWFT3G

NVMFD5877NL MOSFET – Power, Dual N-Channel, Logic Level, Dual SO8FL 60 V, 39 mW, 17 A http://onsemi.com Features • Low RDS(on) to Minimize Conduction Losses • Low Capacitance to Minimize Driver Losses • NVMFD5877NLWF − Wettable Flanks Option for Enhanced Optical • • V(BR)DSS Symbol Value Unit Drain−to−Source Voltage VDSS 60 V Gate−to−Source Voltage VGS "20 V ID 17 A Power Dissipation RYJ−mb (Notes 1, 2, 3) Continuous Drain Current RqJA (Notes 1 & 3, 4) Power Dissipation RqJA (Notes 1, 3) Pulsed Drain Current Tmb = 25°C Steady State Tmb = 100°C Tmb = 25°C Dual N−Channel Steady State Operating Junction and Storage Temperature Source Current (Body Diode) Single Pulse Drain− to−Source Avalanche Energy (TJ = 25°C, VDD = 24 V, VGS = 10 V, RG = 25 W) ID (IL(pk) = 14.5 A, L = 0.1 mH) A PD W 3.2 1.6 IDM 74 A TJ, Tstg −55 to +175 °C IS 19 A EAS 10.5 mJ TL 260 °C THERMAL RESISTANCE MAXIMUM RATINGS (Note 1) Junction−to−Mounting Board (top) − Steady State (Note 2, 3) Junction−to−Ambient − Steady State (Note 3) Symbol Value Unit RYJ−mb 6.5 °C/W RqJA 47 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. © Semiconductor Components Industries, LLC, 2014 July, 2019 − Rev. 9 1 DFN8 5x6 (SO8FL) CASE 506BT S1 G1 S2 G2 5877xx AYWZZ D1 D1 D2 D2 D2 D2 5877NL = Specific Device Code for NVMFD5877NL 5877LW = Specific Device Code for NVMFD5877NLWF A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability 40 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Parameter MARKING DIAGRAM D1 D1 5 (IL(pk) = 6.3 A, L = 2 mH) Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) W 6 TA = 100°C TA = 25°C, tp = 10 ms S2 12 TA = 100°C TA = 25°C G2 S1 23 Tmb = 100°C TA = 25°C D2 G1 12 PD 17 A 60 mW @ 4.5 V D1 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Continuous Drain Current RYJ−mb (Notes 1, 2, 3, 4) ID MAX 39 mW @ 10 V 60 V Inspection AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free and are RoHS Compliant Parameter RDS(on) MAX 1 ORDERING INFORMATION Device Package Shipping† NVMFD5877NLT1G DFN8 1500 / Tape & (Pb−Free) Reel NVMFD5877NLWFT1G DFN8 1500 / Tape & (Pb−Free) Reel NVMFD5877NLT3G DFN8 5000 / Tape & (Pb−Free) Reel NVMFD5877NLWFT3G DFN8 5000 / Tape & (Pb−Free) Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: NVMFD5877NL/D NVMFD5877NL 2. Psi (Y) is used as required per JESD51−12 for packages in which substantially less than 100% of the heat flows to single case surface. 3. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. 4. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. http://onsemi.com 2 NVMFD5877NL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 60 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current V 53 VGS = 0 V, VDS = 60 V mV/°C TJ = 25°C 1.0 TJ = 125°C 10 IGSS VDS = 0 V, VGS = ±20 V VGS(TH) VGS = VDS, ID = 250 mA ±100 mA nA ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On Resistance RDS(on) Forward Transconductance gFS 1.0 3.0 3.5 VGS = 10 V ID = 7.5 A VGS = 4.5 V ID = 7.5 A VDS = 15 V, ID = 5.0 A V mV/°C 31 39 42 60 mW 7.0 S pF CHARGES AND CAPACITANCES Input Capacitance Ciss 540 Output Capacitance Coss 55 Reverse Transfer Capacitance Crss 36 Total Gate Charge QG(TOT) 5.9 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD Total Gate Charge QG(TOT) VGS = 0 V, f = 1.0 MHz, VDS = 25 V VGS = 4.5 V, VDS = 48 V, ID = 5.0 A nC 0.62 1.64 2.80 VGS = 10 V, VDS = 48V, ID = 5.0A 11 td(on) 8.1 tr VGS = 4.5 V, VDS = 48 V, ID = 5.0 A, RG = 2.5 W 15.8 20 nC SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(off) 11.8 tf 3.9 td(on) 4.9 tr td(off) VGS = 10 V, VDS = 48 V, ID = 5.0 A, RG = 2.5 W tf ns ns 6.4 14.5 2.4 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD TJ = 25°C 0.8 TJ = 125°C 0.7 tRR Charge Time ta Discharge Time tb Reverse Recovery Charge VGS = 0 V, IS = 5.0 A 14.5 VGS = 0 V, dIS/dt = 100 A/ms, IS = 5.0 A QRR 1.2 V ns 11.5 3.1 11 nC nH PACKAGE PARASITIC VALUES Source Inductance LS 0.93 Drain Inductance LD 0.005 Gate Inductance LG Gate Resistance RG TA = 25°C 1.84 1.5 5. Pulse Test: pulse width = 300 ms, duty cycle v 2%. 6. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 3 W NVMFD5877NL TYPICAL CHARACTERISTICS 40 36 30 TJ = 25°C 32 VDS ≥ 10 V 4.5 V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 5V VGS = 10 V 28 24 4.0 V 20 16 12 8 3.5 V 4 3.0 V 2 3 4 5 3 4 5 Figure 2. Transfer Characteristics 0.055 0.050 0.045 0.040 0.035 0.030 4 5 6 7 8 9 VGS, GATE−TO−SOURCE VOLTAGE (V) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) Figure 1. On−Region Characteristics 0.060 10 0.065 0.055 0.050 0.040 0.035 0.025 8 10 13 15 18 20 23 25 ID, DRAIN CURRENT (A) 1E−05 1.7 1E−06 0.9 5 Figure 4. On−Resistance vs. Drain Current and Gate Voltage 1E−04 1.1 VGS = 10 V 0.030 ID = 7.5 A 1.9 V = 10 V GS 1.3 VGS = 4.5 V 0.045 2.1 1.5 TJ = 25°C 0.060 Figure 3. On−Resistance vs. Gate−to−Source Voltage 0.7 0.5 −50 2 VGS, GATE−TO−SOURCE VOLTAGE (V) ID = 10 A TJ = 25°C 3 1 TJ = −55°C VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0.065 0.025 0 IDSS, LEAKAGE (A) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 1 TJ = 25°C 10 TJ = 125°C 0 0 20 VGS = 0 V TJ = 150°C 1E−07 TJ = 125°C 1E−08 1E−09 TJ = 25°C 1E−10 1E−11 −25 0 25 50 75 100 125 150 175 1E−12 5 10 15 20 25 30 35 40 45 50 55 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 4 60 NVMFD5877NL TYPICAL CHARACTERISTICS C, CAPACITANCE (pF) 700 VGS = 0 V TJ = 25°C Ciss 600 VGS, GATE−TO−SOURCE VOLTAGE (V) 800 500 400 300 200 Coss 100 0 Crss 0 5 10 15 20 25 30 8 7 6 5 4 Qgs Qgd 3 TJ = 25°C VDD = 48 V ID = 5 A 2 1 0 0 1 2 3 4 5 6 7 8 9 10 DRAIN−TO−SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC) Figure 8. Gate−to−Source vs. Gate Charge 11 40 100 IS, SOURCE CURRENT (A) VDD = 48 V ID = 5 A VGS = 10 V td(off) tf tr 10 td(on) 1 10 100 VGS = 0 V TJ = 25°C 30 20 10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage 100 10 ms ID, DRAIN CURRENT (A) t, TIME (ns) QT 9 Figure 7. Capacitance Variation 1000 1 10 100 ms 10 1 ms VGS = 20 V Single Pulse TC = 25°C 1 10 ms RDS(on) Limit Thermal Limit Package Limit 0.1 0.1 dc 1 10 VDS, DRAIN VOLTAGE (V) Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 5 100 0.9 1.0 NVMFD5877NL TYPICAL CHARACTERISTICS 100 Duty Cycle = 0.5 RqJA(t) (°C/W) 10 1 0.2 0.1 0.05 0.02 0.01 0.1 0.01 0.000001 Device Mounted on 650 mm2 2 oz Cu PCB Single Pulse 0.00001 0.0001 0.001 0.01 0.1 PULSE TIME (sec) Figure 12. Thermal Response http://onsemi.com 6 1 10 100 1000 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual) CASE 506BT ISSUE F 1 2X SCALE 2:1 0.20 C D A B D1 8 7 6 ÉÉ ÉÉ ÉÉ PIN ONE IDENTIFIER NOTE 7 1 2 2X 0.20 C 5 DATE 23 NOV 2021 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP. 4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. 6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. 7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA. E1 E 4X h 3 4 c TOP VIEW A1 0.10 C A DETAIL B 0.10 C NOTE 4 C SIDE VIEW DETAIL A D2 D3 4X e 1 SEATING PLANE NOTE 6 ALTERNATE CONSTRUCTION DETAIL A L K 4 DIM A A1 b b1 c D D1 D2 D3 E E1 E2 e G h K K1 L M N MILLIMETERS NOM MIN MAX −−− 0.90 1.10 −−− −−− 0.05 0.33 0.42 0.51 0.33 0.42 0.51 0.20 −−− 0.33 5.15 BSC 4.70 4.90 5.10 3.90 4.10 4.30 1.50 1.70 1.90 6.15 BSC 5.70 5.90 6.10 3.90 4.15 4.40 1.27 BSC 0.45 0.55 0.65 −−− −−− 12 _ 0.51 −−− −−− 0.56 −−− −−− 0.48 0.61 0.71 3.25 3.50 3.75 1.80 2.00 2.20 SOLDERING FOOTPRINT* DETAIL B 4.56 M 4X b1 N 4X 8 G 5 8X 2X 2X 2.08 8X E2 0.75 0.56 b K1 BOTTOM VIEW 0.10 C A B 0.05 C GENERIC MARKING DIAGRAM* 1 XXXXXX AYWZZ NOTE 3 4.84 4X 6.59 3.70 0.70 4X XXXXXX = Specific Device Code A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability 1.40 2.30 1.00 1.27 PITCH 5.55 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON50417E Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DFN8 5X6, 1.27P DUAL FLAG (SO8FL−DUAL) PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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