NVMFS5844NLWFT1G

NTMFS5844NL, NVMFS5844NL MOSFET – Power, Single, N-Channel 60 V, 61 A, 12 mW Features • • • • • • Small Footprint (5x6 mm) for Compact Design Low RDS(on) to Minimize Conduction Losses Low QG and Capacitance to Minimize Driver Losses NVMFS5844NLWF − Wettable Flanks Product NVMFS Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant http://onsemi.com V(BR)DSS RDS(ON) MAX ID MAX 12 mW @ 10 V 60 V 61 A 16 mW @ 4.5 V D (5) MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Symbol Parameter Value Unit Drain−to−Source Voltage VDSS 60 V Gate−to−Source Voltage VGS "20 V ID 61 A Continuous Drain Current RYJ−mb (Notes 1, 2, 3, 4) Power Dissipation RYJ−mb (Notes 1, 2, 3) Continuous Drain Current RqJA (Notes 1, 3, 4) Power Dissipation RqJA (Notes 1 & 3) Pulsed Drain Current Tmb = 25°C Steady State Tmb = 100°C Tmb = 25°C Steady State PD 107 ID 11.2 Current Limited by Package (Note 4) TA = 25°C Operating Junction and Storage Temperature Source Current (Body Diode) Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V, IL(pk) = 31 A, L = 0.1 mH, RG = 25 W) Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) MARKING DIAGRAM A D 8.0 PD 3.7 IDM 247 A IDmaxPkg 80 A TJ, Tstg −55 to 175 °C IS 60 A EAS 48 mJ TA = 100°C TA = 25°C, tp = 10 ms N−CHANNEL MOSFET W 54 TA = 100°C TA = 25°C S (1,2,3) 43 Tmb = 100°C TA = 25°C G (4) W 1.8 1 DFN5 (SO−8FL) CASE 488AA STYLE 1 A Y W ZZ S S S G D XXXXXX AYWZZ D D = Assembly Location = Year = Work Week = Lot Traceability ORDERING INFORMATION TL 260 °C See detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. THERMAL RESISTANCE MAXIMUM RATINGS Parameter Junction−to−Mounting Board (top) − Steady State (Notes 2, 3) Junction−to−Ambient − Steady State (Note 3) Symbol Value Unit RYJ−mb 1.4 °C/W RqJA 41 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Psi (Y) is used as required per JESD51−12 for packages in which substantially less than 100% of the heat flows to single case surface. © Semiconductor Components Industries, LLC, 2013 May, 2019 − Rev. 5 1 Publication Order Number: NTMFS5844NL/D NTMFS5844NL, NVMFS5844NL 3. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. 4. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 60 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/ TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current V 57 VGS = 0 V, VDS = 60 V mV/°C TJ = 25 °C 1 TJ = 125°C 100 IGSS VDS = 0 V, VGS = ±20 V VGS(TH) VGS = VDS, ID = 250 mA mA ±100 nA 2.3 V ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On Resistance Forward Transconductance RDS(on) 1.5 6.2 mV/°C VGS = 10 V ID = 10 A 10.2 12 VGS = 4.5 V ID = 10 A 13 16 gFS VDS = 5 V, ID = 10 A 27 mW S CHARGES, CAPACITANCES & GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS 1460 VGS = 0 V, f = 1 MHz, VDS = 25 V 150 pF 96 Total Gate Charge QG(TOT) VGS = 10 V, VDS = 48 V; ID = 10 A Total Gate Charge QG(TOT) 15 Threshold Gate Charge QG(TH) 1.0 Gate−to−Source Charge QGS 4.0 Gate−to−Drain Charge QGD 8.0 Plateau Voltage VGP 3.0 V Gate Resistance RG 0.62 W td(ON) 12 VGS = 4.5 V, VDS = 48 V; ID = 10 A 30 nC SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time tr td(OFF) VGS = 4.5 V, VDS = 48 V, ID = 10 A, RG = 2.5 W tf 25 ns 20 10 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD TJ = 25°C 0.79 TJ = 125°C 0.65 tRR Charge Time ta Discharge Time tb Reverse Recovery Charge VGS = 0 V, IS = 10 A 1.2 V 19 VGS = 0 V, dIS/dt = 100 A/ms, IS = 10 A QRR 13 15 5. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 6. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 ns 6.0 nC NTMFS5844NL, NVMFS5844NL TYPICAL CHARACTERISTICS 50 3.6 V 40 3.4 V 30 60 50 40 30 20 3.2 V 10 3.0 V 10 0 2.8 V 0 1 2 3 4 5 TJ = 25°C 20 TJ = 125°C 1 TJ = −55°C 2 3 4 5 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0.030 ID = 10 A TJ = 25°C 0.025 0.020 0.015 0.010 0.005 VDS ≥ 10 V 70 2 4 6 8 10 12 VGS, GATE−TO−SOURCE VOLTAGE (V) 0.016 TJ = 25°C 0.014 VGS = 4.5 V 0.012 VGS = 10 V 0.010 0.008 5 10 15 20 25 30 35 40 ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 2.5 100,000 VGS = 0 V VGS = 10 V ID = 10 A 2 IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) TJ = 25°C 3.8 V 60 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 4.0 V RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) ID, DRAIN CURRENT (A) 70 80 VGS = 5 V 10 V ID, DRAIN CURRENT (A) 80 10,000 1.5 1 0.5 −50 −25 0 25 50 75 100 125 150 175 TJ = 150°C 1,000 100 TJ = 125°C 10 20 30 40 50 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 3 60 NTMFS5844NL, NVMFS5844NL TYPICAL CHARACTERISTICS 10 VGS = 0 V TJ = 25°C 1600 C, CAPACITANCE (pF) VGS, GATE−TO−SOURCE VOLTAGE (V) 1800 1400 Ciss 1200 1000 800 600 400 Coss 200 0 Crss 0 10 20 30 40 50 60 IS, SOURCE CURRENT (A) t, TIME (ns) 2 0 VDS = 48 V ID = 10 A TJ = 25°C 0 5 10 15 20 25 Qg, TOTAL GATE CHARGE (nC) td(off) tf td(on) 10 1 10 100 30 VGS = 0 V TJ = 25°C 30 20 10 0 0.5 0.6 0.7 0.8 0.9 1.0 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 1000 50 VGS = 10 V Single Pulse TC = 25°C 100 ms EAS, SINGLE PULSE DRAIN−TO− SOURCE AVALANCHE ENERGY (mJ) ID, DRAIN CURRENT (A) Qgd Qgs 40 tr 10 ms 1 ms 10 10 ms 0.1 4 Figure 8. Gate−to−Source Voltage vs. Total Charge 100 1 6 DRAIN−TO−SOURCE VOLTAGE (V) VDD = 48 V ID = 10 A VGS = 4.5 V 100 8 Figure 7. Capacitance Variation 1000 1 QT RDS(on) Limit Thermal Limit Package Limit 0.1 dc 1 10 VDS, DRAISN VOLTAGE (V) 100 40 30 20 10 0 25 Figure 11. Maximum Rated Forward Biased Safe Operating Area 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 4 175 NTMFS5844NL, NVMFS5844NL TYPICAL CHARACTERISTICS RqJA(t) (°C/W) EFFECTIVE TRANSIENT THERMAL RESISTANCE 100 Duty Cycle = 0.5 10 0.2 0.1 1 0.05 0.02 0.01 0.1 Single Pulse 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 PULSE TIME (sec) Figure 13. Thermal Response DEVICE ORDERING INFORMATION Marking Package Shipping† NTMFS5844NLT1G 5844NL DFN5 (Pb−Free) 1500 / Tape & Reel NVMFS5844NLT1G V5844L DFN5 (Pb−Free) 1500 / Tape & Reel NVMFS5844NLWFT1G 5844LW DFN5 (Pb−Free) 1500 / Tape & Reel NVMFS5844NLT3G V5844L DFN5 (Pb−Free) 5000 / Tape & Reel NVMFS5844NLWFT3G 5844LW DFN5 (Pb−Free) 5000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN5 5x6, 1.27P (SO−8FL) CASE 488AA ISSUE N 1 DATE 25 JUN 2018 SCALE 2:1 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS. 0.20 C D A 2 B D1 2X 0.20 C 4X E1 2 q E c 1 2 3 A1 4 TOP VIEW C DETAIL A 0.10 C SEATING PLANE A 0.10 C SIDE VIEW MILLIMETERS MIN NOM MAX 0.90 1.00 1.10 0.00 −−− 0.05 0.33 0.41 0.51 0.23 0.28 0.33 5.00 5.15 5.30 4.70 4.90 5.10 3.80 4.00 4.20 6.00 6.30 6.15 5.70 5.90 6.10 3.45 3.65 3.85 1.27 BSC 0.51 0.575 0.71 1.20 1.35 1.50 0.51 0.575 0.71 0.125 REF 3.00 3.40 3.80 0_ −−− 12 _ DIM A A1 b c D D1 D2 E E1 E2 e G K L L1 M q GENERIC MARKING DIAGRAM* DETAIL A 1 0.10 b C A B 0.05 c 8X XXXXXX AYWZZ e/2 e L 1 4 K RECOMMENDED SOLDERING FOOTPRINT* E2 PIN 5 (EXPOSED PAD) L1 M 2X 0.495 4.560 2X 1.530 G D2 2X BOTTOM VIEW XXXXXX = Specific Device Code A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Some products may not follow the Generic Marking. 0.475 3.200 4.530 STYLE 1: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 1.330 STYLE 2: 2X PIN 1. ANODE 0.905 2. ANODE 3. ANODE 4. NO CONNECT 0.965 5. CATHODE 1 4X 1.000 4X 0.750 1.270 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON14036D DFN5 5x6, 1.27P (SO−8FL) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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