NVMFS5C646NLT1G

NVMFS5C646NL Power MOSFET 60 V, 4.7 mW, 93 A, Single N−Channel Features • • • • • • Small Footprint (5x6 mm) for Compact Design Low RDS(on) to Minimize Conduction Losses Low QG and Capacitance to Minimize Driver Losses NVMFS5C646NLWF − Wettable Flank Option for Enhanced Optical Inspection AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant www.onsemi.com V(BR)DSS RDS(ON) MAX 4.7 mW @ 10 V 60 V Symbol Value Unit Drain−to−Source Voltage VDSS 60 V Gate−to−Source Voltage VGS ±20 V ID 93 A Continuous Drain Current RqJC (Notes 1, 3) TC = 25°C Power Dissipation RqJC (Note 1) Continuous Drain Current RqJA (Notes 1, 2, 3) Steady State TC = 100°C TC = 25°C TC = 100°C TA = 25°C Power Dissipation RqJA (Notes 1 & 2) Pulsed Drain Current Steady State ID TA = 25°C, tp = 10 ms Source Current (Body Diode) G (4) S (1,2,3) N−CHANNEL MOSFET A 20 MARKING DIAGRAM 14 PD TA = 100°C Operating Junction and Storage Temperature W 79 40 TA = 100°C TA = 25°C D (5,6) 65 PD W 3.7 1.8 IDM 750 A TJ, Tstg −55 to +175 °C IS 100 A Single Pulse Drain−to−Source Avalanche Energy (IL(pk) = 5 A) EAS 185 mJ Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 93 A 6.3 mW @ 4.5 V MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter ID MAX 1 DFN5 (SO−8FL) CASE 488AA STYLE 1 D S S S G D XXXXXX AYWZZ D D XXXXXX = 5C646L XXXXXX = (NVMFS5C646NL) or XXXXXX = 646LWF XXXXXX = (NVMFS5C646NLWF) A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability THERMAL RESISTANCE MAXIMUM RATINGS Symbol Value Unit ORDERING INFORMATION Junction−to−Case − Steady State Parameter RqJC 1.9 °C/W Junction−to−Ambient − Steady State (Note 2) RqJA 41 See detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet. 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. 3. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. © Semiconductor Components Industries, LLC, 2016 March, 2018 − Rev. 6 1 Publication Order Number: NVMFS5C646NL/D NVMFS5C646NL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 60 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/ TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current V 15.5 VGS = 0 V, VDS = 60 V mV/°C TJ = 25 °C 10 TJ = 125°C 250 IGSS VDS = 0 V, VGS = ±16 V VGS(TH) VGS = VDS, ID = 80 mA ±100 mA nA ON CHARACTERISTICS (Note 4) Gate Threshold Voltage Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On Resistance Forward Transconductance RDS(on) 1.2 2.0 −4.9 VGS = 10 V ID = 50 A 3.8 4.7 VGS = 4.5 V ID = 50 A 5.0 6.3 gFS VDS = 15 V, ID = 50 A V mV/°C 105 mW S CHARGES, CAPACITANCES & GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS 2164 VGS = 0 V, f = 1 MHz, VDS = 25 V 900 pF 17 Total Gate Charge QG(TOT) VGS = 4.5 V, VDS = 30 V; ID = 25 A 15.7 Total Gate Charge QG(TOT) VGS = 10 V, VDS = 30 V; ID = 25 A 33.7 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD Plateau Voltage VGP 2.8 td(ON) 10.4 1.5 VGS = 4.5 V, VDS = 30 V; ID = 25 A nC 5.6 5.1 V SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time tr td(OFF) VGS = 4.5 V, VDS = 30 V, ID = 25 A, RG = 2.5 W tf 14.9 ns 23.6 5.1 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge VSD VGS = 0 V, IS = 50 A TJ = 25°C 0.88 TJ = 125°C 0.78 tRR ta tb 1.2 V 40.9 VGS = 0 V, dIS/dt = 100 A/ms, IS = 50 A QRR 20.8 ns 20.1 32 nC 4. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 5. Switching characteristics are independent of operating junction temperatures. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 2 NVMFS5C646NL 3.8 V 140 10 V to 4.5 V 120 3.6 V 100 3.4 V 80 3.2 V 60 3.0 V 40 2.8 V 0 0.5 1.0 1.5 2.0 2.5 120 TJ = −55°C 100 80 60 40 0 3.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0.008 TJ = 25°C ID = 50 A 0.007 0.006 0.005 0.004 0.003 0 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 3 4 5 6 7 8 9 VGS, GATE VOLTAGE (V) 10 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) TJ = 25°C 20 20 0 TJ = 125°C 140 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) TYPICAL CHARACTERISTICS 0.007 4.0 TJ = 25°C 0.006 VGS = 4.5 V 0.005 VGS = 10 V 0.004 0.003 10 30 50 70 90 110 130 150 ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage VGS = 10 V ID = 40 A 1.7 TJ = 125°C IDSS, LEAKAGE (nA) RDS(on), NORMALIZED DRAIN−TO− SOURCE RESISTANCE 100,000 1.9 1.5 1.3 1.1 10,000 TJ = 85°C 1000 100 0.9 0.7 −50 −25 0 25 50 75 100 125 150 175 10 5 15 25 35 45 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage www.onsemi.com 3 55 NVMFS5C646NL C, CAPACITANCE (pF) CISS 2000 1600 VGS = 0 V TJ = 25°C f = 1 MHz COSS 1200 800 400 0 CRSS 0 10 20 30 40 50 60 VGS, GATE−TO−SOURCE VOLTAGE (V) 10 2400 30 QT 25 8 20 6 15 QGD QGS 4 2 0 10 VDS = 30 V TJ = 25°C ID = 25 A 0 4 8 12 16 20 24 28 5 32 0 VDS, DRAIN−TO−SOURCE VOLTAGE (V) QG, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge VDS, DRAIN−TO−SOURCE VOLTAGE (V) TYPICAL CHARACTERISTICS 1000 td(off) tf 100 t, TIME (ns) IS, SOURCE CURRENT (A) 45 VGS = 4.5 V VDD = 30 V ID = 25 A tr td(on) 10 40 TJ = 125°C 35 30 TJ = 25°C 25 20 15 TJ = −55°C 10 5 1 1 10 0 100 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 1000 100 TC = 25°C VGS ≤ 10 V 0.01 ms 0.1 ms 10 1 ms dc 10 ms 10 TJ(initial) = 25°C IPEAK (A) IDS (A) 100 TJ(initial) = 100°C 1 RDS(on) Limit Thermal Limit Package Limit 1 0.1 1 10 0.1 100 1E−04 1E−03 VDS (V) TIME IN AVALANCHE (s) Figure 11. Safe Operating Area Figure 12. IPEAK vs. Time in Avalanche www.onsemi.com 4 1E−02 NVMFS5C646NL 100 RqJA(t) (°C/W) 50% Duty Cycle 10 20% 10% 5% 1 2% 1% NVMFS5C646NL 650 mm2, 2 oz., Cu Single Layer Pad 0.1 Single Pulse 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 PULSE TIME (sec) Figure 13. Thermal Characteristics DEVICE ORDERING INFORMATION Device Marking Package Shipping† NVMFS5C646NLT1G 5C646L DFN5 (Pb−Free) 1500 / Tape & Reel NVMFS5C646NLWFT1G 646LWF DFN5 (Pb−Free, Wettable Flanks) 1500 / Tape & Reel NVMFS5C646NLT3G 5C646L DFN5 (Pb−Free) 5000 / Tape & Reel NVMFS5C646NLWFT3G 646LWF DFN5 (Pb−Free, Wettable Flanks) 5000 / Tape & Reel NVMFS5C646NLAFT1G 5C646L DFN5 (Pb−Free) 1500 / Tape & Reel NVMFS5C646NLWFAFT1G 646LWF DFN5 (Pb−Free, Wettable Flanks) 1500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN5 5x6, 1.27P (SO−8FL) CASE 488AA ISSUE N 1 DATE 25 JUN 2018 SCALE 2:1 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS. 0.20 C D A 2 B D1 2X 0.20 C 4X E1 2 q E c 1 2 3 A1 4 TOP VIEW C DETAIL A 0.10 C SEATING PLANE A 0.10 C SIDE VIEW MILLIMETERS MIN NOM MAX 0.90 1.00 1.10 0.00 −−− 0.05 0.33 0.41 0.51 0.23 0.28 0.33 5.00 5.15 5.30 4.70 4.90 5.10 3.80 4.00 4.20 6.00 6.30 6.15 5.70 5.90 6.10 3.45 3.65 3.85 1.27 BSC 0.51 0.575 0.71 1.20 1.35 1.50 0.51 0.575 0.71 0.125 REF 3.00 3.40 3.80 0_ −−− 12 _ DIM A A1 b c D D1 D2 E E1 E2 e G K L L1 M q GENERIC MARKING DIAGRAM* DETAIL A 1 0.10 b C A B 0.05 c 8X XXXXXX AYWZZ e/2 e L 1 4 K RECOMMENDED SOLDERING FOOTPRINT* E2 PIN 5 (EXPOSED PAD) L1 M 2X 0.495 4.560 2X 1.530 G D2 2X BOTTOM VIEW XXXXXX = Specific Device Code A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Some products may not follow the Generic Marking. 0.475 3.200 4.530 STYLE 1: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 1.330 STYLE 2: 2X PIN 1. ANODE 0.905 2. ANODE 3. ANODE 4. NO CONNECT 0.965 5. CATHODE 1 4X 1.000 4X 0.750 1.270 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON14036D DFN5 5x6, 1.27P (SO−8FL) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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