NVMFS6H801NLT1G

DATA SHEET www.onsemi.com MOSFET - Power, Single N-Channel V(BR)DSS RDS(ON) MAX 2.7 mW @ 10 V 80 V 80 V, 2.7 mW, 160 A ID MAX 3.3 mW @ 4.5 V NVMFS6H801NL 160 A D (5,6) Features • • • • • • Small Footprint (5x6 mm) for Compact Design Low RDS(on) to Minimize Conduction Losses Low QG and Capacitance to Minimize Driver Losses NVMFS6H801NLWF − Wettable Flank Option for Enhanced Optical Inspection AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant G (4) S (1,2,3) N−CHANNEL MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Symbol Value Unit Drain−to−Source Voltage VDSS 80 V Gate−to−Source Voltage VGS ±20 V ID 160 A Continuous Drain Current RqJC (Notes 1, 3) Steady State Power Dissipation RqJC (Note 1) Continuous Drain Current RqJA (Notes 1, 2, 3) TC = 100°C TC = 25°C 113 PD TC = 100°C Steady State Power Dissipation RqJA (Notes 1, 2) Pulsed Drain Current TC = 25°C TA = 25°C TA = 100°C TA = 25°C PD A 24 W 3.8 1.9 IDM 900 A TJ, Tstg −55 to +175 °C IS 139 A Single Pulse Drain−to−Source Avalanche Energy (IL(pk) = 12.2 A) EAS 706 mJ Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C TA = 25°C, tp = 10 ms Operating Junction and Storage Temperature Range Source Current (Body Diode) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL RESISTANCE MAXIMUM RATINGS Parameter DFNW5 (FULL−CUT SO8FL WF) CASE 507BA MARKING DIAGRAM 17 TA = 100°C DFN5 (SO−8FL) CASE 488AA STYLE 1 W 167 83 ID 1 Symbol Value Unit Junction−to−Case − Steady State RqJC 0.9 °C/W Junction−to−Ambient − Steady State (Note 2) RqJA 39 D S S S G D XXXXXX AYWZZ D D XXXXXX = 6H801L XXXXXX = (NVMFS6H801NL) or XXXXXX = 801LWF XXXXXX = (NVMFS6H801NLWF) A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet. 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. 3. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. © Semiconductor Components Industries, LLC, 2019 May, 2022 − Rev. 1 1 Publication Order Number: NVMFS6H801NL/D NVMFS6H801NL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage V(BR)DSS Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/ TJ Zero Gate Voltage Drain Current Gate−to−Source Leakage Current IDSS 80 VGS = 0 V, ID = 250 mA V 45.6 VGS = 0 V, VDS = 80 V mV/°C TJ = 25 °C 10 TJ = 125°C 100 IGSS VDS = 0 V, VGS = 20 V 100 VGS(TH) VGS = VDS, ID = 250 mA mA nA ON CHARACTERISTICS (Note 4) Gate Threshold Voltage Threshold Temperature Coefficient Drain−to−Source On Resistance Forward Transconductance VGS(TH)/TJ RDS(on) gFS 1.2 2.0 −5.3 V mV/°C VGS = 10 V ID = 50 A 2.2 2.7 mW VGS = 4.5 V ID = 50 A 2.6 3.3 mW VDS = 8 V, ID = 50 A 240 S VGS = 0 V, f = 1 MHz, VDS = 40 V 5126 pF CHARGES, CAPACITANCES & GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS 657 Reverse Transfer Capacitance CRSS 30 Total Gate Charge QG(TOT) VGS = 10 V, VDS = 40 V; ID = 50 A 90 Threshold Gate Charge QG(TH) VGS = 4.5 V, VDS = 40 V; ID = 50 A 8 Gate−to−Source Charge QGS 14 Gate−to−Drain Charge QGD 16 Plateau Voltage Total Gate Charge nC VGP 3 V QG(TOT) 44 nC 25 ns SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(ON) tr VGS = 4.5 V, VDS = 64 V, ID = 50 A, RG = 2.5 W 99 td(OFF) 50 tf 20 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge VSD tRR ta VGS = 0 V, IS = 50 A TJ = 25°C 0.76 TJ = 125°C 0.61 VGS = 0 V, dIS/dt = 100 A/ms, IS = 50 A 66 1.2 V ns 38 tb 28 QRR 92 nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 5. Switching characteristics are independent of operating junction temperatures. www.onsemi.com 2 NVMFS6H801NL TYPICAL CHARACTERISTICS 160 140 140 ID, DRAIN CURRENT (A) 3.0 V 120 3.2 V 100 80 2.8 V 60 40 2.6 V 120 100 80 60 20 0 0 0 1 2 4 3 5 0 1.0 1.5 2.0 TJ = −55°C 2.5 3.5 3.0 Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics TJ = 25°C ID = 50 A 5 4 3 2 1 4 6 5 7 8 10 9 VGS, GATE−TO−SOURCE VOLTAGE (V) 4 4.0 TJ = 25°C 3 VGS = 4.5 V VGS = 10 V 2 1 0 10 30 20 50 40 ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 1000 2.5 VGS = 10 V ID = 50 A 100 TJ = 175°C 2.0 IDSS, LEAKAGE (nA) RDS(on), NORMALIZED DRAIN−TO− SOURCE RESISTANCE 0.5 VGS, GATE−TO−SOURCE VOLTAGE (V) 6 3 TJ = 125°C VDS, DRAIN−TO−SOURCE VOLTAGE (V) 7 0 TJ = 25°C 40 20 RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) ID, DRAIN CURRENT (A) 160 VGS = 10 V to 3.4 V 1.5 1.0 TJ = 150°C 10 TJ = 125°C 1 TJ = 85°C 0.1 TJ = 25°C 0.01 0.001 0.5 −50 −25 0 25 50 75 100 125 150 175 0.0001 5 15 25 35 45 55 65 75 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage www.onsemi.com 3 NVMFS6H801NL 10K CISS C, CAPACITANCE (pF) 1K COSS 100 CRSS 10 1 VGS = 0 V TJ = 25°C f = 1 MHz 0 10 20 30 40 50 60 70 80 VGS, GATE−TO−SOURCE VOLTAGE (V) TYPICAL CHARACTERISTICS (continued) 6 QGS 4 QGD VDS = 40 V ID = 50 A TJ = 25°C 2 0 10 0 20 30 50 70 60 90 80 Figure 7. Capacitance Variation Figure 8. Gate−to−Source Voltage vs. Total Charge tr td(off) td(on) tf 10 VGS = 4.5 V VDS = 64 V ID = 50 A 1 10 VGS = 0 V 10 TJ = 125°C 1 0.3 50 0.4 TJ = −55°C TJ = 25°C 0.5 0.6 0.7 0.8 0.9 1.0 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 1000 100 100 IPEAK (A) TJ(initial) = 25°C 10 ms 10 TA = 25°C Single Pulse 1 VGS ≤ 10 V 0.1 40 QG, TOTAL GATE CHARGE (nC) IS, SOURCE CURRENT (A) t, TIME (ns) 8 50 100 ID, DRAIN CURRENT (A) 10 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 1000 1 12 0.1 10 TJ(initial) = 100°C 0.5 ms 1 ms RDS(on) Limit Thermal Limit Package Limit 1 10 10 ms 100 1000 1 0.0001 0.001 0.01 VDS, DRAIN−TO−SOURCE VOLTAGE (V) TIME IN AVALANCHE (s) Figure 11. Safe Operating Area Figure 12. Maximum Drain Current vs. Time in Avalanche www.onsemi.com 4 NVMFS6H801NL TYPICAL CHARACTERISTICS (continued) 100 R(t) (°C/W) 50% Duty Cycle 10 20% 10% 5% 1 2% 1% 0.1 Single Pulse 0.01 0.000001 0.00001 0.0001 0.001 0.01 1 0.1 10 100 1000 PULSE TIME (sec) Figure 13. Thermal Response DEVICE ORDERING INFORMATION Device Marking Package Shipping† NVMFS6H801NLT1G 6H801L DFN5 (Pb−Free) 1500 / Tape & Reel NVMFS6H801NLWFT1G 801LWF DFNW5 (Pb−Free, Wettable Flanks) 1500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN5 5x6, 1.27P (SO−8FL) CASE 488AA ISSUE N 1 DATE 25 JUN 2018 SCALE 2:1 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS. 0.20 C D 2 A B D1 2X 0.20 C 4X E1 2 1 2 3 q E c A1 4 TOP VIEW C DETAIL A 0.10 C SEATING PLANE A 0.10 C SIDE VIEW MILLIMETERS MIN NOM MAX 0.90 1.00 1.10 0.00 −−− 0.05 0.33 0.41 0.51 0.23 0.28 0.33 5.00 5.15 5.30 4.70 4.90 5.10 3.80 4.00 4.20 6.00 6.30 6.15 5.70 5.90 6.10 3.45 3.65 3.85 1.27 BSC 0.51 0.575 0.71 1.20 1.35 1.50 0.51 0.575 0.71 0.125 REF 3.00 3.40 3.80 0_ −−− 12 _ DIM A A1 b c D D1 D2 E E1 E2 e G K L L1 M q GENERIC MARKING DIAGRAM* DETAIL A 1 0.10 b C A B 0.05 c 8X XXXXXX AYWZZ e/2 e L 1 4 K PIN 5 (EXPOSED PAD) RECOMMENDED SOLDERING FOOTPRINT* E2 L1 M 2X 0.495 4.560 2X 1.530 G D2 BOTTOM VIEW 2X XXXXXX = Specific Device Code A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Some products may not follow the Generic Marking. 0.475 3.200 4.530 STYLE 1: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 1.330 STYLE 2: 2X PIN 1. ANODE 0.905 2. ANODE 3. ANODE 4. NO CONNECT 0.965 5. CATHODE 1 4X 1.000 4X 0.750 1.270 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON14036D DFN5 5x6, 1.27P (SO−8FL) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFNW5 5x6 (FULL−CUT SO8FL WF) CASE 507BA ISSUE A DATE 03 FEB 2021 q q GENERIC MARKING DIAGRAM* 1 XXXXXX AYWZZ XXXXXX A Y W ZZ = Specific Device Code *This information is generic. Please refer to = Assembly Location device data sheet for actual part marking. = Year Pb−Free indicator, “G” or microdot “ G”, = Work Week may or may not be present. Some products = Lot Traceability may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON26450H Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DFNW5 5x6 (FULL−CUT SO8FL WF) PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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