NVMTS0D7N06CLTXG

MOSFET - Power, Single N-Channel 60 V, 0.68 mW, 477 A NVMTS0D7N06CL Features • • • • • • • Small Footprint (8x8 mm) for Compact Design Low RDS(on) to Minimize Conduction Losses Low QG and Capacitance to Minimize Driver Losses Power 88 Package, Industry Standard AEC−Q101 Qualified and PPAP Capable Wettable Flank Option for Enhanced Optical Inspection These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant www.onsemi.com V(BR)DSS RDS(ON) MAX 0.68 mW @ 10 V 60 V 0.90 mW @ 4.5 V ID MAX 477 A D (5−8) MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Drain−to−Source Voltage Gate−to−Source Voltage Continuous Drain Current RqJC (Notes 1, 3) TC = 25°C Power Dissipation RqJC (Note 1) Continuous Drain Current RqJA (Notes 1, 2, 3) Steady State Pulsed Drain Current Value Unit VDSS 60 V VGS ±20 V ID 477 A TC = 100°C TC = 25°C PD Steady State ID W A 62.2 44.0 PD TA = 100°C W 5.0 2.5 IDM 900 A TJ, Tstg −55 to +175 °C IS 245.5 A Single Pulse Drain−to−Source Avalanche Energy (IL(pk) = 40 A) EAS 1754 mJ Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C TA = 25°C, tp = 10 ms Operating Junction and Storage Temperature Range Source Current (Body Diode) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL RESISTANCE MAXIMUM RATINGS Parameter Symbol Value Unit °C/W Junction−to−Case − Steady State RqJC 0.5 Junction−to−Ambient − Steady State (Note 2) RqJA 30 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. 3. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. © Semiconductor Components Industries, LLC, 2017 April, 2020 − Rev. 3 S (2−4) 147.3 TA = 100°C TA = 25°C 294.6 G (1) N−CHANNEL MOSFET 337.6 TC = 100°C TA = 25°C Power Dissipation RqJA (Notes 1, 2) Symbol 1 DFNW8 CASE 507AP MARKING DIAGRAM 0D7N06CL AWLYWW A WL Y WW = Assembly Location = Wafer Lot Code = Year Code = Work Week Code ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet. Publication Order Number: NVMTS0D7N06CL/D NVMTS0D7N06CL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 60 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/ TJ ID = 250 mA, ref to 25°C Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current VGS = 0 V, VDS = 60 V V 16.8 mV/°C TJ = 25°C 10 TJ = 125°C 250 IGSS VDS = 0 V, VGS = 20 V VGS(TH) VGS = VDS, ID = 250 mA VGS(TH)/TJ ID = 250 mA, ref to 25°C 100 mA nA ON CHARACTERISTICS (Note 4) Gate Threshold Voltage Threshold Temperature Coefficient Drain−to−Source On Resistance Forward Transconductance RDS(on) 1.0 2.5 −5.63 VGS = 10 V ID = 50 A 0.52 0.68 VGS = 4.5 V ID = 50 A 0.69 0.90 gFS VDS =15 V, ID = 50 A V mV/°C 310 mW S CHARGES, CAPACITANCES & GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS 16200 VGS = 0 V, f = 1 MHz, VDS = 25 V 8490 pF 270 Total Gate Charge QG(TOT) VGS = 4.5 V, VDS = 30 V; ID = 50 A 103 Total Gate Charge QG(TOT) VGS = 10 V, VDS = 30 V; ID = 50 A 225 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD Plateau Voltage VGP 2.46 td(ON) 35.3 21.6 VGS = 10 V, VDS = 30 V; ID = 50 A nC 36.5 20.7 V SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time tr td(OFF) VGS = 10 V, VDS = 30 V, ID = 50 A, RG = 2.5 W tf 26.3 ns 263 60.7 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge VSD VGS = 0 V, IS = 50 A TJ = 25°C 0.67 TJ = 125°C 0.59 tRR ta tb 1.2 V 115 VGS = 0 V, dIS/dt = 100 A/ms, IS = 50 A QRR 70 ns 45 307 nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 5. Switching characteristics are independent of operating junction temperatures. www.onsemi.com 2 NVMTS0D7N06CL TYPICAL CHARACTERISTICS 400 VDS = 10 V VGS = 3.6 to 10 V 320 3.0 V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 600 3.2 V 360 280 240 200 2.8 V 160 120 80 40 0 0.4 0.2 0.6 0.8 1.0 1.2 1.4 1.8 1.6 2.0 200 TJ = 25°C 100 TJ = 125°C 0 TJ = −55°C 2 3 5 4 Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics TJ = 25°C ID = 50 A 0.8 0.6 0.4 0.2 5 4 6 7 8 10 9 VGS, GATE−TO−SOURCE VOLTAGE (V) 1.2 TJ = 25°C ID = 50 A 1.0 0.8 VGS = 4.5 V 0.6 VGS = 10 V 0.4 0.2 0 10 30 50 70 90 110 130 150 170 190 ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 2.0 1E−02 VGS = 10 V ID = 50 A IDSS, LEAKAGE CURRENT (nA) RDS(on), NORMALIZED DRAIN−TO− SOURCE RESISTANCE 1 VGS, GATE−TO−SOURCE VOLTAGE (V) 1.0 3 300 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 1.2 0 400 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) 0 500 1E−03 1.5 TJ = 175°C TJ = 150°C 1E−04 1.0 TJ = 125°C 1E−05 0.5 0 −50 TJ = 85°C 1E−06 −25 0 25 50 75 100 125 150 175 1E−07 5 15 25 35 45 55 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage www.onsemi.com 3 NVMTS0D7N06CL TYPICAL CHARACTERISTICS VGS, GATE−TO−SOURCE VOLTAGE (V) 100K C, CAPACITANCE (pF) CISS COSS 10K 1K CRSS 100 0.01 1E−05 1 0.1 100 10 4 QGS td(off) t, TIME (ns) tr td(on) 0 25 0 22 12 42 32 10 50 75 100 125 150 175 200 TJ = 175°C TJ = 150°C TJ = 125°C 1 TJ = 25°C 0.1 TJ = −55°C 0 0.2 0.4 0.6 0.8 1.0 1.2 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 1000 1000 10 ms 100 100 RDS(on) Limit Thermal Limit Package Limit 0.1 1 10 TJ(initial) = 25°C IPEAK (A) TC = 25°C Single Pulse VGS ≤ 10 V 1 0.1 VDS = 30 V TJ = 25°C ID = 50 A 2 VGS = 0 V 1E−07 10 QGD Figure 8. Gate−to−Source Voltage vs. Total Charge tf ID, DRAIN CURRENT(A) 6 Figure 7. Capacitance Variation VGS = 10 V VDS = 30 V ID = 50 A 2 8 QG, TOTAL GATE CHARGE (nC) 1E−06 1E−08 10 VDS, DRAIN−TO−SOURCE VOLTAGE (V) IS, SOURCE CURRENT (A) 10 VGS = 0 V TJ = 25°C f = 1 MHz 12 0.5 ms 1 ms 10 ms TJ(initial) = 100°C 10 100 1000 1 0.0001 0.001 0.01 VDS, DRAIN−TO−SOURCE VOLTAGE (V) TIME IN AVALANCHE (s) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Drain Current vs. Time in Avalanche www.onsemi.com 4 NVMTS0D7N06CL TYPICAL CHARACTERISTICS 100 Duty Cycle = 0.5 R(t) (°C/W) 10 0.2 0.1 0.05 1 0.02 0.01 0.1 0.01 0.001 Single Pulse 0.000001 0.00001 0.0001 0.001 0.1 0.01 1 10 100 1000 PULSE TIME (sec) Figure 13. Thermal Characteristics DEVICE ORDERING INFORMATION Device NVMTS0D7N06CLTXG Marking Package Shipping† 0D7N06CL DFNW8 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TDFNW8 8.3x8.4, 2.0P, SINGLE COOL CASE 507AP ISSUE D DATE 29 MAR 2021 GENERIC MARKING DIAGRAM* XXXX A WL Y WW = Specific Device Code = Assembly Location = Wafer Lot Code = Year Code = Work Week Code *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON80534G Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. TDFNW8 8.3x8.4, 2.0P, SINGLE COOL PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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