NXV04V120DB1

Three Phase Inverter Automotive Power MOSFET Module NXV04V120DB1 Features • • • • • • • • • Three−Phase Inverter Bridge for Variable Speed Motor Drive RC Snubber for Low EMI Current Sensing and Temperature Sensing Electrically Isolated DBC Substrate for Low Thermal Resistance Compact Design for Low Total Module Resistance Module Serialization for Full Traceability AEC Qualified − AQG324 PPAP Capable This Device is Pb−free, RoHS and UL94−V0 Compliant www.onsemi.com Applications • 12 V Motor Control • Electric and Electro−Hydraulic Power Steering • Electric Water Pump, Oil Pump and Fan 19LD, APM, PDD STD CASE MODCD MARKING DIAGRAM Benefits • Enable Design of Small, Efficient and Reliable System for Reduced • • Vehicle Fuel Consumption and CO2 Emission Simplified Vehicle Assembly Enable Low Thermal Resistance to Junction−to−Heat Sink by Direct Mounting via Thermal Interface Material between Module Case and Heat Sink NXV04V120DB1 ZZZ ATYWW NNNNNN NXV04V120DB1 ZZZ AT Y WW NNN = Specific Device Code = Lot ID = Assembly & Test Location = Year = Work Week = Serial Number ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2019 October, 2019 − Rev. 0 1 Publication Order Number: NXV04V120DB1/D NXV04V120DB1 PACKAGE MARKING AND ORDERING INFORMATION Part Number Package Pb−Free and RoHS Compliant Operating Temperature Range Packing Method NXV04V120DB1 APM19−CBC Yes −40 ∼ 150°C Tube Figure 1. Pin Configuration PIN DESCRIPTION Pin Number Pin Name Pin Description 1 TEMP 1 NTC Thermistor Terminal 1 2 TEMP 2 NTC Thermistor Terminal 2 3 PHASE 3 SENSE 4 GATE 3 Gate of Q3, high side Phase 3 MOSFET 5 GATE 6 Gate of Q6, low side Phase 3 MOSFET 6 PHASE 2 SENSE 7 GATE 2 Gate of Q2, high side Phase 2 MOSFET 8 GATE 5 Gate of Q5, low side Phase 2 MOSFET 9 PHASE 1 SENSE Source of Q3 and Drain of Q6 Source of Q2 and Drain of Q5 Source of Q1 and Drain of Q4 10 GATE 1 11 VBAT SENSE Gate of Q2, high side Phase 1 MOSFET 12 GATE 4 13 SHUNT P Positive CSR sense pin and source connection for low side MOSFETs 14 SHUNT N Negative CSR sense pin and sense pin for battery return 15 VBAT Battery voltage power lead 16 GND Battery return power lead 17 PHASE 1 Phase 1 power lead 18 PHASE 2 Phase 2 power lead 19 PHASE 3 Phase 3 power lead Sense pin for battery voltage and Drain of high side MOSFETs Gate of Q4, low side Phase 1 MOSFET www.onsemi.com 2 NXV04V120DB1 Schematic Diagram VBAT SENSE VBAT GATE 3 GATE 2 Q1 Q3 Q2 GATE 1 PHASE 1 SENSE PHASE 1 PHASE 2 SENSE PHASE 2 PHASE 3 SENSE PHASE 3 Q4 Q6 Q5 R GATE 4 GATE 5 C GATE 6 SHUNT P TEMP 1 TEMP 2 CSR NTC SHUNT N GND Figure 2. Schematic Flammability Information Solder All materials present in the power module meet UL flammability rating class 94V−0 or higher. Solder used is a lead free SnAgCu alloy. Compliance to RoHS Directives The power module is 100% lead free and RoHS compliant 2000/53/C directive. ABSOLUTE MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Symbol Parameter Max Unit VDS Drain−to−Source Voltage 40 V VGS Gate−to−Source Voltage ±20 V Drain Current Continuous (TC = 25°C, TJ = 175°C) (Note 1) 160 A Single Pulse Avalanche Energy (Note 2) 340 mJ Maximum Junction Temperature 175 °C TSTG Storage Temperature Range 150 °C VISO Isolation Voltage 2500 Vrms ID EAS TJ(max) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Defined by design, not subject to production testing. The value is the result of the calculation, Min (package limit max current, Silicon limit max current) where the silicon limit current is calculated based on the maximum value which is not to exceed TJ = 175°C on maximum thermal limitation and on resistance. 2. Starting TJ = 25°C, L = 0.47 mH, IAS = 50 A, VDD = 40 V during inductor charging and VDD = 0 V during time in avalanche. www.onsemi.com 3 NXV04V120DB1 THERMAL CHARACTERISTICS Symbol Parameter Thermal Resistance, Junction−to−Case (Note 3) RqJC Min Typ Max Unit − − 1.2 K/W 3. Test method compliant with MIL−STD−883−1012.1, case temperature measured below the package at the chip center. Cosmetic oxidation and discolor on the DBC surface is allowed. MODULE SPECIFIC CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameters Test Conditions Symbol Min Typ Max Unit Drain−to−Source Breakdown Voltage ID = 250 mA, VGS = 0 V BVDSS 40 − − V Drain−to−Source Leakage Current VDS = 40 V, VGS = 0 V IDSS − − 1 mA Gate−to−Source Leakage Current VGS = ±20 V IGSS −100 − +100 nA VGS(th) 2.0 − 4.0 V VSD − − 0.955 V Drain−to−Source On Resistance, Q1 RDS(ON)Q1 − 0.85 1.1 mW Drain−to−Source On Resistance, Q2 RDS(ON)Q2 − 0.9 1.1 mW RDS(ON)Q3 − 1 1.2 mW RDS(ON)Q4 − 1.1 1.3 mW Drain−to−Source On Resistance, Q5 RDS(ON)Q5 − 1.3 1.5 mW Drain−to−Source On Resistance, Q6 RDS(ON)Q6 − 1.6 1.9 mW VBAT to PHASE 1 RDS(ON)MQ1 − 1.7 2 mW VBAT to PHASE 2 RDS(ON)MQ2 − 1.8 2 mW RDS(ON)MQ3 − 1.9 2.1 mW RDS(ON)MQ4 − 1.9 2.2 mW PHASE2 to GND RDS(ON)MQ5 − 2.1 2.4 mW PHASE3 to GND RDS(ON)MQ6 − 2.4 2.7 mW − 4.15 4.8 mW Gate−to−Source Threshold Voltage VGS = VDS, ID = 250 mA Body Diode Forward Voltage of MOSFET IS = 80 A, VGS = 0 V Drain−to−Source On Resistance, Q3 Drain−to−Source On Resistance, Q4 VBAT to PHASE 3 PHASE1 to GND Total Loop Resistance B+ ≥ Phase ≥ GND ID = 80 A, VGS = 10 V (Note 4) ID = 80 A, VGS = 10 V ID = 80 A, VGS = 10 V 4. All MOSFETs have same size and on resistance. However, the different values listed due to the different access points available inside the module for on resistance measurement. Q1 has the shortest measurement path in the layout, in this reason, on resistance of Q1 can be used for simple power loss calculation. COMPONENTS Symbol Spec Quantity Size RESISTOR 1.0 W 1 142 × 55 mil CAPACITOR 100 V, 0.022 mF 1 79 × 49 mil CURRENT SENSING RESISTOR 0.5 mW 1 250 × 120 mil NTC B57342V5103H060, 10 kW 1 63 × 32 mil www.onsemi.com 4 NXV04V120DB1 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted, Reference typical characteristics of FDBL9406−F085, TOLL) Parameter Symbol Test Conditions Min Typ Max Unit DYNAMIC CHARACTERISTICS Ciss Input Capacitance − 7735 − pF Coss Output Capacitance − 2160 − pF Crss Reverse Transfer Capacitance − 129 − pF Rg VDS = 25 V, VGS = 0 V, f = 1 MHz Gate Resistance f = 1 MHz − 2.5 − W Total Gate Charge VGS = 0 to 10 V − 90 112 nC Threshold Gate Charge VGS = 0 to 2 V − 13.5 18 nC Qgs Gate−to−Source Gate Charge 43 − nC Gate−to−Drain “Miller” Charge VDD = 32 V, ID = 80 A − Qgd − 10 − nC Turn−On Time − − 102 ns Turn−On Delay Time − 33 − ns − 40 − ns Qg(ToT) Qg(th) SWITCHING CHARACTERISTICS ton td(on) tr td(off) tf toff Turn−On Rise Time Turn−Off Delay Time VDD = 20 V, ID = 80 A, VGS = 10 V, RGEN = 6 W − 47 − ns Turn−Off Fall Time − 23 − ns Turn−Off Time − − 91 ns Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 5 NXV04V120DB1 TYPICAL CHARACTERISTICS (Graphs are generated using the die assembled in discrete package for reference purposes only. Datasheet of FDBL9406−F085 is available in the web) Figure 3. Forward Bias Safe Operating Area Figure 4. Unclamped Inductive Switching Capability Figure 5. Transfer Characteristics Figure 6. Forward Diode Characteristics Figure 7. Saturation Characteristics Figure 8. Saturation Characteristics www.onsemi.com 6 NXV04V120DB1 TYPICAL CHARACTERISTICS (continued) (Graphs are generated using the die assembled in discrete package for reference purposes only. Datasheet of FDBL9406−F085 is available in the web) Figure 9. RDS(on) vs. Gate Voltage Figure 10. Normalized RDS(on) vs. Junction Temperature Figure 11. Normalized Gate Threshold Voltage vs. Temperature Figure 12. Normalized Drain−to−Source Breakdown Voltage vs. Junction Temperature Figure 13. Capacitance vs. Drain−to−Source Voltage Figure 14. Gate Charge vs. Gate−to−Source Voltage www.onsemi.com 7 NXV04V120DB1 Figure 15. Flatness Measurement Position MECHANICAL CHARACTERISTICS AND RATINGS Parameter Test Conditions Device Flatness Refer to the package dimensions Mounting Torque Mounting screw: M3, recommended 0.7 N•m Weight www.onsemi.com 8 Min. Typ. Max. Units 0 − 150 um 0.4 − 0.8 N•m − 20 − g MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS 19LD, APM, PDD STD (APM19−CBC) CASE MODCD ISSUE O DOCUMENT NUMBER: DESCRIPTION: 98AON13505G DATE 30 NOV 2016 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 19LD, APM, PDD STD (APM19−CBC) PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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