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P5P2305AF-1H08SR

P5P2305AF-1H08SR

  • 厂商:

    ONSEMI(安森美)

  • 封装:

    SOICN8_150MIL

  • 描述:

    PLL BASED CLOCK DRIVER

  • 数据手册
  • 价格&库存
P5P2305AF-1H08SR 数据手册
ASM5P2305A, ASM5P2309A 3.3 V Zero Delay Buffer Description ASM5P2309A is a versatile, 3.3 V zero−delay buffer designed to distribute high−speed clocks. It accepts one reference input and drives out nine low−skew clocks. It is available in a 16−pin package. The ASM5P2305A is the eight−pin version of the ASM5P2309A. It accepts one reference input and drives out five low−skew clocks. The −1H version of the ASM5P230xA operates at up to 133 MHz frequencies, and has higher drive than the −1 devices. All parts have on−chip PLLs that lock to an input clock on the REF. The PLL feedback is on−chip and is obtained from the CLKOUT. ASM5P2309A has two banks of four outputs each, which can be controlled by the Select inputs as shown in the Select Input Decoding Table. The select input also allows the input clock to be directly applied to the outputs for chip and system testing purposes. Multiple ASM5P2309A and ASM5P2305A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 700 pS. All outputs have less than 200 pS of cycle−to−cycle jitter. The input and output propagation delay is guaranteed to be less than ±350 pS, and the output to output skew is guaranteed to be less than 200 pS. The ASM5P2309A and the ASM5P2305A are available in two different configurations, as shown in the ordering information table. The ASM5P2305A−1 / ASM5P2309A−1 is the base part. The ASM5P2305A−1H / ASM5P2309A−1H is the high drive version of the −1 and its rise and fall times are faster than −1 part. • 10 MHz to 133 MHz Operating Range, Compatible with CPU and • • • • • • • PCI Bus Frequencies Zero Input−output Propagation Delay Multiple Low−skew Outputs ♦ Output−output Skew less than 200 pS ♦ Device−device Skew less than 700 pS ♦ One Input Drives 9 Outputs, Grouped as 4 + 4 + 1 (ASM5P2309A) ♦ One Input Drives 5 Outputs (ASM5P2305A) Less than 200 pS Cycle−to−Cycle Jitter is Compatible with Pentium® Based Systems Test Mode to Bypass PLL (ASM5P2309A Only, Refer to Select Input Decoding Table) Packaging Information: ASM5P2309A: 16−pin SOIC, TSSOP ASM5P2305A: 8−pin SOIC, TSSOP Commercial and Industrial Temperature Range 3.3 V Operation Advanced 0.35 � CMOS Technology These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant © Semiconductor Components Industries, LLC, 2011 August, 2011 − Rev. 4 SOIC−8 S SUFFIX CASE 751BD TSSOP−8 T SUFFIX CASE 948AL SOIC−16 S SUFFIX CASE 751BG TSSOP−16 T SUFFIX CASE 948AN PIN CONFIGURATIONS 1 Features • • http://onsemi.com 1 REF CLKOUT CLK CLK4 CLK1 VDD GND CLK3 ASM5P2305A (Top View) 1 CLKOUT REF CLKA1 CLKA4 CLKA2 CLKA3 VDD VDD GND GND CLKB1 CLKB4 CLKB2 CLKB3 S2 S1 ASM5P2309A (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. Publication Order Number: ASM5P2305A/D ASM5P2305A, ASM5P2309A PLL CLKOUT MUX CLKA1 REF CLKA2 REF PLL ASM5P2309A CLKOUT CLKA3 CLKA4 CLK1 ASM5P2305A S1 CLK3 CLKB1 Select Input Decoding S2 CLK2 CLKB2 CLKB3 CLK4 CLKB4 Figure 1. Block Diagram Table 1. SELECT INPUT DECODING FOR ASM5P2309A S2 S1 Clock A1 − A4 Clock B1 − B4 CLKOUT (Note 1) Output Source PLL Shut−Down 0 0 Three−state Three−state Driven PLL N 0 1 Driven Three−state Driven PLL N 1 0 Driven Driven Driven Reference Y 1 1 Driven Driven Driven PLL N 1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and the output. For applications requiring zero input−output delay, all outputs, including CLKOUT, must be equally loaded. Even if CLKOUT is not used, it must have a capacitive load equal to that on other outputs, for obtaining zero input−output delay. Zero Delay and Skew Control All outputs should be uniformly loaded to achieve Zero Delay between input and output. Since the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input−output delay. REF−Input to CLKA / CLKB Delay (pS) 1500 1000 500 0 −30 −25 −20 −15 −10 −5 0 5 10 15 20 25 −500 −1000 −1500 Figure 2. Output Load Difference: CLKOUT Load − CLKA/CLKB Load (pF) http://onsemi.com 2 30 ASM5P2305A, ASM5P2309A Table 2. PIN DESCRIPTION FOR ASM5P2305A Pin # Pin Name Description 1 REF (Note 2) Input reference clock frequency, 5 V−tolerant input 2 CLK2 (Note 3) Buffered clock output 3 CLK1 (Note 3) Buffered clock output 4 GND 5 CLK3 (Note 3) 6 VDD 7 CLK4 (Note 3) 8 CLKOUT (Note 3) Ground Buffered clock output 3.3 V supply Buffered clock output Buffered clock output, internal feedback on this pin Table 3. PIN DESCRIPTION FOR ASM5P2309A Pin # Pin Name Description 1 REF (Note 2) 2 CLKA1 (Note 3) Buffered clock output, bank A 3 CLKA2 (Note 3) Buffered clock output, bank A Input reference clock frequency, 5 V tolerant input 4 VDD 3.3 V supply 5 GND Ground 6 CLKB1 (Note 3) Buffered clock output, bank B 7 CLKB2 (Note 3) Buffered clock output, bank B 8 S2 (Note 4) Select input, bit 2 9 S1 (Note 4) Select input, bit 1 10 CLKB3 (Note 3) Buffered clock output, bank B 11 CLKB4 (Note 3) Buffered clock output, bank B 12 GND Ground 13 VDD 3.3 V supply 14 CLKA3 (Note 3) Buffered clock output, bank A 15 CLKA4 (Note 3) Buffered clock output, bank A 16 CLKOUT (Note 3) Buffered output, internal feedback on this pin 2. Weak pull−down. 3. Weak pull−down on all outputs. 4. Weak pull−up on these inputs. http://onsemi.com 3 ASM5P2305A, ASM5P2309A Table 4. ABSOLUTE MAXIMUM RATINGS Parameter Min Max Unit −0.5 +4.6 V DC Input Voltage (Except REF) −0.5 VDD + 0.5 V DC Input Voltage (REF) −0.5 7 V Storage Temperature −65 +150 °C Max. Soldering Temperature (10 sec) 260 °C Junction Temperature 150 °C Static Discharge Voltage (As per JEDEC STD22− A114−B) 2000 V Supply Voltage to Ground Potential Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 5. OPERATING CONDITIONS (for ASM5P2305A (−1, −1H) and ASM5P2309A (−1, −1H)) Parameter VDD Description Supply Voltage Min Max Unit 3.0 3.6 V 0 70 °C −40 85 TA Operating Temperature (Ambient Temperature) CL Load Capacitance, below 100 MHz 30 pF Load Capacitance, from 100 MHz to 133 MHz 10 pF Input Capacitance 7 pF CIN Commercial temperature Industrial temperature Table 6. ELECTRICAL CHARACTERISTICS (for ASM5P2305A (−1, −1H) and ASM5P2309A (−1, −1H)) Parameter Description Test Conditions Min Typ Max Unit 0.8 V VIL Input LOW Voltage (Note 5) VIH Input HIGH Voltage (Note 5) IIL Input LOW Current VIN = 0 V 50 �A IIH Input HIGH Current VIN = VDD 100 �A VOL Output LOW Voltage (Note 6) IOL = 8 mA (−1) IOL = 12 mA (−1H) 0.4 V VOH Output HIGH Voltage (Note 6) IOH = −8 mA (−1) IOH = −12 mA (−1H) IDD Supply Current Unloaded outputs at 66.67 MHz, SEL inputs at VDD Commercial temp. Industrial temp. 2.2 5. REF input has a threshold voltage of VDD /2. 6. Parameter is guaranteed by design and characterization. Not 100% tested in production. http://onsemi.com 4 V V 2.4 30 32 mA ASM5P2305A, ASM5P2309A Table 7. SWITCHING CHARACTERISTICS (for ASM5P2305A (−1, −1H) and ASM5P2309A (−1, −1H) (Notes 7, 8) Parameter Test Conditions Min 30 pF load 10 pF load 10 10 Measured at 1.4 V, FOUT > 50 MHz 40 Measured at VDD /2, FOUT ≤ 50 MHz 45 Output Frequency Duty Cycle (Note 9) Output Rise Time (Note 9) Measured between 0.8 V and 2.0 V Measured between 2.0 V and 0.8 V (−1H) 100 133 MHz 50 60 % 50 55 2.25 1.5 nS 2 2.25 nS 1.5 2 200 pS Measured at VDD /2 0 ±350 pS Measured at VDD/2 on the CLKOUT pins of the device 0 All outputs equally loaded Delay, REF Rising Edge to CLKOUT Rising Edge (Note 9) 700 pS Measured at 66.67 MHz, loaded outputs 200 pS Stable power supply, valid clock presented on REF pin 1.0 mS Cycle−to−cycle Jitter (Note 9) PLL Lock Time (Note 9) Unit (−1) Output−to−output skew (Note 9) Device−to−Device Skew (Note 9) Max (−1) (−1H) Output Fall Time (Note 9) Typ 7. For all measurements use Test Circuit #1. 8. All parameters are specified with loaded outputs. 9. Parameter is guaranteed by design and characterization. Not 100% tested in production. TEST CIRCUIT #1 22 Q CLK OUT +3.3 V CLOAD VDD 0.1 �F 22 Q ASM5P2305A ASM5P2309A CLK A / CLK B GND CLOAD Figure 3. Test Circuit http://onsemi.com 5 ASM5P2305A, ASM5P2309A Switching Waveforms t1 t2 1.4 V 1.4 V 1.4 V OUTPUT Figure 4. Duty Cycle Timing 2V 2V 0.8 V VDD 0.8 V OUTPUT 0V t4 t3 Figure 5. All Outputs Rise/Fall Time 1.4 V OUTPUT 1.4 V OUTPUT t5 Figure 6. Output−Output Skew VDD/2 INPUT VDD/2 OUTPUT t6 Figure 7. Input−Output Propagation Delay VDD/2 CLKOUT, Device1 VDD/2 CLKOUT, Device2 t7 Figure 8. Device−Device Skew http://onsemi.com 6 ASM5P2305A, ASM5P2309A PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O E1 E SYMBOL MIN A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 e PIN # 1 IDENTIFICATION NOM MAX 4.00 1.27 BSC h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 θ A c e b L SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. http://onsemi.com 7 ASM5P2305A, ASM5P2309A PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O b SYMBOL MIN NOM A A1 E1 E MAX 1.20 0.05 0.15 A2 0.80 b 0.19 0.90 0.30 c 0.09 0.20 D 2.90 3.00 3.10 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 e 0.65 BSC L 1.00 REF L1 0.50 θ 0º 0.60 1.05 0.75 8º e TOP VIEW D A2 c 81 A A1 L1 SIDE VIEW L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. http://onsemi.com 8 ASM5P2305A, ASM5P2309A PACKAGE DIMENSIONS SOIC−16, 150 mils CASE 751BG−01 ISSUE O E1 E SYMBOL MIN A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 D 9.80 MAX 0.25 9.90 10.00 E 5.80 6.00 6.20 E1 3.80 3.90 4.00 e PIN#1 IDENTIFICATION NOM 1.27 BSC h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h 8 A e b c L A1 END VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. http://onsemi.com 9 ASM5P2305A, ASM5P2309A PACKAGE DIMENSIONS TSSOP16, 4.4x5 CASE 948AN−01 ISSUE O b SYMBOL MIN NOM A A1 MAX 1.10 0.05 0.15 A2 0.85 0.95 b 0.19 0.30 c 0.13 0.20 D 4.90 5.10 E 6.30 6.50 E1 4.30 4.50 E1 E e 0.65 BSC L 1.00 REF L1 0.45 0.75 θ 0º 8º e PIN#1 IDENTIFICATION TOP VIEW D A2 A c θ1 A1 L1 SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. http://onsemi.com 10 L ASM5P2305A, ASM5P2309A Table 8. ORDERING INFORMATION Part Number P5P2309AF−1−16ST Marking Package Type Temperature 5P2309AF−1 16−pin 150−mil SOIC−TUBE,Pb Free P5I2309AF−1−16ST 5I2309AF−1 16−pin 150−mil SOIC− TUBE,Pb Free P5P2309AF−116SR 5P2309AF−1 16−pin 150−mil SOIC−TAPE & REEL,Pb Free Commercial P5I2309AF−116SR 5I2309AF−1 16−pin 150−mil SOIC−TAPE & REEL,Pb Free Industrial P5P2309AF−1−16TT 5P2309AF−1 16−pin 4.4−mm TSSOP − TUBE,Pb Free Commercial ASM5I2309AF−1−16−TT 5I2309AF−1 16−pin 4.4−mm TSSOP − TUBE,Pb Free Industrial P5P2309AF−1−16TR 5P2309AF−1 16−pin 4.4−mm TSSOP − TAPE & REEL,Pb Free 5I2309AF−1 16− pin 4.4−mm TSSOP − TAPE & REEL,Pb Free ASM5I2309AF−1−16−TR Commercial Industrial Commercial Industrial P5P2309AF−1H16ST 5P2309AF−1H 16−pin 150−mil SOIC−TUBE,Pb Free Commercial ASM5I2309AF−1H−16−ST 5I2309AF−1H 16−pin 150−mil SOIC− TUBE,Pb Free Industrial P5P2309AF−1H16SR 5P2309AF−1H 16−pin 150−mil SOIC−TAPE & REEL,Pb Free Commercial ASM5I2309AF−1H−16−SR 5I2309AF−1H 16−pin 150−mil SOIC−TAPE & REEL,Pb Free Industrial ASM5P2309AF−1H−16−TT 5P2309AF−1H 16−pin 4.4−mm TSSOP − TUBE,Pb Free ASM5I2309AF−1H−16−TT 5I2309AF−1H 16−pin 4.4−mm TSSOP − TUBE,Pb Free P5P2309AF−1H16TR 5P2309AF−1H 16−pin 4.4−mm TSSOP − TAPE & REEL,Pb Free Commercial ASM5I2309AF−1H−16−TR 5I2309AF−1H 16−pin 4.4−mm TSSOP − TAPE & REEL,Pb Free Industrial P5P2305AF−1−08ST 5P2305AF−1 8−pin 150−mil SOIC−TUBE,Pb Free Commercial P5I2305AF−108ST 5I2305AF−1 8−pin 150−mil SOIC− TUBE,Pb Free Industrial P5P2305AF−1−08SR 5P2305AF−1 8−pin 150−mil SOIC−TAPE & REEL,Pb Free ASM5I2305AF−1−08−SR 5I2305AF−1 8−pin 150−mil SOIC−TAPE & REEL,Pb Free ASM5P2305AF−1−08−TT 5P2305AF−1 8−pin 4.4−mm TSSOP − TUBE,Pb Free Commercial ASM5I2305AF−1−08−TT 5I2305AF−1 8−pin 4.4−mm TSSOP − TUBE,Pb Free Industrial ASM5P2305AF−1−08−TR 5P2305AF−1 8−pin 4.4−mm TSSOP − TAPE & REEL,Pb Free Commercial ASM5I2305AF−1−08−TR 5I2305AF−1 8−pin 4.4−mm TSSOP − TAPE & REEL,Pb Free Industrial ASM5P2305AF−1H−08−ST Commercial Industrial Commercial Industrial 5P2305AF−1H 8−pin 150−mil SOIC−TUBE,Pb Free P5I2305AF−1H08ST 5I2305AF−1H 8−pin 150−mil SOIC− TUBE,Pb Free P5P2305AF−1H08SR 5P2305AF−1H 8−pin 150−mil SOIC−TAPE & REEL,Pb Free Commercial P5I2305AF−1H08SR 5I2305AF−1H 8−pin 150−mil SOIC−TAPE & REEL,Pb Free Industrial ASM5P2305AF−1H−08−TT 5P2305AF−1H 8−pin 4.4−mm TSSOP − TUBE,Pb Free Commercial ASM5I2305AF−1H−08−TT 5I2305AF−1H 8−pin 4.4−mm TSSOP − TUBE,Pb Free Industrial P5P2305AF−1H08TR 5P2305AF−1H 8−pin 4.4−mm TSSOP − TAPE & REEL,Pb Free Commercial P5I2305AF−1H08TR 5I2305AF−1H 8−pin 4.4−mm TSSOP − TAPE & REEL,Pb Free Industrial http://onsemi.com 11 Commercial Industrial ASM5P2305A, ASM5P2309A Pentium is a registered trademark of Intel Corporation. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 12 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative ASM5P2305A/D
P5P2305AF-1H08SR 价格&库存

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