74ABT573AD

Philips Semiconductors Product specification Octal D-type transparent latch (3-State) 74ABT573A FEATURES • 74ABT573A is flow-through pinout version of 74ABT373 • Inputs and outputs on opposite side of package allow easy • 3-State output buffers • Common output enable • Latch-up protection exceeds 500mA per JEDEC Std 17 • ESD protection exceeds 2000 V per MIL STD 883 Method 3015 • Power-up 3-State • Power-up reset DESCRIPTION The 74ABT573A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. and 200 V per Machine Model interface to microprocessors The 74ABT573A device is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled independently by Enable (E) and Output Enable (OE) control gates. The 74ABT573A is functionally identical to the 74ABT373 but has a flow-through pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. The data on the D inputs are transferred to the latch outputs when the Latch Enable (E) input is High. The latch remains transparent to the data inputs while E is High, and stores the data that is present one setup time before the High-to-Low enable transition. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in the High-impedance ”OFF” state, which means they will neither drive nor load the bus. QUICK REFERENCE DATA SYMBOL tPLH tPHL CIN COUT ICCZ PARAMETER Propagation delay Dn to Qn Input capacitance Output capacitance Total supply current CONDITIONS Tamb = 25°C; GND = 0V CL = 50pF; VCC = 5V VI = 0V or VCC Outputs disabled; VO = 0V or VCC Outputs disabled; VCC =5.5V TYPICAL 2.8 3.3 3 6 100 UNIT ns pF pF µA ORDERING INFORMATION PACKAGES 20-Pin Plastic DIP 20-Pin plastic SO 20-Pin Plastic SSOP Type II 20-Pin Plastic TSSOP Type I TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C OUTSIDE NORTH AMERICA 74ABT573A N 74ABT573A D 74ABT573A DB 74ABT573A PW NORTH AMERICA 74ABT573A N 74ABT573A D 74ABT573A DB 74ABT573APW DH DWG NUMBER SOT146-1 SOT163-1 SOT339-1 SOT360-1 PIN CONFIGURATION PIN DESCRIPTION PIN NUMBER 1 SYMBOL OE D0-D7 FUNCTION Output enable input (active-Low) Data inputs OE D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8 9 20 VCC 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7 11 E 2, 3, 4, 5, 6, 7, 8, 9 19, 18, 17, 16, 15, 14, 13, 12 11 10 20 Q0-Q7 E GND VCC Data outputs Enable input (active-High) Ground (0V) Positive supply voltage GND 10 SA00185 1995 Sep 06 1 853–1455 15703 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) 74ABT573A LOGIC SYMBOL (IEEE/IEC) 1 EN 11 C1 LOGIC SYMBOL 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2D 1 19 18 17 16 15 14 1 11 D0 E D1 D2 D3 D4 D5 D6 D7 OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 13 12 18 17 16 15 14 13 12 SA00187 SA00186 FUNCTION TABLE INPUTS OE L L L L L H H H= h= L= l= NC= X= Z= ↓= E H H ↓ ↓ L L H Dn L H l h X X Dn INTERNAL REGISTER L H L H NC NC Dn OUTPUTS Q0 – Q7 L H L H NC Z Z Enable and read register Latch and read register Hold Disable outputs OPERATING MODE High voltage level High voltage level one set-up time prior to the High-to-Low E transition Low voltage level Low voltage level one set-up time prior to the High-to-Low E transition No change Don’t care High impedance “off” state High-to-Low E transition LOGIC DIAGRAM D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 D D D D D D D D E Q E Q E Q E Q E Q E Q E Q E Q 11 E 1 OE 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7 SA00188 1995 Sep 06 2 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) 74ABT573A ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL VCC IIK VI IOK VOUT IOUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 VO < 0 output in Off or High state output in Low state VI < 0 CONDITIONS RATING –0.5 to +7.0 –18 –1.2 to +7.0 –50 –0.5 to +5.5 128 –65 to 150 UNIT V mA V mA V mA °C DC output diode current DC output voltage3 DC output current Storage temperature range NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER Min VCC VI VIH VIL IOH IOL ∆t/∆v Tamb DC supply voltage Input voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature range 0 –40 4.5 0 2.0 0.8 –32 64 5 +85 LIMITS Max 5.5 VCC V V V V mA mA ns/V °C UNIT 1995 Sep 06 3 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) 74ABT573A DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25°C Min VIK Input clamp voltage VCC = 4.5V; IIK = –18mA VCC = 4.5V; IOH = –3mA; VI = VIL or VIH VOH High-level output voltage VCC = 5.0V; IOH = –3mA; VI = VIL or VIH VCC = 4.5V; IOH = –32mA; VI = VIL or VIH VOL VRST II IOFF IPU/IPD IOZH IOZL ICEX IO ICCH ICCL ICCZ ∆ICC Additional supply current per input pin2 Quiescent supply current Low-level output voltage Power-up output low voltage3 Input leakage current Power-off leakage current Power-up/down 3-State output current4 3-State output High current 3-State output Low current Output High leakage current Output current1 VCC = 4.5V; IOL = 64mA; VI = VIL or VIH VCC = 5.5V; IO = 1mA; VI = GND or VCC VCC = 5.5V; VI = GND or 5.5V VCC = 0.0V; VO or VI ≤ 4.5V VCC = 2.0V; VO = 0.5V; VOE = Don’t Care; VI = GND or VCC VCC = 5.5V; VO = 2.7V; VI = VIL or VIH VCC = 5.5V; VO = 0.5V; VI = VIL or VIH VCC = 5.5V; VO = 5.5V; VI = GND or VCC VCC = 5.5V; VO = 2.5V VCC = 5.5V; Outputs High, VI = GND or VCC VCC = 5.5V; Outputs Low, VI = GND or VCC VCC = 5.5V; Outputs 3-State; VI = GND or VCC VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND –40 100 24 100 0.5 2.5 3.0 2.0 Typ –0.9 2.9 3.4 2.4 0.42 0.13 ±0.01 ±5.0 ±5.0 5.0 –5.0 5.0 0.55 0.55 ±1.0 ±100 ±50 50 –50 50 –180 250 30 250 1.5 –40 Max –1.2 2.5 3.0 2.0 0.55 0.55 ±1.0 ±100 ±50 50 –50 50 –180 250 30 250 1.5 Tamb = –40°C to +85°C Min Max –1.2 V V V V V V µA µA µA µA µA µA mA µA mA µA mA UNIT NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. For VCC = 2.1V to VCC = 5V " 10%, a transition time of up to 100µsec is permitted. AC CHARACTERISTICS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER WAVEFORM Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation delay Dn to Qn Propagation delay E to Qn Output enable time to High and Low level Output disable time from High and Low level 2 1 4 5 4 5 1.5 2.2 1.2 1.8 1.2 2.7 1.5 1.2 Tamb = +25oC VCC = +5.0V Typ 2.8 3.3 2.5 3.0 3.0 3.8 2.8 2.2 Max 4.0 4.8 4.0 4.4 4.5 5.3 4.1 3.4 Tamb = -40 to +85oC VCC = +5.0V ±0.5V Min 1.5 2.2 1.2 1.8 1.2 2.7 1.5 1.2 Max 4.5 5.3 4.5 4.7 5.2 5.7 4.5 3.8 ns ns ns ns UNIT 1995 Sep 06 4 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) 74ABT573A AC SETUP REQUIREMENTS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER WAVEFORM Tamb = +25oC VCC = +5.0V Min ts(H) ts(L) th(H) th(L) tw(H) Setup time, High or Low Dn to E Hold time, High or Low Dn to E E pulse width High 3 3 1 1.0 1.0 1.0 1.0 2.0 Typ 0.3 0.2 –0.1 –0.2 0.7 Tamb = -40 to +85oC VCC = +5.0V ±0.5V Min 1.0 1.0 1.0 1.0 2.0 ns ns ns UNIT AC WAVEFORMS VM = 1.5V, VIN = GND to 3.0V E VM VM VM OE VM tPZH VM tPHZ VOH–0.3V 0V tw(H) tPHL Qn VM tPLH VM Qn VM SA00063 SA00066 Waveform 1. Propagation Delay, Enable to Output, and Enable Pulse Width Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level Dn VM tPLH VM tPHL OE VM tPZL VM tPLZ Qn VM VM Qn VM VOL+0.3V VOL SA00064 SA00332 Waveform 2. Propagation Delay for Data to Outputs Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level Dn E 1995 Sep 06 ÉÉÉÉÉÉÉÉÉÉ ÉÉÉ É ÉÉÉ É ÉÉÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ VM VM VM VM ts(H) th(H) ts(L) th(L) VM VM NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SA00065 Waveform 3. Data Setup and Hold Times 5 Philips Semiconductors Product specification Octal D-type transparent latch (3-State) 74ABT573A TEST CIRCUIT AND WAVEFORM VCC 7.0V RL 90% NEGATIVE PULSE VM 10% tTHL (tF) CL RL POSITIVE PULSE 10% tW tTLH (tR) 90% 90% VM 10% 0V 10% 0V tTLH (tR) tTHL (tF) AMP (V) tW VM 90% AMP (V) PULSE GENERATOR VIN D.U.T. RT VOUT Test Circuit for 3-State Outputs VM SWITCH POSITION TEST tPLZ tPZL All other SWITCH closed closed open VM = 1.5V Input Pulse Definition DEFINITIONS RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. INPUT PULSE REQUIREMENTS FAMILY Amplitude 74ABT 3.0V Rep. Rate 1MHz tW 500ns tR 2.5ns tF 2.5ns SA00012 1995 Sep 06 6