74LV163D

INTEGRATED CIRCUITS 74LV163 Presettable synchronous 4-bit binary counter; synchronous reset Product specification Supersedes data of 1997 May 15 IC24 Data Handbook 1998 Apr 30 Philips Semiconductors Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; synchronous reset 74LV163 FEATURES • Optimized for low voltage applications: 1.0 to 3.6 V • Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V • Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, • Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, • Synchronous counting and loading • Two count enable inputs for n-bit cascading • Positive-edge triggered clock • Synchronous reset • Output capability: standard • ICC category: MSI DESCRIPTION The 74LV163 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT163. The 74LV163 is a synchronous presettable binary counter which features an internal look-head carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops Tamb = 25°C Tamb = 25°C clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock (providing that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (CEP and CET). A low level at the master reset input (MR) sets all four outputs of the flip-flops (Q0 to Q3) to LOW level after the next positive-going transition on the clock (CP) input (provided that the set-up and hold time requirements for MR are met). This action occurs regardless of the levels at PE, CET and CEP inputs. This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate. The look ahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH level output of Q0. This pulse can be used to enable the next cascading stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula: 1 f max + tp (max) (CP to TC) ) t su(CEP to CP) QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL PARAMETER Propagation delay CP to Qn CP to TC CET to TC Maximum clock frequency Input capacitance Power dissipation capacitance per gate VI = GND to VCC 1 CONDITIONS CL = 15 pF; VCC = 3.3 V TYPICAL 15 18 9 77 3.5 25 UNIT tPHL/tPLH fmax CI CPD ns MHz pF pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi ) (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL × VCC2 × fo) = sum of the outputs. ORDERING INFORMATION PACKAGES 16-Pin Plastic DIL 16-Pin Plastic SO 16-Pin Plastic SSOP Type II 16-Pin Plastic TSSOP Type I TEMPERATURE RANGE –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C OUTSIDE NORTH AMERICA 74LV163 N 74LV163 D 74LV163 DB 74LV163 PW NORTH AMERICA 74LV163 N 74LV163 D 74LV163 DB 74LV163PW DH PKG. DWG. # SOT38-4 SOT109-1 SOT338-1 SOT403-1 1998 Apr 30 2 853–1916 19318 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; synchronous reset 74LV163 PIN CONFIGURATION MR CP D0 D1 D2 D3 CEP GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 V CC TC Q0 LOGIC SYMBOL 15 TC 3 D0 Q0 14 4 Q1 Q2 Q3 CET PE 9 5 D1 Q1 13 D2 Q2 12 6 D3 Q3 11 PE CEP CET CP MR SV00569 7 10 2 1 PIN DESCRIPTION PIN NUMBER 1 2 3, 4, 5, 6 7 8 9 10 14, 13, 12, 11 15 16 SYMBOL MR FUNCTION Asynchronous master reset (active LOW) Clock input (LOW-to-HIGH, edge-triggered) Data inputs Count enable inputs Ground (0 V) Parallel enable input (active LOW) Count enable carry input Flip-flop outputs Terminal count output Positive supply voltage Q0 14 Q1 Q2 13 12 Q3 11 2 CP 1 MR 10 CET 7 CEP BINARY COUNTER SV00570 FUNCTIONAL DIAGRAM 3 D0 9 PE PARALLEL LOAD CIRCUITRY 4 5 6 D3 CP D0 to D3 CEP GND PE CET Q0 to Q3 TC VCC D1 D2 TC 15 SV00572 LOGIC SYMBOL (IEEE/IEC) 1 9 7 10 2 3 1, 2D 4 5 6 CTR4 R M1 G3 G4 C2/1,3,4+ 14 13 12 11 15 4CT = 15 SV00571 1998 Apr 30 3 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; synchronous reset 74LV163 FUNCTION TABLE INPUTS OPERATING MODES MODES Reset (clear) Parallel load load Count Hold (do nothing) (do nothing) MR l h h h h h CP ↑ ↑ ↑ ↑ X X CEP X X X h I X CET X X X h X I PE X I I h h h Dn X I h X X X Qn L L H Count qn qn OUTPUTS TC L L * * * L NOTES: * = The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH) H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level I = LOW voltage level level one set-up time prior to the LOW-to-HIGH clock transition q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition X = don’t care ↑ = LOW-to-HIGH clock transition STATE DIAGRAM 0 1 2 3 4 TYPICAL TIMING SEQUENCE MR PE 15 5 D0 D1 14 6 D2 D3 CP 13 7 CEP CET 12 11 10 9 8 Q0 Q1 Q2 Q3 TC 12 13 14 15 0 1 2 inhibit SV00573 reset preset count Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, one and two; inhibit SV00582 1998 Apr 30 4 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; synchronous reset 74LV163 LOGIC DIAGRAM D0 D1 D2 D3 CET CEP PE MR FF0 DQ FF1 DQ CP FF2 DQ CP FF3 DQ CP CP CP Q Q Q Q Q0 Q1 Q2 Q3 TC SV00583 1998 Apr 30 5 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; synchronous reset 74LV163 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO Tamb tr, tf PARAMETER DC supply voltage Input voltage Output voltage Operating ambient temperature range in free air See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V CONDITIONS See Note 1 MIN 1.0 0 0 –40 –40 – – – – – – TYP 3.3 – – MAX 3.6 VCC VCC +85 +125 500 200 100 UNIT V V V °C ns/V Input rise and fall times NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 3.6V. ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). SYMBOL VCC "IIK "IOK "IO "IGND, "ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC output diode current DC output source or sink current – standard outputs DC VCC or GND current for types with – standard outputs Storage temperature range Power dissipation per package – plastic DIL – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) for temperature range: –40 to +125°C above +70°C derate linearly with 12 mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K VI < –0.5 or VI > VCC + 0.5V VO < –0.5 or VO > VCC + 0.5V –0.5V < VO < VCC + 0.5V CONDITIONS RATING –0.5 to +4.6 20 50 25 UNIT V mA mA mA 50 –65 to +150 750 500 400 mA °C mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Apr 30 6 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; synchronous reset 74LV163 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VCC = 1.2 V VIH HIGH l level I l Input t voltage VCC = 2.0 V VCC = 2.7 to 3.6 V VCC = 1.2 V VIL LOW l level I l Input t voltage VCC = 2.0 V VCC = 2.7 to 3.6 V VCC = 1.2 V; VI = VIH or VIL; –IO = 100µA VO OH HIGH level output voltage; all outputs VCC = 2.0 V; VI = VIH or VIL; –IO = 100µA VCC = 2.7 V; VI = VIH or VIL; –IO = 100µA VCC = 3.0 V; VI = VIH or VIL; –IO = 100µA VOH HIGH level output voltage; STANDARD outputs VCC = 3.0 V; VI = VIH or VIL; –IO = 6mA VCC = 1.2 V; VI = VIH or VIL; IO = 100µA VO OL LOW level output voltage; all outputs VCC = 2.0 V; VI = VIH or VIL; IO = 100µA VCC = 2.7 V; VI = VIH or VIL; IO = 100µA VCC = 3.0 V; VI = VIH or VIL; IO = 100µA VOL LOW level output voltage; STANDARD outputs Input leakage current Quiescent supply current; MSI Additional quiescent supply current per input VCC = 3.0 V; VI = VIH or VIL; IO = 6mA 1.8 2.5 2.8 2.40 1.2 2.0 2.7 3.0 2.82 0 0 0 0 0.25 0.2 0.2 0.2 0.40 0.2 0.2 0.2 0.50 V V 1.8 2.5 2.8 2.20 V V 0.9 1.4 2.0 0.3 0.6 0.8 -40°C to +85°C TYP1 MAX -40°C to +125°C MIN 0.9 1.4 2.0 0.3 0.6 0.8 V V MAX UNIT II ICC ∆ICC VCC = 3.6 V; VI = VCC or GND VCC = 3.6 V; VI = VCC or GND; IO = 0 VCC = 2.7 V to 3.6 V; VI = VCC – 0.6 V 1.0 20.0 500 1.0 160 850 µA µA µA NOTE: 1. All typical values are measured at Tamb = 25°C. 1998 Apr 30 7 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; synchronous reset 74LV163 AC CHARACTERISTICS GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ SYMBOL PARAMETER WAVEFORM CONDITION VCC(V) 1.2 tPHL/tPLH Propagation delay g y CP to Qn Figures 1 2.0 2.7 3.0 to 3.6 1.2 tPHL/tPLH / Propagation delay g y CP to TC Figures Figures 1 2.0 2.7 3.0 to 3.6 1.2 tPHL/tPLH / Propagation delay g y CET to TC Figures Figures 2 2.0 2.7 3.0 to 3.6 2.0 tw Cl k pulse width idth Clock l or LOW HIGH or LOW Figures 1 2.7 3.0 to 3.6 1.2 tsu Set-up time MR, Dn to CP Figures 3, 4 2.0 2.7 3.0 to 3.6 1.2 tsu Set-up time PE to CP Figures 3 2.0 2.7 3.0 to 3.6 1.2 tsu Set-up time CEP, CET to CP Figures 5 2.0 2.7 3.0 to 3.6 1.2 th Hold time Dn, PE, CEP, CET, PE CEP CET MR to CP Figures 3, 4, 5 2.0 2.7 3.0 to 3.6 2.0 fmax Maximum clock Mi lk pulse frequency frequency Figures 1 2.7 3.0 to 3.6 NOTES: 1. Unless otherwise stated, all typical values are measured at Tamb = 25°C 2. Typical values are measured at VCC = 3.3 V. 0 0 0 14 19 24 22 16 13 22 16 13 22 16 13 34 25 20 MIN LIMITS –40 to +85 °C TYP1 95 32 24 182 115 39 29 222 55 19 14 102 10 8 62 25 9 6 52 30 10 8 62 30 10 8 62 –35 –12 –9 –7 40 58 70 0 0 0 12 16 20 MHz ns 26 19 15 ns 26 19 15 ns 26 19 15 ns 36 26 21 41 30 24 ns 44 33 26 ns 75 55 44 90 66 53 ns 61 45 36 75 55 44 ns MAX –40 to +125 °C MIN MAX UNIT 1998 Apr 30 8 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; synchronous reset 74LV163 AC WAVEFORMS VM = 1.5 V at VCC ≥ 2.7 V; VM = 0.5 × VCC at VCC < 2.7 V; VOL and VOH are the typical output voltage drop that occur with the output load. 1/fmax VI CP INPUT GND tW tPHL VOH Qn, TC OUTPUT VOL VM tPLH The shaded areas indicate when the input is permitted to change for predictable output performance. VM VI CP INPUT GND VM VI MR INPUT GND VM tsu th tsu th SV00584 Figure 4. MR set-up and hold times. SV00576 VI Figure 1. Clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width and the maximum clock frequency. CEP, CET INPUT GND VM tsu th tsu th VI CET INPUT GND tPLH VOH TC OUTPUT VOL VM tPHL VM VI CP INPUT GND The shaded areas indicate when the input is permitted to change for predictable output performance. VM SV00580 Figure 5. CEP and CET set-up and hold times. SV00578 Figure 2. Input (CET) to output (TC) propagation delays and output transition times. TEST CIRCUIT VCC VI PE INPUT GND tsu VI CP INPUT GND tsu VI Dn INPUT GND The shaded areas indicate when the input is permitted to change for predictable output performance. VM th tsu th VM th tsu th VM VI PULSE GENERATOR RT D.U.T. 50pF CL RL = 1KΩ VO Test Circuit for switching times DEFINITIONS RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators. SWITCH POSITION SV00579 TEST Figure 3. Set-up and hold times for input (Dn) and parallel enable input (PE). tPLH/tPHL VCC < 2.7V 2.7–3.6V VI VCC 2.7V SV00901 Figure 6. Load circuitry for switching times. 1998 Apr 30 9 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; synchronous reset 74LV163 DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 1998 Apr 30 10 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; synchronous reset 74LV163 SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 1998 Apr 30 11 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; synchronous reset 74LV163 SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 1998 Apr 30 12 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; synchronous reset 74LV163 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 1998 Apr 30 13 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; synchronous reset 74LV163 DEFINITIONS Data Sheet Identification Objective Specification Product Status Formative or in Design Definition This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Preliminary Specification Preproduction Product Product Specification Full Production Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 © Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04429 Philips Semiconductors 1998 Apr 30 14