HEF40097BT

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF40097B buffers 3-state hex non-inverting buffer Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification 3-state hex non-inverting buffer DESCRIPTION The HEF40097B is a hex non-inverting buffer with 3-state outputs. The 3-state outputs are controlled by two enable inputs (EO4 and EO2). A HIGH on EO4 causes four of the six buffer elements to assume a high impedance or OFF-state, regardless of the other input conditions and a HIGH on EO2 causes the outputs of the remaining two buffer elements to assume a high impedance or OFF-state, regardless of the other input conditions. HEF40097B buffers Fig.2 Pinning diagram. HEF40097BP(N): HEF40097BD(F): HEF40097BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PINNING I1 to I6 EO4, EO2 O1 to O6 buffer inputs enable inputs (active LOW) buffer outputs (active HIGH) Fig.1 Functional diagram. FAMILY DATA, IDD LIMITS category BUFFERS See Family Specifications January 1995 2 Philips Semiconductors Product specification 3-state hex non-inverting buffer HEF40097B buffers Fig.3 Logic diagram. DC CHARACTERISTICS VSS = 0 V Tamb (°C) HEF VDD V 5 10 15 HIGH Output current LOW 5 4,75 10 15 VOH V 4,6 9,5 13,5 2,5 0,4 0,5 1,5 IOL −IOH −IOH VOL V SYMBOL −40 +25 +85 MIN. 0,8 2,5 8,0 2,5 2,3 8,0 16,0 MAX. mA mA mA mA mA mA mA MIN. MAX. MIN. MAX. Output current HIGH 1,2 3,8 12,0 3,8 3,5 12,0 24,0 1,0 3,2 10,0 3,2 2,9 10,0 20,0 Tamb (°C) HEC VDD V 5 10 15 HIGH Output current LOW 5 4,75 10 15 VOH V 4,6 9,5 13,5 2,5 0,4 0,5 1,5 IOL −IOH −IOH VOL V SYMBOL −55 +25 +125 MIN. 0,6 2,1 6,7 2,1 1,9 6,7 13,0 MAX. mA mA mA mA mA mA mA MIN. MAX. MIN. MAX. Output current HIGH 1,25 4,0 12,5 4,0 3,6 12,5 25,0 1,0 3,2 10,0 3,2 2,9 10,0 20,0 January 1995 3 Philips Semiconductors Product specification 3-state hex non-inverting buffer AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Propagation delays In → On HIGH to LOW 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW 10 15 5 10 15 5 LOW to HIGH 3-state propagation delays Output disable times EO2, EO4 → On HIGH 5 10 15 5 LOW Output enable times EO2, EO4 → On HIGH 5 10 15 5 LOW 10 15 tPZL tPZH 75 35 30 95 40 30 150 70 60 190 80 65 ns ns ns ns ns ns 10 15 tPLZ tPHZ 45 35 30 60 35 25 95 70 60 120 70 55 ns ns ns ns ns ns 10 15 tTLH tTHL tPLH tPHL 70 30 25 60 25 20 30 15 10 35 20 15 140 60 50 120 50 40 60 30 20 70 40 30 ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL TYP. MAX. HEF40097B buffers TYPICAL EXTRAPOLATION FORMULA 60 ns + (0,20 ns/pF) CL 26 ns + (0,08 ns/pF) CL 22 ns + (0,06 ns/pF) CL 45 ns + (0,30 ns/pF) CL 19 ns + (0,13 ns/pF) CL 16 ns + (0,09 ns/pF) CL 15 ns + (0,30 ns/pF) CL 10 ns + (0,11 ns/pF) CL 7 ns + (0,07 ns/pF) CL 10 ns + (0,50 ns/pF) CL 8 ns + (0,24 ns/pF) CL 6 ns + (0,18 ns/pF) CL VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (µW) 5 400 fi + ∑ (foCL) × VDD2 25 200 fi + ∑ (foCL) × 96 500 fi + ∑ (foCL) × VDD2 VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load cap. (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 4