HEF40163BP

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF40163B MSI 4-bit synchronous binary counter with synchronous reset Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification 4-bit synchronous binary counter with synchronous reset DESCRIPTION The HEF40163B is a fully synchronous edge-triggered 4-bit binary counter with a clock input (CP), four synchronous parallel data inputs (P0 to P3), four synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP), count enable trickle (CET) and synchronous reset (SR)), buffered outputs from all four bit positions (O0 to O3) and a terminal count output (TC). Operation is fully synchronous and occurs on the LOW to HIGH transition of CP. When PE is LOW, the next LOW to HIGH transition of CP loads data into the counter from P0 to P3. When PE is HIGH, the next LOW to HIGH HEF40163B MSI transition of CP advances the counter to its next state only if both CEP and CET are HIGH; otherwise no change occurs in the state of the counter. TC is HIGH when the state of the counter is 15 (O0 to O3 = HIGH) and when CET is HIGH. A LOW on SR sets all outputs (O0 to O3 and TC) LOW on the next LOW to HIGH transition of CP, independent of the state of all other synchronous mode control inputs (CEP, CET and PE). Multistage synchronous counting is possible without additional components by using a carry look-ahead counting technique; in this case, TC is used to enable successive cascaded stages. CEP, CET, PE and SR must be stable only during the set-up time before the LOW to HIGH transition of CP. Fig.1 Functional diagram. FAMILY DATA, IDD LIMITS category MSI See Family Specifications January 1995 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... January 1995 3 Fig.2 Logic diagram. Philips Semiconductors Product specification 4-bit synchronous binary counter with synchronous reset HEF40163B MSI Philips Semiconductors Product specification 4-bit synchronous binary counter with synchronous reset PINNING PE P0 to P3 CEP CET CP SR O0 to O3 TC Fig.3 Pinning diagram. parallel enable input parallel data inputs HEF40163B MSI count enable parallel input count enable trickle input clock input (LOW to HIGH, edge-triggered) synchronous reset input (active LOW) parallel outputs terminal count output HEF40163BP(N): 16-lead DIL; plastic (SOT38-1) HEF40163BD(F): HEF40163BT(D): 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America SYNCHRONOUS MODE SELECTION SR H H H H L Notes 1. H = HIGH state (the more positive voltage) 2. L = LOW state (the less positive voltage) 3. X = state is immaterial PE L H H H X CEP X L X H X CET X X L H X preset no change no change count reset Note 1. TC = CET ⋅ O0 ⋅ O1 ⋅ O2 ⋅ O3 MODE TERMINAL COUNT GENERATION CET L L H H (O0 ⋅ O1 ⋅ O2 ⋅ O3) L H L H TC L L L H Fig.4 State diagram. January 1995 4 Philips Semiconductors Product specification 4-bit synchronous binary counter with synchronous reset AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (µW) 1 200 fi + ∑ (foCL) × VDD2 5 600 fi + ∑ (foCL) × 16 000 fi + ∑ (foCL) × VDD2 VDD2 where HEF40163B MSI fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Propagation delays CP → On HIGH to LOW 5 10 15 5 LOW to HIGH CP → TC HIGH to LOW 10 15 5 10 15 5 LOW to HIGH CET → TC HIGH to LOW 10 15 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW 10 15 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL tPLH tPHL tPLH tPHL tPLH tPHL 110 45 30 115 45 35 130 55 35 140 55 40 105 50 35 90 35 25 60 30 20 60 30 20 220 90 60 230 95 65 260 105 75 280 115 80 210 100 75 185 70 50 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 83 ns + (0,55 ns/pF) CL 34 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 88 ns + (0,55 ns/pF) CL 34 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 103 ns + (0,55 ns/pF) CL 44 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 113 ns + (0,55 ns/pF) CL 44 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 78 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 63 ns + (0,55 ns/pF) CL 24 ns + (0,23 ns/pF) CL 17 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA January 1995 5 Philips Semiconductors Product specification 4-bit synchronous binary counter with synchronous reset AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Minimum clock pulse width; LOW Set-up times Pn → CP 5 10 15 5 10 15 5 PE → CP 10 15 5 CEP, CET → CP 10 15 5 SR → CP Hold times Pn → CP 10 15 5 10 15 5 PE → CP 10 15 5 CEP, CET → CP 10 15 5 SR → CP Maximum clock pulse frequency 10 15 5 10 15 fmax thold thold thold thold tsu tsu tsu tsu tWCPL SYMBOL MIN. 100 40 30 110 40 30 120 40 25 260 100 70 50 20 15 20 10 5 15 5 5 25 15 10 15 5 5 2,5 7 9 TYP. 50 20 15 55 20 15 60 20 10 130 50 35 25 10 10 −35 −10 −10 −45 −15 −10 −105 −35 −25 −10 −5 0 5 14 18 MAX. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz HEF40163B MSI see also waveforms Figs 5, 6, 7 and 8 January 1995 6 Philips Semiconductors Product specification 4-bit synchronous binary counter with synchronous reset HEF40163B MSI Conditions PE = LOW P0 to P3 = HIGH Fig.5 Waveforms showing set-up and hold times for SR input and minimum CP pulse width. Condition: PE = SR = HIGH. Fig.6 Waveforms showing set-up times and hold times for CEP and CET inputs. January 1995 7 Philips Semiconductors Product specification 4-bit synchronous binary counter with synchronous reset HEF40163B MSI Conditions PE = LOW SR = HIGH Fig.7 Waveforms showing set-up times and hold times for Pn inputs. Condition SR = HIGH Fig.8 Waveforms showing set-up times and hold times for PE input. Note Set-up and hold times are shown as positive values but may be specified as negative values. January 1995 8 Philips Semiconductors Product specification 4-bit synchronous binary counter with synchronous reset HEF40163B MSI Fig.9 Timing diagram. APPLICATION INFORMATION An example of an application for the HEF40163B is: • Programmable binary counter. January 1995 9 Philips Semiconductors Product specification 4-bit synchronous binary counter with synchronous reset HEF40163B MSI NOTE On the TC outputs, glitches can occur during counting. In totally synchronous mode they will not have any adverse affect. However the TC output in asynchronous mode can cause problems. Fig.10 Synchronous multi-stage counting scheme. January 1995 10