PCA9561

INTEGRATED CIRCUITS PCA9561 Quad 6-bit multiplexed I2C EEPROM DIP switch Product data sheet Supersedes data of 2003 Jun 27 2004 May 17 Philips Semiconductors Philips Semiconductors Product data sheet Quad 6-bit multiplexed I2C EEPROM DIP switch PCA9561 FEATURES via I2C-bus • Selection of non-volatile register_n as source to MUX_OUT pins • I2C-bus can override MUX_SELECT pin in selecting output source The PCA9561 typically resides between the CPU and Voltage Regulator Module (VRM) when used for CPU VID (Voltage IDentification code) configuration. It is used to bypass the CPU-defined VID values and provide a different set of VID values to the VRM, if an increase in the CPU voltage is desired. An increase in CPU voltage combined with an increase in CPU frequency leads to a performance boost of up to 7.5%. Lower CPU voltage reduces power consumption. The main advantage of the PCA9561 over older devices, such as the PCA9559 or PCA9560, is that it contains four internal non-volatile EEPROM registers instead of just one or two, allowing five independent settings which allows a more accurate CPU voltage tuning depending on specific applications. The PCA9561 has 2 address pins, allowing up to 4 devices to be placed on the same I2C-bus or SMBus. • 6-bit 5-to-1 multiplexer DIP switch • 4 internal non-volatile registers • Internal non-volatile registers programmable and readable via I2C-bus PIN CONFIGURATION SCL SDA A0 MUX_IN_A MUX_IN_B MUX_IN_C MUX_IN_D MUX_IN_E MUX_IN_F 1 2 3 4 5 6 7 8 9 20 VDD 19 WP 18 A1 17 MUX_OUT_A 16 MUX_OUT_B 15 MUX_OUT_C 14 MUX_OUT_D 13 MUX_OUT_E 12 MUX_OUT_F 11 MUX_SELECT • 6 open drain multiplexed outputs • 400 kHz maximum clock frequency • Operating supply voltage 3.0 V to 3.6 V • 5 V and 2.5 V tolerant inputs/outputs • Useful for Speed Step® configuration of laptop • 2 address pins, allowing up to 4 devices on the I2C-bus • MUX_IN values readable via I2C-bus • ESD protection exceeds 200 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 GND 10 SW00823 PIN DESCRIPTION PIN 1 2 3 4–9 10 11 12–17 18 19 20 SYMBOL I2C SCL Serial I2C SDA A0 MUX_IN_A–F GND MUX_SELECT MUX_OUT_F–A A1 WP VDD FUNCTION I2C-bus clock Serial bi-directional I2C-bus data A0 address External inputs to multiplexer Ground Selects MUX_IN inputs or register contents for MUX_OUT outputs Open drain multiplexed outputs A1 address Non-volatile register write-protect Power supply: +3.0 to +3.6 V • Latch-up testing is done to JESDEC Standard JESD78 which exceeds 100 mA. DESCRIPTION The PCA9561 is a 20-pin CMOS device consisting of four 6-bit non-volatile EEPROM registers, 6 hardware pin inputs and a 6-bit multiplexed output. It is used for DIP switch-free or jumper-less system configuration and supports Mobile and Desktop VID Configuration, where 5 preset values (4 sets of internal non-volatile registers and 1 set of external hardware pins) set processor voltage for operation in various performance or battery conservation sleep modes. The PCA9561 is also useful in server and telecom/networking applications when used to replace DIP switches or jumpers, since the settings can be easily changed via I2C/SMBus without having to power down the equipment to open the cabinet. The non-volatile memory retains the most current setting selected before the power is turned off. ORDERING INFORMATION PACKAGES 20-Pin Plastic SO 20-Pin Plastic TSSOP TEMPERATURE RANGE –40 to +85 °C –40 to +85 °C ORDER CODE PCA9561D PCA9561PW TOPSIDE MARK PCA9561D PCA9561 DRAWING NUMBER SOT163-1 SOT360-1 Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging. ® Speed Step is a registered trademark of Intel Corp. 2004 May 17 2 Philips Semiconductors Product data sheet Quad 6-bit multiplexed I2C EEPROM DIP switch PCA9561 BLOCK DIAGRAM PCA9561 WRITE PROTECT NON-VOLATILE REGISTER 0 6-BIT EEPROM 6 6-BIT 4 TO 1 DEMULTIPLEXER NON-VOLATILE REGISTER 1 6-BIT EEPROM 6 NON-VOLATILE REGISTER 2 6-BIT EEPROM 6 NON-VOLATILE REGISTER 3 6-BIT EEPROM 8 6 A0 A1 SCL SDA INPUT FILTER 2 I C LOGIC 2 6 VDD POWER-ON RESET MUX_OUT_A GND 4 6-BIT 2 TO 1 DEMULTIPLEXER MUX_OUT_B MUX_IN_A MUX_OUT_C MUX_IN_B MUX_OUT_D MUX_IN_C MUX_OUT_E MUX_OUT_F MUX_IN_D 6 MUX_IN_E MUX_IN_F MUX_SELECT SELECT LOGIC SW00842 2004 May 17 3 Philips Semiconductors Product data sheet Quad 6-bit multiplexed I2C EEPROM DIP switch PCA9561 DEVICE ADDRESS Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9561 is shown in Figure 1. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW. The last bit of the slave address byte defines the operation to be performed. When set to logic 1 a read is selected while a logic 0 selects a write operation. CONTROL REGISTER Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9561, which will be stored in the control register. This register can be written and read via the I2C-bus. D7 MSB 1 0 0 1 1 A1 A0 LSB R/W D6 D5 D4 D3 D2 D1 D0 SW00954 Figure 2. Control Register FIXED PROGRAMMABLE SW00955 Figure 1. Slave address CONTROL REGISTER DEFINITION Following the address and acknowledge bit with logic 0 in the read/write bit, the first byte written is the command byte. If the command byte is reserved and therefore not valid, it will not be acknowledged. Only valid command bytes will be acknowledged. Table 1. Register Addresses D7 0 0 0 0 1 D6 0 0 0 0 1 D5 0 0 0 0 1 D4 0 0 0 0 1 D3 0 0 0 0 1 D2 0 0 0 0 1 D1 0 0 1 1 1 D0 0 1 0 1 1 REGISTER NAME EEPROM 0 EEPROM 1 EEPROM 2 EEPROM 3 MUX_IN TYPE Read/Write Read/Write Read/Write Read/Write Read REGISTER FUNCTION EEPROM byte 0 register EEPROM byte 1 register EEPROM byte 2 register EEPROM byte 3 register MUX_IN values register Table 2. Commands D7 1 1 1 1 1 1 D6 1 1 1 1 1 1 D5 1 1 1 1 1 1 D4 1 1 1 1 1 1 D3 1 1 1 1 1 1 D2 0 1 0 1 X X D1 0 0 X X 1 X D0 0 0 1 1 0 1 COMMAND MUX_OUT from EEPROM byte 0 MUX_OUT from EEPROM byte 1 MUX_OUT from EEPROM byte 2 MUX_OUT from EEPROM byte 3 MUX_OUT from MUX_IN MUX_OUT from MUX_SELECT2 NOTE: 1. All other combinations are reserved. 2. MUX_SELECT pins select between MUX_IN and EEPROM to MUX_OUT. 2004 May 17 4 Philips Semiconductors Product data sheet Quad 6-bit multiplexed I2C EEPROM DIP switch PCA9561 REGISTER DESCRIPTION If the command byte is an EEPROM address, the next byte sent will be programmed into that EEPROM address on the following STOP condition, if the WP is logic 0. If more than one byte is sent sequentially, the second byte will be written in the other-volatile register, on the following STOP condition. Up to four bytes can be sent sequentially. If any more data bytes are sent after the second byte, they will not be acknowledged and no bytes will be written to the non-volatile registers. After a byte is read from or written to the EEPROM, the part automatically points to the next non-volatile register. If the command code was FFH, the MUX_IN values are sent with the three MSBs padded with zeroes as shown below. If the command codes was 00H, then the non-volatile register 1 is sent, and if the command code was 01H, then the non-volatile register 1 is sent. EEPROM Byte 0 Register D7 Write Read Default X 0 0 D6 X 0 0 D5 EEPROM 0 Data F EEPROM 0 Data F 0 D4 EEPROM 0 Data E EEPROM 0 Data E 0 D3 EEPROM 0 Data D EEPROM 0 Data D 0 D2 EEPROM 0 Data C EEPROM 0 Data C 0 D1 EEPROM 0 Data B EEPROM 0 Data B 0 D0 EEPROM 0 Data A EEPROM 0 Data A 0 EEPROM Byte 1 Register D7 Write Read Default X 0 0 D6 X 0 0 D5 EEPROM 1 Data F EEPROM 1 Data F 0 D4 EEPROM 1 Data E EEPROM 1 Data E 0 D3 EEPROM 1 Data D EEPROM 1 Data D 0 D2 EEPROM 1 Data C EEPROM 1 Data C 0 D1 EEPROM 1 Data B EEPROM 1 Data B 0 D0 EEPROM 1 Data A EEPROM 1 Data A 0 EEPROM Byte 2 Register D7 Write Read Default X 0 0 D6 X 0 0 D5 EEPROM 2 Data F EEPROM 2 Data F 0 D4 EEPROM 2 Data E EEPROM 2 Data E 0 D3 EEPROM 2 Data D EEPROM 2 Data D 0 D2 EEPROM 2 Data C EEPROM 2 Data C 0 D1 EEPROM 2 Data B EEPROM 2 Data B 0 D0 EEPROM 2 Data A EEPROM 2 Data A 0 EEPROM Byte 3 Register D7 Write Read Default X 0 0 D6 X 0 0 D5 EEPROM 3 Data F EEPROM 3 Data F 0 D4 EEPROM 3 Data E EEPROM 3 Data E 0 D3 EEPROM 3 Data D EEPROM 3 Data D 0 D2 EEPROM 3 Data C EEPROM 3 Data C 0 D1 EEPROM 3 Data B EEPROM 3 Data B 0 D0 EEPROM 3 Data A EEPROM 3 Data A 0 MUX_IN Register D7 Read 0 D6 0 D5 MUX_IN Data F D4 MUX_IN Data E D3 MUX_IN Data D D2 MUX_IN Data C D1 MUX_IN Data B D0 MUX_IN Data A If the command byte is a MUX command byte, any additional data bytes sent after the MUX command code will not be acknowledged. If the read/write bit in the address is a logic 1, then a read operation follows and the data sent out depends on the previously stored command code. The MUX_SELECT_1 pin can function as the over-ride pin as on the PCA9559 if the non-volatile register 1 is left at all 0s. The NON_MUXED_OUT pin is a latched output. It is latched when MUX_SELECT_0 = 1. It is transparent when the MUX_SELECT_0 = 0. The data sent out on the NON_MUXED_OUT output is the 6th most significant bit of the non-volatile register. Whether this comes from the non-volatile register 0 or non-volatile register 1 depends on the command code or the external mux-select pins. After a valid I2C write operation to the EEPROM, the part cannot be addressed via the I2C for 3.6 ms. If the part is addressed prior to this time, the part will not acknowledge its address. NOTE: 1. To ensure data integrity, the non-volatile register must be internally write protected when VDD to the I2C-bus is powered down or VDD to the component is dropped below normal operating levels. 2004 May 17 5 Philips Semiconductors Product data sheet Quad 6-bit multiplexed I2C EEPROM DIP switch PCA9561 EXTERNAL CONTROL SIGNALS The Write Protect (WP) input is used to control the ability to write the content of the non-volatile registers. If the WP signal is logic 0, the I2C-bus will be able to write the contents of the non-volatile registers. If the WP signal is logic 1, data will not be allowed to be written into the non-volatile registers. In this case, the slave address and the command code will be acknowledged but the following data bytes will not be acknowledged and the EEPROM is not updated. The factory default for the contents of the non-volatile register are all logic 0. These stored values can be read or written using the I2C-bus (described in the next section). The WP, MUX_IN*, and MUX_SELECT signals have internal pull-up resistors. See the DC and AC Characteristics for hysteresis and signal spike suppression figures. Function Table1 WP 0 1 X X MUX_SELECT X X 0 1 COMMANDS Write to the non-volatile registers through I2C-bus allowed Write to the non-volatile registers through I2C-bus not allowed MUX_OUT from EEPROM byte 0–3 (EEPROM selected through I2C – see Table 2) MUX_OUT from MUX_IN inputs NOTE: 1. This table is valid when not overridden by I2C control register. POWER-ON RESET (POR) When power is applied to VDD, an internal power-on reset holds the PCA9561 in a reset state until VDD has reached VPOR. At that point, the reset condition is released and the PCA9561 volatile registers and state machine will initialize to their default states. The MUX_OUT pin values depend on the MUX_SELECT logic level: – if MUX_SELECT = 0, the MUX_OUT pin output values will equal the previously stored EEPROM byte 0 values regardless of the last non-volative EEPROM byte selected by the command byte prior to power down. – if MUX_SELECT = 1, the MUX_OUT output values will equal the MUX_IN pin input values as shown in the Function Table. 2004 May 17 6 Philips Semiconductors Product data sheet Quad 6-bit multiplexed I2C EEPROM DIP switch PCA9561 CHARACTERISTICS OF THE I2C-BUS The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 3). SDA SCL data line stable; data valid change of data allowed SW00363 Figure 3. Bit transfer Start and stop conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Figure 4). System configuration A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device initiates a transfer is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 5). SDA SDA SCL S START condition P STOP condition SCL SW00365 Figure 4. Definition of start and stop conditions SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C MULTIPLEXER SLAVE SW00366 Figure 5. System configuration 2004 May 17 7 Philips Semiconductors Product data sheet Quad 6-bit multiplexed I2C EEPROM DIP switch PCA9561 Acknowledge The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold times must be taken into account. A receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition. DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition 1 2 8 9 clock pulse for acknowledgement SW00368 Figure 6. Acknowledgement on the I2C-bus 2004 May 17 8 Philips Semiconductors Product data sheet Quad 6-bit multiplexed I2C EEPROM DIP switch PCA9561 Bus Transactions Data is transmitted to the PCA9561 registers using Write Byte transfers (see Figures 7 and 8). Data is read from the PCA9561 registers using Read and Receive Byte transfers (see Figure 9). slave address control register write on EEPROM byte 0 EEPROM byte 0 data S 1 0 0 1 1 A1 A0 0 R/W A 0 0 0 0 0 0 0 0 A X X D5 D4 D3 D2 D1 D0 A P stop condition start condition acknowledge from slave acknowledge from slave acknowledge from slave SW00956 Figure 7. WRITE on 1 EEPROM — assuming WP = 0 control register write on EEPROM byte 0 slave address EEPROM byte 0 data EEPROM byte 1 data S 1 0 0 1 1 A1 A0 0 R/W A 0 0 0 0 0 0 0 0 A X X D5 D4 D3 D2 D1 D0 A X X D5 D4 D3 D2 D1 D0 A P start condition acknowledge from slave acknowledge from slave stop condition SW00957 Figure 8. WRITE on 2 EEPROMs — assuming WP = 0 control register read MUX_IN values slave address slave address data from MUX_IN S 1 0 0 1 1 A1 A0 0 R/W A 1 1 1 1 1 1 1 1 A S 1 0 0 1 1 A1 A0 1 R/W A 0 0 0 4 3 2 1 0 NA P restart start condition acknowledge from master acknowledge from master acknowledge from master no acknowledge from master stop condition SW00958 Figure 9. READ MUX_IN register 2004 May 17 9 Philips Semiconductors Product data sheet Quad 6-bit multiplexed I2C EEPROM DIP switch PCA9561 ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). SYMBOL VDD VI VOUT Tstg PARAMETER DC supply voltage DC input voltage DC output voltage Storage temperature range Note 3 Note 3 CONDITIONS RATING –0.5 to +4.0 –1.5 to +5.5 –0.5 to +5.5 –60 to +150 UNIT V V V °C NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C. 3. The maximum input or output voltage is the lesser of 5.5 V or VDD + 4.0 V, except for very short (e.g., system start-up or shut-down) durations. RECOMMENDED OPERATING CONDITIONS SYMBOL VDD VIL VIH VO OL DC supply voltage LOW-level input voltage HIGH-level input voltage LOW-level output voltage level output voltage SCL, SDA SCL, SDA SCL, SDA SDA MUX_IN, MUX_SELECT_0 MUX_SELECT_1 MUX_IN, MUX_SELECT_0 MUX_SELECT_1 MUX_OUT MUX_OUT PARAMETER CONDITIONS — IOL= 3 mA IOL= 3 mA IOL= 3 mA IOL= 6 mA — LIMITS MIN 3.0 –0.5 2.7 — — –0.5 MAX 3.6 0.9 5.5 1 0.4 0.6 0.8 UNIT V V V V V V VIL LOW-level input voltage VIH IOL IOH dt/dv Tamb HIGH-level input voltage LOW-level output current HIGH-level output current Input transition rise or fall time Operating temperature — — — — — 2.0 — — 0 –40 5.5 1 8 100 10 85 V mA µA ns/V °C NOTES: 1. The maximum input voltage is the lesser of 5.5 V or VDD + 4.0 V, except for very short (e.g., system start-up or shut-down) durations. 2004 May 17 10 Philips Semiconductors Product data sheet Quad 6-bit multiplexed I2C EEPROM DIP switch PCA9561 DC CHARACTERISTICS LIMITS SYMBOL Supply VDD IDDL IDDH VPOR VIL VIH IOL IOL IIH IIL CI IIH IIL CI Mux A → F IIH IIL CI IIH IIL CI MUX_OUT VOL VOL IOH LOW-level output voltage LOW-level output voltage HIGH-level output current IOL = 100 µA IOL = 4 mA VOH = VDD — — — — — — 0.4 0.7 100 V V µA Leakage current HIGH Input current LOW Input capacitance VI = VDD VDD = 3.6 V; VI = GND –1 –20 — — — 2.5 1 –50 5 µA µA pF µA µA pF Supply voltage Supply current Supply current Power-on reset voltage Operating mode ALL inputs = 0 V Operating mode ALL inputs = VDD no load; VI = VDD or GND 3 — — — — 0.6 — 2.3 3.6 1 600 2.7 V mA µA V PARAMETER TEST CONDITION CONDITION MIN. TYP. MAX. UNIT Input SCL; Input/Output SDA LOW-level input voltage HIGH-level input voltage LOW-level output current LOW-level output current Leakage current HIGH Leakage current LOW Input capacitance VOL = 0.4 V VOL = 0.6 V VI = VDD VI = GND –0.5 2 3 6 –1 –1 — — — — — — — 3 0.8 5.5 — — 1 1 6 1 V V mA mA µA µA pF µA µA pF WP and MUX_SELECT Leakage current HIGH Input current LOW Input capacitance VI = VDD VDD = 3.6 V; VI = GND –1 –20 — — — 2.5 1 –50 5 A0 and A1 Inputs Leakage current HIGH Input current LOW Input capacitance VI = VDD VDD = 3.6 V; VI = GND –1 –20 — — — 2 1 –50 4 NOTE: 1. The maximum input voltage is the lesser of 5.5 V or VDD + 4.0 V, except for very short (e.g., system start-up or shut-down) durations. NON-VOLATILE STORAGE SPECIFICATIONS PARAMETER Memory cell data retention Number of memory cell write cycles SPECIFICATION 10 years min 100,000 cycles min Application Note AN250 I 2C DIP Switch provides additional information on memory cell data retention and the minimum number of write cycles. 2004 May 17 11 Philips Semiconductors Product data sheet Quad 6-bit multiplexed I2C EEPROM DIP switch PCA9561 AC CHARACTERISTICS SYMBOL MUX_IN ⇒ MUX_OUT tPLH tPHL tPLH tPHL tR tF CL LOW-to-HIGH transition time HIGH-to-LOW transition time LOW-to-HIGH transition time HIGH-to-LOW transition time Output rise time Output fall time Test load capacitance on outputs — — — — 1.0 1.0 — 28 8 30 10 — — — 40 15 43 15 3 3 — ns ns ns ns ns/V ns/V pF PARAMETER LIMITS MIN. TYP. MAX. UNIT Select ⇒ MUX_OUT SYMBOL fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO Cb tSP SCL clock frequency PARAMETER STANDARD-MODE I2C-BUS MIN 0 4.7 4.0 4.7 4.0 4.7 01 250 — — 4.0 — — MAX 100 — — — — — 3.45 — 1000 300 — 400 50 FAST-MODE I2C-BUS MIN 0 1.3 0.6 1.3 0.6 0.6 01 100 20 + 0.1Cb2 20 + 0.1Cb2 0.6 — — MAX 400 — — — — — 0.9 — 300 300 — 400 50 UNIT kHz µs µs µs µs µs µs ns ns ns µs pF ns Bus free time between a STOP and START condition Hold time (repeated) START condition After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Capacitive load for each bus line Pulse width of spikes which must be suppressed by the input filter NOTES: 1. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. 2. Cb = total capacitance of one bus line in pF. SDA tBUF tLOW tR tF tHD;STA tSP SCL tHD;STA P S tHD;DAT tHIGH tSU;DAT Sr tSU;STA tSU;STO P SU00645 Figure 10. Definition of timing 2004 May 17 12 Philips Semiconductors Product data sheet Quad 6-bit multiplexed I2C EEPROM DIP switch PCA9561 MUX INPUT VM VM VCC VO tPHL tPLZ VO PULSE GENERATOR VIN D.U.T. RT VOUT RL MUX OUTPUT VM VOL + 0.3 V VOL CL SW00500 Test Circuit for Open Drain Outputs Figure 11. Open drain output enable and disable times DEFINITIONS RL = Load resistor; 1 kΩ CL = Load capacitance includes jig and probe capacitance; 10 pF RT = Termination resistance should be equal to ZOUT of pulse generators. SW00510 Figure 12. Test circuit 2004 May 17 13 Philips Semiconductors Product data sheet Quad 6-bit multiplexed I2C EEPROM DIP switch PCA9561 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 2004 May 17 14 Philips Semiconductors Product data sheet Quad 6-bit multiplexed I2C EEPROM DIP switch PCA9561 TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 2004 May 17 15 Philips Semiconductors Product data sheet Quad 6-bit multiplexed I2C EEPROM DIP switch PCA9561 REVISION HISTORY Rev _3 Date 20040517 Description Product data (9397 750 13153). Supersedes data of 2003 Jun 27 (9397 750 11677). Modifications: • Features section, 9th bullet: from “inputs” to “inputs/outputs” • Absolute maximum ratings table: VDD, VIN, and VOUT limits modified. Note 3 re-written. • Recommended operating conditions – VIH max. (on SCL, SDA) changed from 4.0 V to 5.5 V (with Note 1 added). – VIH max. (on MUX_IN, MUX_SELECT_0, MUX_SELECT_1) changed from 4.0 V to 5.5 V (with Note 1 added). • DC characteristics table – Input SCL: Input/Output SDA; VIH parameter max. limit modified, and Note 1 added. – Mux A → F: Symbols IIH and IIL : change the Unit from ‘mA’ to ‘µA’. _2 _1 20030627 20020524 Product data (9397 750 11677); ECN 853-2348 29936 dated 19 May 2003. Supersedes data of 2002 May 24 (9397 750 09888). Product data (9397 750 09888); ECN 853-2348 28311 of 24 May 2002. 2004 May 17 16 Philips Semiconductors Product data sheet Quad 6-bit multiplexed I2C EEPROM DIP switch PCA9561 Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011. Data sheet status Level I Data sheet status [1] Objective data sheet Product status [2] [3] Development Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data sheet Qualification III Product data sheet Production [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2004 All rights reserved. Printed in U.S.A. Date of release: 05-04 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. Document order number: 9397 750 13153 Philips Semiconductors 2004 May 17 17