SA1630BE

INTEGRATED CIRCUITS SA1630 IF quadrature transceiver Product specification IC17 Data Handbook 1998 Jul 21 Philips Semiconductors Philips Semiconductors Product specification IF quadrature transceiver SA1630 DESCRIPTION The SA1630 is a 70–400 MHz I/Q transceiver for wireless LAN. The Receive Path contains a digitally gain controlled linear IF amplifier, a pair of quadrature down conversion mixers and a pair of baseband amplifiers. The transmit path contains a pair of quadrature up conversion mixers that transposes a quadrature baseband input signal up to IF frequency. An external VCO signal is divided internally and provides quadrature local oscillator signals for the mixers. Another divider chain, reference divider and phase detector are provided to avoid the need for an external synthesizer. To keep power consumption to a minimum the transmit, receive and local oscillator functions can be powered down under digital control. • Internal IF PLL for synthesizing the local IF oscillator signal. • Bandwidth of baseband Tx inputs is 20 MHz and that of baseband Rx outputs is 8.5MHz. • Designed for IEEE 802.11 wireless LAN using Direct Sequence Spread Spectrum modulation. • Control registers power up in a default state. • Only a standard reference input frequency required, choice of 8, 11, 22 or 44 MHz. FEATURES • Low supply voltage operation of 2.7V for main chip and 2.9V for charge pump. • Digital gain control of 70 dB in steps of 2 dB. • Rx Baseband amplifiers are capable of driving 1kW ||15pF • Rx Baseband o/p’s clamp symmetrically, above 1Vp–p in order to prevent dc bias shift under overdrive conditions. • Low current consumption: 33.5 mA in RX, 26.5 mA in TX, typical at 3V. • Package: LQFP–48, PCMCIA compatible APPLICATIONS • Flexible power up/down options. • Optional 2.5V regulated reference voltage available during transmit. • Input IF frequency range of 70–400 MHz. IFOUT TxIFOUTX • IF circuitry for IEEE 802.11 DSSS wireless LAN. • Applications for high speed wireless data. BE Package GNDTxRx GNDRx VCC TxRx V REF 2.5 RxIF INX GNDRX GNDRx RxIF IN GNDTxRx I REF 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 Q_RxOUT I_RXOUT Q_Tx INX GND_BB GND_BB VCC _DIG VCC _BB I_Tx_INX GNDDIG I_Tx_IN Q_Tx IN Tx_ON Tx 48 47 46 45 44 43 42 VCC Rx 1 GNDRX 2 VCC Rx 3 PLL_ON 4 Rx_ON GNDHDR GC0 GC1 GC2 5 6 7 8 9 41 40 39 38 37 GNDCP CP V CC CP DATA CLOCK STROBE LOCK LO_INX LO_IN GNDRx CLK IN CLK INX GC3 10 GC4 11 GC5 12 SR01549 Figure 1. Pin Configuration ORDERING INFORMATION DESCRIPTION 48–Pin Plastic Low Profile Quad Flat package TEMPERATURE RANGE –40 to +85°C ORDER CODE SA1630BE DWG # SOT313–2 1998 Jul 21 2 853–2049 19763 Philips Semiconductors Product specification IF quadrature transceiver SA1630 (4) (38) (1,3) (39) PLL–ON VREF 2.5 VCCRX VCCTXRX GND_BB (13, 14) (15) (5) RXON MODE CONTROL 2.5V REGULATOR VCC_BB (23) TxON I_Tx IN (18) I_Tx INX (19) (43) (42) TxIFOUT TxIFOUTX Q_Tx IN (20) Q_Tx INX (21) (7) (8) (9) GC0 GC1 GC2 I_RxOUT 1 (46) RxIFIN (45) RxIFINX (17) (10) GC3 (11) GC4 (12) GC5 (28) (29) (34) LO IN LO INX Q_RxOUT 1 (16) ÷2 BUFFERS VCCCP DAC (35) (37) (30) CP IREF LOCK CHARGE PUMP ÷N PHASE DETECTOR SYNTH REGISTER GND HDR GNDTXRX (6) (40, 41) GNDCP (36) ÷ 8, 11, 22, 44 TEST REGISTER SERIAL INPUT CLKIN (26) CLKINX (25) VCCDIG (22) GND DIG (24) DATA CLOCK STROBE (33) (32) (31) GND RX (2, 27, 44, 47, 48) SR01551 Figure 2. Block Diagram 3 1998 Jul 21 Philips Semiconductors Product specification IF quadrature transceiver SA1630 PIN DESCRIPTIONS Pin No. 1, 3 2, 27, 44,47, 48 4 5 6 7 8 9 10 11 12 13, 14 15 16 17 18 19 20 21 22 23 24 25 26 28 29 30 31 32 33 34 35 36 37 38 39 40,41 42 43 45 46 Pin Name VCCRx GNDRx PLL_ON Rx_ON GNDHDR GCO GC1 GC2 GC3 GC4 GC5 GND_BB VCC_BB Q_RXOUT I_RxOUT I_Tx IN I_Tx INX Q_Tx IN Q_Tx INX VCC_DIG Tx_ON GNDDIG CLK INX CLK IN LO_IN LO INX LOCK STROBE CLOCK DATA VCCCP CP GNDCP IREF VREF2.5 VCCTxRx GNDTxRx TxIFOUTX TxIFOUT RxIF INX RxIF IN Supply Pin for Rx section (IF circuits) Ground pins for Rx section (IF circuits) One of the three digital CMOS logic control inputs to the mode control section One of the three digital CMOS logic control inputs to the mode control section Substrate ground Control bit 0 for IF VGA gain control, CMOS input Control bit 1 for IF VGA gain control, CMOS input Control bit 2 for IF VGA gain control, CMOS input Control bit 3 for IF VGA gain control, CMOS input Control bit 4 for IF VGA gain control, CMOS input Control bit 5 for IF VGA gain control, CMOS input Ground pin for Rx baseband circuits Supply Pin for Rx Baseband circuits Quadrature–phase Rx baseband output, single–ended In–phase Rx baseband output, single–ended In–phase differential Tx baseband input, positive In–phase differential Tx baseband input, negative Quadrature differential Tx baseband input, positive Quadrature differential Tx baseband input, negative Supply for digital circuits One of the Three digital CMOS logic control inputs to the mode control section Digital ground Differential reference input for synthesizer, negative Differential reference input for synthesizer, positive Differential LO input,positive Differential LO input, negative Test control output and synthesizer lock indicator Serial bus strobe input Serial bus clock input Serial bus data input Supply for charge pump circuits Charge pump output Ground for charge pump circuits Charge pump reference current Reference voltage of 2.5V available for external use Supply pin used by Tx circuits Ground pins used by Tx circuits Differential transmitter IF output (open collector), positive Differential transmitter IF output (open collector), negative Differential receiver IF input, negative Differential receiver IF input, positive Description 1998 Jul 21 4 Philips Semiconductors Product specification IF quadrature transceiver SA1630 ABSOLUTE MAXIMUM RATINGS SYMBOL VCCXX VIN ∆VG PD TJMAX PMAX TSTG Supply voltages Voltage applied to any other pin Any GND pin to any other GND pin Power dissipation, TA = 25°C (still air) Maximum operating junction temperature Maximum power input/output Storage temperature range PARAMETER RATING -0.3 to +6.0 -0.3 to VCCXX+0.3 0 300 150 +20 –65 to +150 UNITS V V V mW °C dBm °C RECOMMENDED OPERATING CONDITIONS SYMBOL VCCXXXX VCCCP TA Supply voltages: Charge pump supply voltage Operating ambient temperature range PARAMETER RATING 2.7 to 3.6 2.7 to 3.6 -40 to +85 UNITS V V °C NOTES: 1. There are no ESD protection diodes between pins 42, 43 and VCC to allow higher AC peak voltage. The ESD protection level has thus been reduced. Proper ESD handling precautions should be followed. MODE CONTROL NO: 1 2 3 4 5 ’0’ – LOGIC LOW ’1’ – LOGIC HIGH ’X’ – DON’T CARE PLL_ON 0 1 1 1 1 RX_ON X 0 1 1 0 TX_ON X 1 1 0 0 STATE DESCRIPTION SLEEP mode Synthesizer ON, Rx STDBY, Tx OFF Synthesizer ON, Rx STDBY, Tx ON Synthesizer ON, Rx ON, Tx OFF Synthesizer ON, Rx OFF, Tx ON MODE SLEEP WAIT TRANSMIT RECEIVE TRANSMIT 2.5V REF Off Off On Off Off 1. Sleep mode (PLL OFF, Rx OFF, Tx OFF) In this mode everything is switched off except the 3–wire digital bus. As long as the digital supply is still on, the programmed values are active and the 3–wire bus will continue to be programmable. except for the bias and baseband circuits needed to hold the baseband output voltages in the active state. This mode is useful if the Rx baseband outputs are AC coupled via a large capacitor and the application demands quick turn–on for the Rx, from Tx. 2. Wait Mode (Tx Off, Rx Standby) PLL is on. Receiver is in the reduced current standby mode and the transmitter is completely switched off. This mode maybe useful if the PLL is to be kept on and is waiting for a quick turn–on to either transmit or receive modes, especially when Rx outputs are AC coupled. 4. Receive Mode (Tx Off) The Transmitter is completely shut–off. The PLL and receiver sections are operating. 5. Transmit Mode (Rx OFF) PLL and Transmit sections are on. However, the Receiver is completely shut–down. This mode is useful if the Rx baseband outputs are DC coupled to the external world. 3. Transmit mode (Rx standby) The PLL and transmitter are on. The receive section is in a reduced current mode wherein most of the Rx circuitry is powered down 1998 Jul 21 5 Philips Semiconductors Product specification IF quadrature transceiver SA1630 RX VGA CONTROL TABLE GC5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 GC4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 GC2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 GC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 GC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 DECIMAL NUMBER 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 23 24 25 26 27 28 29 30 31 52 53 54 55 56 57 58 59 60 61 62 REDUCTION FROM Gmax 0 –2 –4 –6 –8 –10 –12 –14 –16 –18 –20 –22 –24 –26 –28 –30 –32 –34 –36 –38 –40 –42 –44 –46 –48 –50 –52 –54 –56 –58 –60 –62 –64 –66 –68 –70 1998 Jul 21 6 Philips Semiconductors Product specification IF quadrature transceiver SA1630 DC ELECTRICAL CHARACTERISTICS VCCXXX=+3V; VEEXXX = 0V; TA=25°C, unless otherwise stated. SYMBOL ICC–4 PARAMETER Supply Current, Receive (mode #4) TEST CONDITION CONDITION PLL_ON=Rx_ON=Hi Tx_ON = Low LIMITS MIN TYP 33.5 MAX 41.5 UNITS mA ICC–2 Supply Current, Wait (mode #2) Wait mode (2) PLL_ON = Hi Tx_ON = Hi Rx_ON = Low PLL_ON = TX_ON = Hi RX_ON = Hi PLL_ON = Low RX_ON = DC TX_ON = DC PLL_ON = Hi TX_ON = RX_ON = Low Load = 1.5mA ∆I = 1.4 to 1.6mA 2.0 0 17 23 mA ICC–3 ICC–1 ICC–5 VREF_2.5 ZOUT_VREF VIH VIL II CI VOH VOL VIH VIL II Supply Current, Transmit (mode #3) Supply Current, Sleep mode (mode #1) Supply current transmit (mode 5) Reference voltage (mode 3, enabled) Output impedance of reference voltage Input logic 1 level Input logic 0 level Input logic current Input logic capacitance Output logic 1 level Output logic 0 level Input logic 1 level Input logic 0 level Input logic current 26.5 0.012 22 2.5 15 34.5 0.1 28.5 mA mA mA V W CMOS LOGIC INPUTS (DATA, CLOCK, STROBE) VCCD 0.8 1 4 IO = –2mA IO = 2mA 2.0 V V µA pF V CMOS Logic output (LOCK) VCCD–0.4 0.4 VCCTXRX 0.8 1 V V V µA CMOS Logic Inputs (PLL_ON, RX_ON, TX_ON) 0 1998 Jul 21 7 Philips Semiconductors Product specification IF quadrature transceiver SA1630 AC ELECTRICAL CHARACTERISTICS IF TRANSMIT MODULATOR (Mode #3, Tx ON Rx Standby) VCCXXX = +3V; GNDXXX = 0V; LO_in = 100 mV peak at 704 MHz, CLKin = 100mV peak at 22 MHz, Tamb = 25°C, unless otherwise stated. SYMBOL BW4,5 VIN THD_3 RINTx CINTx4 PARAMETER Input modulation bandwidth Input signal amplitude, Differential1 Third harmonic distortion5 Input resistance Input Capacitance Minimum Tx output DC voltage IO DC Mean output DC current Output current DC offset4 Output current available2 Output differential voltage1,2 CS SBS nG4 tON 4 TEST CONDITION CONDITION 500 ohms source impedance Voltage common mode = 1 to 2V Input signal amplitude = 1 VPP, 8 MHz, VCM = 1.5 Between pins I_TXIN, I_TXINX Q_TXIN, Q_TXINX Between pins I_TXIN, I_TXINX Q_TXIN, Q_TXINX VIN = IVPP VCMI = VCMQ = VCC/2 At TXIFOUT and TXIFOUTX Mismatch at TXIFOUT and TXIFOUTX At TXIFOUT and TXIFOUTX 400 Ω tuned load2 Differential output fOUT = 352 MHz offset = 10 MHz TX_ON, RX_ON transition to transmit signal at 90% level TX_ON, RX_ON transition to transmit signal at 10% level LIMITS MIN 22 1 –55 98 2 VCC–0.3 2 0.475 190 30 TYP MAX UNITS MHz Vpp –45 dBc kΩ pF V 2.75 40 mA µA mA rms mV rms dBc dBc dBc/Hz Carrier suppression1,3 SB Suppression 1,3 Noise floor Gain stability6 Turn–on time Turn–off time 36 47 156 0.5 4 4 2.0 35 dB µs µs TOFF4 NOTES: 1. Tx inputs are differential sine wave, 0.5 V peak, with quadrature relationship between I and Q Tx input. The output spectrum will be SSB. The tone is at a frequency of 1 MHz. 2. The output current in each arm is the same but 180 degrees out of phase with each other. Also the tuned load of 400 ohms differential, is assumed. The power delivered to 400 ohms will be –10.4 dBm (typ.). The output current measurement is indirect based on output power measurement according to P = 10 log I2rms (400W)/IMV. See typical performance characteristic curve. 3. This is measured with respect to the SSB output. 4. Guaranteed by design and or characterization but not final tested. 5. The input bandwidth may be verified by measuring the output THD and signal level using a DSB spectrum where I = Q. 6. Measured over temperature and supply. 1998 Jul 21 8 Philips Semiconductors Product specification IF quadrature transceiver SA1630 AC ELECTRICAL CHARACTERISTICS IF RECEIVER DEMODULATOR (Mode #4, Rx_ON, Tx_OFF) VCCXXX = +3V = GNDXXX = 0V; LO IN = 100 mVpeak at 704 MHz, CLKIN = 100mVpeak, at 22 MHz, Ta = 25°C, unless otherwise stated. SYMBOL RInRx VG NF PARAMETER Differential input impedance Voltage gain Input noise AGC range AGC step size AGC differential error AGC settling time Channel matching gain phase Output DC offset between IRx Out and QRx Out OVS Output voltage swing Output voltage swing Output common mode voltage Output impedance THD3 BW5 tON 4 TEST CONDITION CONDITION fIN = 352 MHz LIMITS MIN 81 67 TYP 6.6K||0.7 88 7.5 70 2 2 MAX UNITS kΩ||pF dB dB dB dB dB nS dB deg mV Vp–p V Ω % AGC at maximum gain VGA at maximum gain figure1 any AGC step 0.1 0.25 Maximum Gain, Output at 1 MHz AGC GMIN, into load2 AGC Gain, except GMIN 0.9 1.0 6 1.15 1.4 1.9 7 Max. Gain, rated output at 1 MHz 7 RX_ON, TX_ON transition to baseband signal out RX_ON, TX_ON transition to no baseband signal out 3 8.5 200 Total Harmonic Distortion Rx Bandwidth Turn–on time Turn–off time 10 2 2 MHz µs µs tOFF4 NOTES: 1. The Receive input is to be differential (using a balun or a differential source such as a differential SAW filter) and matched to external generator’s impedance (ex: 50 ohms). The balun may or may not provide any impedance transformation depending on availability. An external L–C matching circuit can provide the rest of the impedance transformation and absorb the input capacitance of the receiver input. Such a differential input scheme is mandatory to avoid pickup, and keep the noise figure low. A shunt resistor across the input (value TBD) will be used to set the input impedance as a compromise between the matching ease in production versus the noise figure of the receiver. The system board layout has to keep the isolation between the receive inputs and the LO signal as high as possible. Otherwise the LO leakage will overload the receiver. 2. The load is 1000 ohms in parallel with 15pF of capacitor. 3. THD is total harmonic distortion. We measure harmonics 2, 3, 4. 4. Guaranteed by design. 5. 3dB bandwidth relative to a passband measurement taken at 1MHz. 1998 Jul 21 9 Philips Semiconductors Product specification IF quadrature transceiver SA1630 AC ELECTRICAL CHARACTERISTICS IF SYNTHESIZER VCCXXX = RX_ON = TX_ON = PLL_ON = +3V, VEEXXX = 0V; LO_IN = 100 mVpeak at 704 MHz, CLKIN = 100mVpeak at 22 MHz, Ta = 25°C, unless otherwise stated. SYMBOL fLO ZLOIN VLOIN PARAMETER Local oscillator input frequency range3 Differential input impedance LO input sensitivity4 Programmable divider: division range step size fCLK ZCLKIN Reference clock maximum frequency3 Differential input impedance CLK input sensitivity4 fCMIN fCMAX IREF |ICP| nICP ICP nICP_M Phase detector minimum comparison frequency Phase detector maximum comparison freq Charge pump reference current Charge pump output current: C0...C2 = 000 C0...C2 = 111 step size Relative output current variation1 Output current matching2 Output leakage current Output current tolerance with temperature with output voltage Serial Interface3 fCLOCK tSU tH tW NOTES: 1. The relative output current variation is defined thus: DI OUT +2 I OUT . TEST CONDITION CONDITION LIMITS MIN 140 TYP 276||0.6 50 64 1 1 44 10|| 1.0 50 200 1 400 350 511 MAX. 800 UNITS MHz Ω||pF mVpk Between LO_IN and LO_INX Single ended Referred to 50Ω MHz kΩ pF mVpk MHz MHz µA 0.240 0.480 0.035 "8 "12 mA mA mA % % nA % Between ClkIN and ClkINX Referred to 50Ω Ref Divider = 44 REXT = 50KΩ IREF = 31.25 µA VCP = VCCCP/2 IREF = 31.25 µA IREF = 31.25 µA VCP = VCCCP/2 0.160 0.320 0.023 2.5 31.25 0.200 0.400 0.029 1.3 0.2 "1 "5 "15 Clock frequency Set–up time; DATA to clock, CLOCK to STROBE Hold time: CLOCK to DATA Pulse width: CLOCK Pulse width: STROBE 30 30 30 30 10 MHz ns ns ns ns I2 – I1 I I2 ) 11 ; WITH V 1 + 0.7V, V 2 + V CCCP – 0.8V (see Figure 3). 2. The output current matching is measured when both (positive current and negative current) sections of the output charge pumps are on 3. Guaranteed by design. 4. Maximum level guaranteed by design. 1998 Jul 21 10 Philips Semiconductors Product specification IF quadrature transceiver SA1630 CURRENT I2 I1 The baseband amplifiers can interface directly to the Track/Hold switch/capacitor combination with capacitance values up to 15 pF. When sampled at 22MHz the output can settle to within 1/4 LSB when swinging 1V p–p. The chip has a unique mode in which the Rx is on standby while the Tx is ON. In this mode the Rx Baseband circuits are idling at reduced currents and all Rx I/O outputs retain their DC bias unchanged from their values when the Rx was fully ON. This mode is very essential if ac coupling through a large capacitor, such as, 10nF is used. From this mode the chip can quickly be switched to the Rx ON mode (Tx OFF) without worrying about charging/discharging the large AC coupling capacitor. The VGA can be programmed in 2 ways: 1) Directly programming external control pins. 2) programming over the serial 3–wire bus. The former method can switch gain in less than 200 ns. The Rx baseband section also incorporates simple low pass active filters of the Sallen key type. The Rx bandwidth is mainly set by these filters. The function of these filters is twofold: 1) attenuate high frequency signals from the Rx mixers. 2) act as anti–aliasing filters for any A to D converters following this chip. VOLTAGE V1 V2 I2 I1 SR00526 Figure 3. Relative Output Current Variation APPLICATION DESCRIPTION General The 1630 performs the IF modulator and demodulator functionality for high–speed wireless data transceivers. The design is optimized for IEEE 802.11 wireless LAN using 11 chips/symbol Direct Sequence Spread Spectrum. IF synthesizer The SA1630 has an integrated synthesizer that uses an external VCO operating on twice the IF frequency. It is internally divided by 2 for obtaining quadrature signals. The divided VCO signal is not externally available. This minimizes the LO feedthrough to the IF input port and hence minimizes output dc glitches when the IF gain is switched. The PLL reference clock is derived from the 22 MHz DSP clock. The available divider ratios facilitate both 1 and 2 MHz phase comparison frequency from a 22 MHz and an optional 44 MHz clock respectively. In essence the reference divider will have programmable dividers ratios of 8, 11, 22 and 44. The VCO shall be fed from a stabilized supply. Such a stabilized supply is necessary in order to prevent oscillator jitters due to Rx/Tx switching. The effect of oscillator jitters is further minimized when using a high PLL loop bandwidth, which on its turn requires a high phase comparison frequency (1 MHz, preferably 2 MHz). If the IF Synthesizer is not used, the CLKIN pins should be terminated to ac ground. Transmitter The IF quadrature transmitter baseband modulator input is driven differentially by the D/A converters in the DSP chip. The baseband signals are DC coupled for fast turn–on and turn–off and for constant carrier testing. The typical common–mode input voltage is VCC/2. The open collector outputs of the mixers are biased by two inductors, which are part of an LC tank. The LC tank matches the output impedance of the mixers to the input impedance of the upconverter chip (or any filter in between) and suppresses IF harmonics. An optional 2.5V reference is available during mode (3) and (5), the transmit mode with Rx in standby. This reference can be enabled or disabled via the 3 wire bus (in this mode). This voltage is provided for use by an external current DAC if needed. Serial Programming Input The serial input is a 3–wire input (CLOCK, STROBE, DATA) to program the counter ratios, charge pump current, status– and DC–offset register, mode select and test register. The programming data is structured into two 21–bit words; each word includes 4 chip address bits and 1 subaddress bit. Figure 2 shows the timing diagram of the serial input. When the STROBE = L, the clock driver is enabled and on the positive edges of the CLOCK the signal on DATA input is clocked into a shift register. When the STROBE = H, the clock is disabled and the data in the shift register remains stable. Depending on the value of the subaddress bit the data is latched into different working registers. Table 3 shows the contents of each word. Receiver The receiver part of the SA1630 consists of an IF Variable gain amplifier, a quadrature demodulator and a pair of baseband amplifiers. The IF amplifier has its gain controlled by the DSP chip. This ensures linear operation of the receiver chain over a wide dynamic range of input signals. Linear operation is essential for resolving echo’s due to multipath reception. The digital controlled AGC is meant for fast level training for the receiver. The high gain receiver, which is distributed between the IF and baseband part facilitates interfacing with the RF front–end chip, which normally have moderate gains (up to 20 dB), and SAW IF filters, which mostly have considerable loss (up to 8 dB) without external amplifiers. The baseband amplifiers have a high drive capability (1 Vpp into 1kΩ, 15 pF for VCC = 3V) that facilitates direct interfacing to the A/D converter without active external elements. Default States Upon power up (VCCDIG is applied) a reset signal is generated, which sets all registers to a default state. The logic level at the 1998 Jul 21 11 Philips Semiconductors Product specification IF quadrature transceiver SA1630 STROBE pin should be low during power up to guarantee a proper reset. These default states are shown in Table 2. The current can be set to zero by connecting the pin IREF to VCCCP. Reference Divider The reference divider can be programmed to four different division ratios (:8, :11, :22, :44), see registers r0, r1; default setting: divide by 22. Charge Pumps The charge pumps at pin CP are driven by the phase detector and the current value is determined by the binary value of the charge pumps register CN = c2, c1, c0, default .4mA. The active charge pump current is typically: |I CP| + (c0 ) 2c1 ) 4c2) @ 29mA ) 200mA Main Divider The external VCO signal, applied to the LOIN and LOINX inputs, is divided by two and then fed to the main divider (:N). The main divider is a programmable 9 bit divider, the minimum division ratio is divide by 64. The division ratio is binary coded and set in the registers n0 to n8. The default setting is a divide by 352. At the completion of a main divider cycle, a main divider output is generated which will drive the phase detector. Lock Detect The output LOCK is H when the phase detector indicates a lock condition. This condition is defined as a phase difference of less than ±1 cycle on the reference input CLKIN, CLKINX. Test Modes (Synthesizer, Transmit Mixer) The LOCK output is selectable as a test output. Bits x0, x1 control the selection, the default setting is normal lock output as described in the Lock detect section. The selection of a Bit x0, x1 combination has a twofold effect: First it routes a divider output signal to the LOCK pin, second it disables mixer stages in the transmit path. Setting x0,1 = 11 disables both transmit path mixers. This mode can be used to prevent the transmitter from producing an IF output signal even if the transmit part is powered on. This can be used to simplify the control timing while commanding the transmit and receive simultaneously without the transmit part causing interference. Phase Detector The phase detector is a D-type flip-flop phase and frequency detector shown in Figure 5. The flip-flops are set by the negative edges of the output signals of the dividers. The rising edge of the signal L will reset the flip-flops after both flip-flops have been set. Around zero phase error this has the effect of delaying the reset for 1 reference input cycle. This avoids non-linearity or deadband around zero phase error. The flip-flops drive on-chip charge pumps. A source current from the charge pump acts to increase the VCO frequency; a sink current acts to decrease the VCO frequency. Current Setting The charge pump current is defined by the current set between the pin IREF and VEECP. The current value to be set there is 31.2µA. This current can be set by an external resistor to be connected between the pin IREF and VEECP. The typical value REXT (current setting resistor) can be calculated with the formula R EXT + V CCCP–1.6V (44.87K for 3V) 31.2mA Table 1. Test Modes x0 0 1 0 1 x1 0 0 1 1 Synthesizer Signal y g at LOCK Pin normal lock detect CLKIN divided by reference divider ratio LOIN ÷ 2 * (main divider ratio) main divider output, that goes to the phase detector Transmit Mixer Q-mixer on off on off I-mixer on on off off 1998 Jul 21 12 Philips Semiconductors Product specification IF quadrature transceiver SA1630 Table 2. Definition of SA1630 Serial Registers First data word: (shown with default values) Address SA1630 MSB Sub Adr N-Divider Reference Divider Charge-Pump Test LSB a0 1 a1 1 a2 1 a3 0 sa 0 n0 1 n1 0 n2 1 n3 1 n4 0 n5 0 n6 0 n7 0 n8 0 r0 1 r1 0 c0 1 c1 1 c2 1 x0 0 x1 0 Address: Sub:Address: N-Divider: Reference Divider Register: Charge-Pump Register: Test Register: 4 bits, a0...a3, fixed to 1110 1 bit, sa, fixed to 0 for first data word 9 bits, n0...n8, values 64 (00100 0000) to 511 (11111 1111) allowed for IF choice, default 352 (assuming LO input frequency is 704 MHz). 2 bits, r0...r1, 00 = /8, 01 = 11, 10 = /22, 11 = /44. Default: 10 3 bits, c0...c2, Binary setting factor for charge pumps, values 000 = minimum current to 111 = maximum current, default is maximum charge pump current (111) 2 bits, x0...x1, default 00, see functional description for details Second data word: (shown with default values) Address SA1630 MSB Sub Adr LLL Mode Control I Offset Register Q Offset Register VGA Gain Control Misc Control bits LSB a0 1 a1 1 a2 1 a3 0 sa 1 s0 0 s1 0 i0 0 i1 0 i2 0 q0 0 q1 0 q2 0 b0 1 b1 1 b2 1 b3 1 b4 1 b5 1 bc 0 vc 1 Address: Sub:Address: LLL Mode control: I Offset Register: Q Offset Register: VGA Gain Control VGA Control Enable Regulator Disable 4 bits, a0...a3, fixed to 1110 1 bit, sa, fixed to 1 for second data word 2 bits, s0, s1 Not used, always set to 0, 0 3 bits, i0...i2 .10 Not used, always set to 0, 0, 0 3 bits, q0...q2. q0. Currently not being used, always set to 0, 0, 0 6 bits, b0...b5. 000 000 corresponds to maximum gain and 111 111 to minimum gain in 2 dB increments. Check control table contained elsewhere in this document. 1 bit, bc. When bc=0 the VGA is controlled by external pins. When bc=1 then bits b0...b5 control the VGA. Default bc=0, control by external pins 1 bit, Vc. When Vc=0 the 2.5V reference output is completely powered down. When Vc=1 the reference voltage is enabled (provided Tx_ON=HIGH). Default: Vc = 1, enable the 2.5 reference. 1998 Jul 21 13 Philips Semiconductors Product specification IF quadrature transceiver SA1630 LSB DATA X1 or t5 X0 or t4 tH tSU 50% CLOCK FIRST CLOCK a1 MSB a0 tSU LAST CLOCK FIRST CLOCK tSU STROBE CLOCK ENABLED SHIFT IN DATA tW 50% CLOCK DISABLED STORE DATA CLOCK STROBE SR00527 Figure 4. Serial Input Timing Sequence L “1” CLKIN REFERENCE DIVIDER R R P P-TYPE CHARGE PUMP D C Q VCCCP “1” LOIN D C R CP ÷2 MAIN DIVIDER X Q N N-TYPE CHARGE PUMP VSS CLKIN L R X P N ICP SR00528 Figure 5. Phase Detector Structure with Timing 1998 Jul 21 14 Philips Semiconductors Product specification IF quadrature transceiver SA1630 10m 1 100n VCCRx GNDRX 48 3V SUPPLY 2 GNDRx 3 GNDRX 47 1.8p VCCRx RxIF IN 46 44nH 5K RxIN 100n 4 PLL_ON 1n Rx_ON 1n 6 TxIFOUT GNDHDR 5 Rx_ON GNDRX 44 43 PLL_ON RxIF INX 45 1.8p 17.4 TxOUT 294 294 GC0 7 GC0 TxIFOUTX 42 GC1 8 GC1 GNDTxRx 41 40 1n GC2 9 GC2 GNDTxRx GC3 10 GC3 VCCTXRX 39 I0n 38 20Ω VREF GC4 11 GC4 VREF2.5 IREF GC5 12 GC5 37 10n 13 GND_BB GNDCP 36 14 GND_BB CP 35 CP 15 100n 16 15P 1K VCC__BB VCCCP DATA 34 100n 33 32 31 30 29 10n W 10n 28 27 26 25 24 23 1n TX_ON 10n 10n 50W CLKIN 3 WIRE SERIAL BUS Q_RXOUT CLOCK STROBE 17 15P 1K I_RxOUT LOCK LO INX LOCK LO IN 18 I/Q GEN 1MHZ FOR SSB TESTING (8MHZ FOR DSB TESTING) 19 I_TX IN LO_IN GNDRx I_Tx INX CLK IN CLK INX GNDDIG 20 Q_Tx IN 21 22 Q_Tx INX Tx_ON VCC DIG 100nF SR01550 Figure 6. Typical SA1630 Test Circuit 15 1998 Jul 21 Philips Semiconductors Product specification IF quadrature transceiver SA1630 Supply Current Sleep Mode 1 22 20 19 18 Supply Current uA 16 2.7 V 14 12 10 –50 0 Temperature °C 50 100 14 –50 3.6 V 3V Supply Current mA 18 Vs. Temperature and Supply 20 Supply Current Wait Mode 2 Vs. Temperature and Supply 3.6 V 17 3V 2.7 V 16 15 0 Temperature °C 50 100 Supply Current Transmit Mode 3 Vs. Temperature and Supply 30 29 28 36 Supply Current mA Supply Current mA 27 26 25 24 23 22 26 –50 0 Temperature °C 50 100 –50 3.6 V 3V 2.7 V 34 40 38 Supply Current Receive Mode 4 Vs. Temperature and Supply 3.6 V 32 2.7 V 30 28 0 Temperature °C 50 100 Supply Current Transmit Mode 5 Vs. Temperature and Supply 26 40 24 38 Third Harmonic dB 36 34 32 30 28 16 –50 0 Temperature °C 50 100 –50 Receiver Third Harmonic Distortion Vs. Temperature and Supply dB below signal with Rx input IVPP at maximum gain Supply Current mA 2.7 V 3V 3.6 V 22 3.6 V 3V 2.7 V 20 18 0 Temperature °C 50 100 SR01601 Figure 7. 1998 Jul 21 16 Philips Semiconductors Product specification IF quadrature transceiver SA1630 Receiver Maximum Gain Vs. Temperature and Supply 100 75 Receiver AGC Gain Range Vs. Temperature and Supply 95 Gain Range dB 2.7 V 3V 3.6 V Gain dB 90 3.6 V 3V 2.7 V 70 85 80 –50 0 Temperature °C 50 100 65 –50 0 Temperature °C 50 100 Transmitter Carrier and Sideband Suppression Vs. Temperature and Supply –30 –32 –34 –36 Suppression dB –38 –40 –42 –44 –46 –48 3.6 3 2.7 V Sideband Suppression Carrier Suppression Transmitter Third Harmonic Distortion Vs. Temperature and Supply –50 –55 3.6 3 2.7 V Distortion dBc –60 2.7 V 3 3.6 –65 –50–50 0 Temperature °C 50 100 –70 –50 0 Temperature °C 50 100 Transmitter AC Output Current Vs. Temperature and Supply 0.5 Average output at 353MHz Input 1VPP –190 P Charge Pump Current 000 Vs. Temperature and Supply –195 Current mA Current uA 0.4 2.7V to 3,6 V 3.6 –200 3 2.7 V –205 0.3 0.2 –50 0 Temperature °C 50 100 –210 –50 0 50 Temperature °C 100 SR01600 Figure 8. 1998 Jul 21 17 Philips Semiconductors Product specification IF quadrature transceiver SA1630 P Charge Pump Current 111 Vs. Temperature and Supply –390 205 N Charge Pump Current 000 Vs. Temperature and Supply –395 200 3.6 –405 3 –410 2.7 V Current uA Current uA –400 3.6 195 3 2.7 V –415 –420 –50 0 Temperature °C 50 100 190 –50 0 Temperature °C 50 100 N Charge Pump Current 111 Vs. Temperature and Supply 5 410 Charge Pump Match 111 Vs. Temperature and Supply 0 405 Current uA 3.6 V 400 3 V 2.7 V Current uA –5 2.7 V 3V 3.6 V –10 395 –15 390 –50 0 Temperature °C 50 100 –50 0 Temperature °C 50 100 N Charge Pump Step Size Vs. Temperature and Supply 35 P Charge Pump Step Size Vs. Temperature and Supply –25 33 –27 Current uA 31 29 3.6 V 3V 2.7 V 27 2.7 V 3V 3.6 V Current uA –29 –31 –33 –35 –50 0 Temperature C 50 100 25 –50 0 Temperature °C 50 100 SR01599 Figure 9. 1998 Jul 21 18 Philips Semiconductors Product specification IF quadrature transceiver SA1630 2.5 Reference Voltage Vs. Load and Temperature Reference Voltage V 3.0 2.8 2.6 2.4 –2.0 Vcc= 3V –1.2 –0.4 0.4 1.2 2.0 85°C 25°C –40°C Transmitter Input Modulation Bandwidth Vs. Frequency –21 Output Level dBm –22 –23 –24 –25 –26 0 Vcc = 3V 4 8 12 16 20 24 28 32 36 Frequency MHz Load Current mA Receiver Filter Bandwidth Vs. Frequency and Temperature –14 –16 Output Level dBm –18 –20 –22 –24 –26 0 3 6 9 12 Output Frequency MHz –40°C 25°C 85°C Transmitter RMS Output Current Vs. Input Voltage RMS Output mA rms 0.6 0.5 0.4 0.3 0.2 0.50 Vcc= 3V 0.70 0.90 1.10 1.30 1.50 Single Ended Input Vpp V 15 Vcc= 3V Gain= –70 Charge Pump Relative Variation Vs. Temperature and Supply 3 Vcm – 0.7V to VCC–0.8V Variation % 2 2.7 V P Pump 1 3V 3.6 V N Pump 2.7V to 3.6V 0 –50 0 Temperature °C 50 100 SR01602 Figure 10. 1998 Jul 21 19 Philips Semiconductors Product specification IF quadrature transceiver SA1630 LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 1998 Jul 21 20 Philips Semiconductors Product specification IF quadrature transceiver SA1630 NOTES 1998 Jul 21 21 Philips Semiconductors Product specification IF quadrature transceiver SA1630 Data sheet status Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Production [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 © Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 07-98 9397 750 04166 Philips Semiconductors 1998 Jul 21 22