PE1144BV

P letronics, Inc. 19013 36 Ave. West PO Box 2607 Lynnwood, Washington 98036 U.S.A. T: 1-425-776-1880 F: 1-425-776-2760 E: ple-sales@pletronics.com www.pletronics.com th Effective January 1, 2008 PE11xxBY PE33xxBY PE37xxBY Devices are OBSOLETE This has been discontinued because: • the difficulty of the older design to assemble well in the newer RoHS compliant high temperature reflow processes. • the cover assembly was not meeting some of the cleaning and assembly needs of the newer processes. • the components needed to make these parts are no longer available. This requirement is best met by using a PE99xxDV oscillator and a -3.3V regulator and operating the device from the 5.0V supply. Pl tronics., Inc. 19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA Manufacturer of High Quality Frequency Control Products Differential PECL Series Differential PECL Output, Some with Enable/ Disable Function Available in 9 Different Package/Configurations, See Next Pages Standard Specifications Overall Frequency Stability Operating Temperature Range Storage Temperature Range Supply Voltage (Vcc) Supply Current (Icc) Output High Level ± 50 PPM, ± 25 PPM, ± 20 PPM over Operating Temperature Range 0 to +80°C is standard, but can be extended to - 40 to +85°C - 55 to +125°C 3.3 volts ± 5% standard, but 5.0 volts or 2.5 volts also available. See Test Cirucit 5. < 250 MHz = 90 mA maximum, 250 MHz and above = 100 mA maximum 2.275 V minimum referenced to Ground, Vcc = 3.300V, 0.975 V minimum referenced to termination voltage, - 1.025 V minimum referenced to Vcc 1.680 V maximum referenced to Ground, Vcc = 3.300V, 0.380 V maximum referenced to termination voltage, - 1.620 V maximum referenced to Vcc 45/55% referenced to 50% of amplitude 1.0 nS maximum when Vth is 10% and 90% of waveform 1 pS RMS maximum measured from 12 kHz to 20 MHz from Fnominal 50 kohm minimum to Vcc 0.3 Vcc maximum referenced to Ground 0.7 Vcc minumum referenced to Ground Output Low Level Output Symmetry Output Rise & Fall (Tr & Tf) Jitter E/D Internal Pullup V disable V enable PE7745D only Output Enable / Disable High Level Input Current -20 uA maximum at Enable / Disable Pin = 0.7 Vcc Low Level Input Current -200 uA maximum at Enable / Disable Pin = 0 V Output Enable Time 200 nS maximum at output enable or 1 mS maximum at output enabled and stable Output Disable Time 200 nS maximum at output disable Vcc Supply Current disabled < 1 mA. Both outputs are high impedance when disabled. All other models Output Enable/Disable (E/D) Output Enable Time 100 nS maximum Output Disable Time 100 nS maximum When Disabled Q Output = Logic Low, QN Output = Logic High. Both Outputs are active Note 1: PECL and ECL are identical circuits. ECL has the most positive pin as ground and is ideally terminated by 50 ohms to - 2.00 V PECL has the most negative pin as ground and is ideally terminated by 50 ohms to the most (positive voltage less 2.00 V) Mechanical: See Next Pages D Package J Package Replacement B Package M Package Mar 2004 Pl tronics, Inc. (425) 776 -1880, Fax: (425) 776-2760, ple -sales@pletronics.com, www.pletronics.com 1 PECL, LVDS, OCXO Page 1 - 7 19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA Manufacturer of High Quality Frequency Control Products B Package PECL Series PE1145T, PE1145B, PE3345B, PE3745B Differential PECL Output with Enable/ Disable Function, 5.0 Vcc or 3.3 Vcc 6 Pad 14x10x3mm Leadless Surface Mount Clock Oscillator Part Numbering Guide Portions of the part number that appear after the frequency may not be marked on part (C of C provided) PE11 45 B V - 70.0M - XXX (Internal Code or blank) 1.50 MHz – 650.00 MHz Model Series > 120.0 MHz to 650 MHz (5.0 Vcc) > 180.0 MHz to 650 MHz (3.3 Vcc) PE1145T = E/D on pin2 Packaging Tube or 24mm tape, 16mm pitch Frequency in MHz Special Specifications (choose all that apply) E: Extended Operating Temperature Range (- 40 to +85°C) F: 47.5 /52.5% Symmetry at 50% of Vcc V: Supply Voltage of 3.3 volts ± 10% Y: Supply Voltage of 5.0 volts ± 10% Frequency Stability 45 = ± 50 PPM 44 = ± 25 PPM 20 = ± 20 PPM 1.5 MHz to 120 MHz (5.0 Vcc) 1.5 MHz to 180 MHz (3.3 Vcc) PE1145B = E/D on pin2, QN on pin 1 PE3345B = E/D on pin 2, QN on pin 5 PE3745B = E/D on pin 1, QN on pin 5 Consult factory for available frequencies and specs. Not all options available for all frequencies. A special part number may be assigned. Frequency Stability is inclusive of frequency shifts due to calibration, temperature, supply voltage, shock, vibration and load Mechanical: inches (mm) not to scale Solder Pads 0.200 (5.08) Due to part size and factory abilities, part marking may vary from lot to lot and may contain our part number or an internal code. 0.400 (10.16) MAX 4 5 6 3 2 1 1 2 3 0.560 (14.23) MAX 0.125 (3.17) MAX 0.200 (5.08) 0.055 0 .145 (1.4) (3.68) PE1145T PIN 1 2 3 4 5 6 SIGNAL N.C. E/D GND Q OUT QN OUT Vcc PE1145B PIN 1 2 3 4 5 6 SIGNAL QN OUT E/D GND Q OUT N.C. Vcc PE3345B PIN 1 2 3 4 5 6 SIGNAL N.C. E/D GND Q OUT QN OUT Vcc PE3745B PIN 1 2 3 4 5 6 SIGNAL E/D N.C. GND Q OUT QN OUT Vcc See page 6 for Layout Guidelines > 180.0 MHz to 650.0 MHz (3.3 Vcc) > 120.0 MHz to 650.0 MHz (5.0 Vcc) Jun 2004 1.5 MHz to 180.0 MHz (3.3 Vcc) 1.5 MHz to 120.0 MHz (5.0 Vcc) 2A Pl tronics, Inc. (425) 776 -1880, Fax: (425) 776-2760, ple -sales@pletronics.com, www.pletronics.com 0.118 0.228 (5.8) (3.0) 6 5 4 PECL, LVDS, OCXO Page 1 - 7 Pl tronics., Inc. Pl tronics., Inc. 19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA Manufacturer of High Quality Frequency Control Products PECL and LVDS Layout Guidelines SUGGESTED PCB LAYOUTS Solder Pad Layout which accommodates all PECL surface mount devices 0.200 (5.08) 0 .185 (4.7) 0 .087 (2.2) 'B Pkg' 5 x7 TOP SIDE BYPASS BOTTOM SIDE BYPASS 0.055 0.100 (1.4) (2.54) The output line should be designed with proper characteristic impedance. Pletronics recommends laying out for the larger 'B package' with pads long enough to accept the smaller 5 x 7mm device. This permits the best option for alternate sources of device. Pletronics also recommends connecting Pin 1 and Pin 2 together on the models with Q & QN OUT on pins 4 & 5. This allows having E/D on either pin 1 or pin 2. MULTI LAYER BYPASS For Optimum Jitter Performance, Pletronics recommends: A ground plane under the device with any other signals below the ground plane Minimize other RF signals near device No large transient signals (both current and voltage) should be routed under the device Do not layout near a large magnetic field such as a high frequency switching power supply Do not place near piezoelectric buzzers or mechancial fans Reflow Cycle for lead free processing 250 Temperature °C 200 150 100 215°C ± 10°C 50 Seconds 175°C ± 10°C 120 to 160 Seconds 260°C max 10 Seconds max T Rise= 4 Degree/second max Mar 2004 Pl tronics, Inc. (425) 776 -1880, Fax: (425) 776-2760, ple -sales@pletronics.com, www.pletronics.com 6 PECL, LVDS, OCXO Page 1 - 7 Pl tronics., Inc. 19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA Manufacturer of High Quality Frequency Control Products PECL and LVDS Layout Guidelines Continued PECL Terminations: Suggested Terminations for 50 ohm impedance matched termination Vcc Vcc R1 Vcc Out Oscillator GND Vcc Out Oscillator GND Thevenin Equivalent Termination Vcc 5.0 V 3.3 V 2.5 V R1 82 ohm 130 ohm 249 ohm R2 130 ohm 82 ohm 61.9 ohm 50 ohm Vcc - 2.00 V R2 Simple termination for NON impedance matched termination Vcc Vcc Out Oscillator GND R load Vcc 5.0 V 3.3 V 2.5 V R load 274 ohm 147 ohm 86.6 ohm LVDS Terminations: Vcc Vcc Q Out Oscillator GND QN Out 100 ohm Design PCB traces for 50 ohm characteristic impedance Mixed System Power Supply: PECL ECL LVDS To use multiple supply voltages requires level translation. Direct circuit connection is not valid. Mixed supply voltages are allowed. No translation is necessary. (ECL is returned to the most positive supply and this is common to all circuits) Mixed supply voltages are allowed. LVDS signal levels are power supply independent. 3.3 V LVDS oscillators properly interface 2.5 V Logic Arrays for example. Mar 2004 6A Pl tronics, Inc. (425) 776 -1880, Fax: (425) 776-2760, ple -sales@pletronics.com, www.pletronics.com