4280

To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS DESCRIPTION The 4280 Group is a 4-bit single-chip microcomputer designed with CMOS technology for remote control transmitters. The 4280 Group has 7 carrier waves and enables fabrication of 8 × 7 key matrix. FEATURES • Number of basic instructions ............................................. 62 • Minimum instruction execution time ............................ 8.0 µs (at f(X IN) = 4.0 MHz, system clock = f(XIN )/8, VDD=3.0 V) • Supply voltage ................................................. 1.8 V to 3.6 V • Subroutine nesting ..................................................... 4 levels • Timer Timer 1 ................................................................... 8-bit timer with a reload register and carrier wave output auto-control function ROM (PROM) size (× 9 bits) 1024 words 1024 words 1024 words 1024 words • Carrier wave output function (port CARR) f(X IN), f(XIN)/4, f(XIN )/8, f(XIN)/12 f(X IN)/64, f(XIN)/96, “H” output fixed • Logic operation function (XOR, OR, AND) • RAM back-up function • Key-on wakeup function (ports D 7, E 0–E2, G 0–G3) ............. 8 • I/O port (ports D, E, G, CARR) .......................................... 16 • Oscillation circuit ..................................... Ceramic resonance • Watchdog timer • Power-on reset circuit • Voltage drop detection circuit ......................... Typical:1.50 V APPLICATION Various remote control transmitters Product M34280M1-XXXFP M34280M1-XXXGP M34280E1FP M34280E1GP RAM size (× 4 bits) 32 words 32 words 32 words 32 words Package 20P2N-A 20P2E/F-A 20P2N-A 20P2E/F-A ROM type Mask ROM Mask ROM One Time PROM One Time PROM PIN CONFIGURATION (TOP VIEW) M34280M1-XXXFP/GP VSS E2 E1 XIN XOUT E0 G0 G1 G2 G3 1 2 20 19 VDD CARR D0 D1 D2 D3 D4 D5 D6 D7 M34280M1-XXXFP/GP 3 4 5 6 7 8 9 10 18 17 16 15 14 13 12 11 Outline 20P2N-A 20P2E/F-A 2 1 2 4 7 1 BLOCK DIAGRAM I/O port Port E Port G Port D Internal peripheral functions System clock generating circuit XIN–XOUT Timer Timer 1 (8 bits) Remote control carrier wave output Memory ROM (Note) 1024 words × 9 bits RAM 32 words × 4 bits 720 Series CPU core ALU (4 bits) Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) Stack register SK (4 levels) 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS MITSUBISHI MICROCOMPUTERS Note: PROM 1024 words × 9 bits MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS PERFORMANCE OVERVIEW Parameter Number of basic instructions Function 62 Minimum instruction execution time 8.0 µs (at 4.0 MHz system clock frequency) Memory sizes ROM Input/Output ports RAM D0–D6 D7 E0–E2 E0, E1 G0–G3 CARR Timer 1 Subroutine nesting Device structure Package Operating temperature range Supply voltage Power dissipation Active mode (f(XIN ) = 4.0 MHz, system clock = f(XIN )/8, VDD = 3 V) M34280M1/ 1024 words ! 9 bits E1 Output I/O Input Output I/O Output 32 words ! 4 bits Seven independent output ports 1-bit I/O port with the pull-down function 3-bit input port with the pull-down function 2-bit output port (E0, E1) 4-bit I/O port with the pull-down function 1-bit output port; CMOS output 8-bit timer with a reload register 4 levels (However, only 3 levels can be used when the TABP p instruction is executed) CMOS silicon gate 20-pin plastic molded SOP (20P2N-A)/SSOP (20P2E/F-A) –20 °C to 85 °C 1.8 V to 3.6 V 400 µA (f(XIN ) = 4.0 MHz, system clock = f(XIN )/8, VDD = 3 V) (typical value) RAM back-up mode 0.1 µA (at room temperature, VDD = 3 V) PIN DESCRIPTION Pin VDD VSS XIN XOUT D0–D6 D7 Name Power supply Ground System clock input System clock output Output port D I/O port D Input/Output — — Input Output Output I/O Connected to a plus power supply. Connected to a 0 V power supply. I/O pins of the system clock generating circuit. Connect a ceramic resonator between pins XIN and X OUT. The feedback resistor is built-in between pins XIN and XOUT. Each pin of port D has an independent 1-bit wide output function. The output structure is P-channel open-drain. 1-bit I/O port. For input use, turn on the built-in pull-down transistor and set the latch of the specified bit to “0.” In addition, key-on wakeup function using “H” level sense becomes valid. The output structure is P-channel open-drain. E0–E2 I/O port E Output Input 2-bit (E0, E 1) output port. The output structure is P-channel open-drain. 3-bit input port. For input use (E0, E1), turn on the built-in pull-down transistor and set the latch of the specified bit to “0.” In addition, key-on wakeup function using “H” level sense becomes valid. Port E2 has an input-only port and has a key-on wakeup function using “H” level sense and pull-down transistor. G0–G3 I/O port G I/O 4-bit I/O port. For input use, set the latch of the specified bit to “0.” The output structure is P-channel open-drain. Port G has a key-on wakeup function using “H” level sense and pull-down transistor. CARR Carrier wave output for remote control Output Carrier wave output pin for remote control. The output structure is CMOS circuit. Function 3 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS CONNECTIONS OF UNUSED PINS Pin D 0–D7 E 0, E1 E2 G 0–G3 Connection Open or connect to VDD pin (Note 1). Set the output latch to “1” and open, or connect to VDD pin (Note 2). Open or connect to VSS pin. Set the output latch to “0” and open, or connect to VSS pin. Notes 1: Port D7: Set the bit 2 (PU02) of the pull-down control register PU0 to “0” by software and turn the pull-down transistor OFF. 2: Set the corresponding bits (PU00, PU01) of the pull-down control register PU0 to “0” by software and turn the pull-down transistor OFF. (Note in order to set the output latch to “0” to make pins open) • After system is released from reset, a port is in a high-impedance state until the output latch of the port is set to “0” by software. Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur. • To set the output latch periodically is recommended because the value of output latch may change by noise or a program run away (caused by noise). (Note when connecting to VSS and VDD) • Connect the unused pins to VSS or VDD at the shortest distance and use the thick wire against noise. PORT FUNCTION Port Port D Pin D0–D6 Input/ Output Output structure Control bits 1 bit Control instructions SD RD CLD SD RD CLD P-channel open-drain SZD Output: OEA 2 bits Input: 3 bits P-channel open-drain 4 bits IAE IAE OGA IAG 1 bit OCRA C Pull-down function and key-on wakeup function PU0 PU0 Pull-down function and key-on wakeup function (programmable) Pull-down function and key-on wakeup function (programmable) Control registers Remark Output P-channel open-drain (7) I/O (1) D7 Port E E0 E1 E2 I/O (2) Input (1) I/O (4) Port G G0–G3 Port CARR CARR Output CMOS (1) DEFINITION OF CLOCK AND CYCLE • System clock (STCK) The system clock is the source clock for controlling this product. It can be selected as shown below whether to use the CCK instruction. CCK instruction When not using When using System clock f(X IN)/8 f(XIN) Instruction clock f(XIN)/32 f(XIN)/4 • Instruction clock (INSTCK) The instruction clock is a signal derived by dividing the system clock by 4, and is the basic clock for controlling CPU. The one instruction clock cycle is equivalent to one machine cycle. • Machine cycle The machine cycle is the cycle required to execute the instruction. 4 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS PORT BLOCK DIAGRAMS Register Y SD instruction RD instruction CLD instruction Decoder (Note 1) S R Q Ports D0–D6 Register Y SD instruction RD instruction Decoder (Note 1) SQ R CLD instruction Pull-down transistor PU02 Port D7 (Note 4) Skip decision (SZD instruction) Key-on wakeup input Register A A0 OEA instruction A0 Key-on wakeup input PU00 Register A A1 A1 OEA instruction DQ T IAE instruction Pull-down transistor DQ T IAE instruction (Note 1) Port E0 (Note 4) (Note 1) Port E1 (Note 4) Key-on wakeup input PU01 IAE instruction Pull-down transistor Register A A2 Key-on wakeup input Port E2 (Note 4) (Note 1) Pull-down transistor Register A Ai (Note 2) Ai Key-on wakeup input TCA instruction Register A Aj (Note 3) Register C OGA instruction DQ T IAG instruction Pull-down transistor (Note 1) Ports G0–G3 (Note 4) Register A Aj (Note 3) TAC instruction To timer 1 CARRY (Note 1) Carrier wave output circuit Register A A3 OCRA instruction Timer 1 underflow signal V12 Port CARR DQ TR TCA instruction DQ TR V10 Carrier wave output control signal Notes 1: This symbol represents a parasitic diode. 2: i represents bits 0 to 3. 3: j represents bits 0 to 2. 4: Applied voltage must be less than VDD. 5 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS FUNCTION BLOCK OPERATIONS CPU (CY) (1) Arithmetic logic unit (ALU) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4-bit data addition, comparison, and bit manipulation. (2) Register A and carry flag Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to “1” when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A 0 i s stored in carry flag CY with the RAR instruction (Figure 2). Carry flag CY can be set to “1” with the SC instruction and cleared to “0” with the RC instruction. (3) Registers B and E Register B is a 4-bit register used for temporary storage of 4bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3). (4) Register D Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 4). (M(DP)) Addition (A) Fig. 1 AMC instruction execution example ALU SC instruction RC instruction CY A3 A2 A1 A0 RAR instruction A0 CY A3 A2 A1 Fig. 2 RAR instruction execution example Register B TAB instruction Register A B3 B2 B1 B0 A3 A2 A1 A0 TEAB instruction Register E ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 TABE instruction B3 B2 B1 B0 Register B A3 A2 A1 A0 TBA instruction Register A Fig. 3 Registers A, B and register E TABP p instruction Specifying address 8 ROM 4 0 Low-order 4 bits p3 PCH p2 p1 p0 PCL DR2 DR1 DR0 A3 A2 A1 A0 Register A (4) Middle-order 4 bits Register B (4) Most significant 1 bit Carry flag CY (1) Immediate field value p The contents of register D The contents of register A URS flag (1) URSC instruction Fig. 4 TABP p instruction execution example 6 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS (5) Most significant ROM code reference enable flag (URS) URS flag controls whether to refer to the contents of the most significant 1 bit (bit 8) of ROM code when executing the TABP p instruction. If URS flag is “0,” the contents of the most significant 1 bit of ROM code is not referred even when executing the TABP p instruction. However, if URS flag is “1,” the contents of the most significant 1 bit of ROM code is set to flag CY when executing the TABP p instruction (Figure 4). URS flag is “0” after system is released from reset and returned from RAM back-up mode. It can be set to “1” with the URSC instruction, but cannot be cleared to “0.” (6) Stack registers (SKs) and stack pointer (SP) Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when; • performing a subroutine call, or • executing the table reference instruction (TABP p). Stack registers (SKs) are four identical registers, so that subroutines can be nested up to 4 levels. However, one of stack registers is used when executing a table reference instruction. Accordingly, be careful not to over the stack. The contents of registers SKs are destroyed when 4 levels are exceeded. The register SK nesting level is pointed automatically by 2-bit stack pointer (SP). Figure 5 shows the stack registers (SKs) structure. Figure 6 shows the example of operation at subroutine call. (7) Skip flag Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. Note : The 4280 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped. Program counter (PC) Executing BM instruction SK0 SK1 SK2 SK3 Executing RT instruction (SP) = 0 (SP) = 1 (SP) = 2 (SP) = 3 Stack pointer (SP) points “3” at reset or returning from RAM back-up mode. It points “0” by executing the first BM instruction, and the contents of program counter is stored in SK0. When the BM instruction is executed after four stack registers are used ((SP) = 3), (SP) = 0 and the contents of SK0 is destroyed. Fig. 5 Stack registers (SKs) structure (SP) (SK0) (PC) 0 000116 SUB1 Main program Address 000016 NOP 000116 BM SUB1 000216 NOP Subroutine SUB1 : NOP · · · RT (PC) (SP) (SK0) 3 Note: Returning to the BM instruction execution address with the RT instruction, and the BM instruction is equivalent to the NOP instruction. Fig. 6 Example of operation at subroutine call 7 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS (8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed. Program counter consists of PCH (most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7). Make sure that the PCH does not exceed after the last page of the built-in ROM. (9) Data pointer (DP) Data pointer (DP) is used to specify a RAM address and consists of registers X and Y. Register X specifies a file and register Y specifies a RAM digit (Figure 8). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 9). Program counter (PC) p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0 PCH Specifying page PCL Specifying address Fig. 7 Program counter (PC) structure Data pointer (DP) X1 X0 Y3 Y2 Y1 Y0 Register Y (4) Register X (2) Specifying RAM digit Specifying RAM file Fig. 8 Data pointer (DP) structure Specifying bit position Set D7 D5 D0 0 101 Register Y (4) 1 Port D output latch Fig. 9 SD instruction execution example 8 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS PROGRAM MEMORY (ROM) The program memory is a mask ROM. 1 word of ROM is composed of 9 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 ROM size and pages Product M34280M1 M34280E1 ROM size (! 9 bits) 1024 words Pages 8 (0 to 7) 8 000016 007F16 008016 00FF16 010016 017F16 018016 7 6 5 4 3 2 10 Page 0 Page 1 Subroutine special page Page 2 Page 3 Page 2 (addresses 0100 16 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. ROM pattern of all addresses can be used as data areas with the TABP p instruction. 03FF16 Fig. 10 ROM map of M34280M1 Page 7 DATA MEMORY (RAM) 1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers X and Y. Set a value to the data pointer certainly when executing an instruction to access RAM. Table 2 shows the RAM size. Figure 12 shows the RAM map. Table 2 RAM size Product M34280M1 M34280E1 RAM 32 words × 4 bits (128 bits) Register X 0 1 2 3 Register Y 0 1 2 3 4 5 6 7 32 words RAM size 32 words ! 4 bits (128 bits) Fig. 11 RAM map 9 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS TIMERS The 4280 Group has the programmable timer. • Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer 1 underflow flag is set to “1,” new data is loaded from the reload register, and count continues (auto-reload function). FF16 n : Counter initial value Count starts n Reload Reload The contents of counter 1st underflow 2nd underflow 0016 Time n+1 count Timer 1 underflow flag A skip instruction is executed. n+1 count Fig. 12 Auto-reload function 10 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS The 4280 Group timer consists of the following circuit. • Timer 1 : 8-bit programmable timer This timer can be controlled with the timer control register V1. Timer 1 function is described below. Table 3 Function related timer Circuit Timer 1 Structure 8-bit programmable binary down counter Count source Frequency dividing ratio Use of output signal • Carrier wave output control Control register V1 • Carrier generating circuit 1 to 256 output (CARRY) • Bit 5 of watchdog timer V11 V10 (Note 1) 0 1 SNZT1 instruction Timer 1 (8) CARRY 0 1 T1F DQ Carrier wave output control signal Reload register R1 (8) (TAB1) (T1AB)(Note 2) Register B Register A V12 TR V10 Frequency divider (divided by 8) STCK (System clock) Frequency divider (divided by 4) INSTCK (Instruction clock) XIN CCK instruction Initializing signal (Note 3) SQ R Synchronous circuit Initializing signal (Note 3) System reset 14-bit timer (WDT) INSTCK 0 5 13 WDF1 WDF2 WRST instruction Initializing signal (Note 3) Notes 1: Counting is stopped by clearing to “0. ” 2: When the T1AB instruction is executed after V10 is set to “1,” writing is performed only to reload register R1. 3: The initializing signal is output at reset or RAM back-up mode. : Data is automatically set from a reload register when timer 1 underflows (auto-reload function). Fig. 13 Timers structure 11 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS Table 4 Control registers related to timer Timer control register V1 V12 V11 V10 Carrier wave output auto-control bit Timer 1 count source selection bit Timer 1 control bit 0 1 0 1 0 1 at reset : 0002 at RAM back-up : 0002 W Auto-control output by timer 1 is invalid Auto-control output by timer 1 is valid Carrier output (CARRY) Bit 5 of watchdog timer (WDT) Stop (Timer 1 state retained) Operating Note: “W” represents write enabled. (1) Control register related to timer • Timer control register V1 Register V1 controls the timer 1 count source and autocontrol function of carrier wave output from port CARR by timer 1. Set the contents of this register through register A with the TV1A instruction. (2) Precautions Note the following for the use of timers. • Count source Stop timer 1 counting to change its count source. • Watchdog timer Be sure that the timing to execute the WRST instruction in order to operate WDT efficiently. • Writing to reload register R1 When writing data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows. (3) Timer 1 Timer 1 is an 8-bit binary down counter with the timer 1 reload register (R1). When timer is stopped, data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB instruction. When timer is operating, data can be set to only reload register R1 with the T1AB instruction. When setting the next count data to reload register R1 at operating, set data before timer 1 underflows. Timer 1 starts counting after the following process; Œ set data in timer 1,  select the count source with the bit 1 of register V1, and Ž set the bit 0 of register V1 to “1.” Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes “0”), the timer 1 underflow flag (T1F) is set to “1,” new data is loaded from reload register R1, and count continues (auto-reload function). When a value set in reload register R1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). Data can be read from timer 1 to registers A and B. When reading the data, stop the counter and then execute the TAB1 instruction. (4) Timer 1 underflow flag (T1F) Timer 1 underflow flag is set to “1” when the timer 1 underflows. The state of this flag can be examined with the skip instruction (SNZT1). T1F flag is cleared to “0” when the next instruction is skipped with a skip instruction. 12 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS WATCHDOG TIMER Watchdog timer provides a method to reset and restart the system when a program runs wild. Watchdog timer consists of 14-bit timer (WDT) and watchdog timer flags (WDF1, WDF2). Watchdog timer downcounts the instruction clock (INSTCK) as the count source. When the timer WDT count value becomes 0000 16 and underflow occurs, the WDF1 flag is set to “1.” Then, when the WRST instruction is not executed before the timer WDT counts 16383, WDF2 flag is set to “1” and internal reset signal is generated and system reset is performed. When using the watchdog timer, execute the WRST instruction at period of 16383 machine cycle or less to keep the microcomputer operation normal. Timer WDT is also used for generation of oscillation stabilization time. When system is returned from reset and from RAM backup mode by key-input, software starts after the stabilization oscillation time until timer WDT downcounts to 3E00 16 elapses. Software start Software start Software start 3FFF16 3E0016 Value of timer WDT 0000 16 WDF1 flag WDF2 flag “1” “0” “1” “0” “H” Internal reset signal “L” System reset POF instruction execution Return WRST instruction execution System reset Fig. 14 Watchdog timer function 13 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS CARRIER GENERATING CIRCUIT The 4280 Group can output the various carrier waveforms by the carrier wave selection register C. Set the contents of this register through register A with the TCA instruction. The TAC instruction can be used to transfer the contents of register C to register A. When the TCA instruction is executed, the output latch of port CARR is cleared to “0.” The carrier waveform selected by setting register C can be output from port CARR by setting port CARR output latch to “1.” When the CARR output latch is cleared to “0,” carrier wave output is stopped and port CARR output is fixed to “L” level. The CARR output latch can be set through bit 3 (A 3) of register A with the OCRA instruction. The relationship between the setting value of register C and selected waveform is described below. Also, timer 1 can auto-control the carrier wave output from port CARR by setting the timer control register V1. Carrier wave selection register C (at reset: 1112, at RAM back-up: 1112) Register C setting value LA 8 O CRA Output waveform LA 0 (TC A) O CRA Carrier wave Frequency Duty C2 C 1 C0 0 0 0 “H” “L” 1/3 System clock/ 12 0 0 1 “H” “L” 1/2 0 1 0 “H” “L” 1/4 System clock/ 8 0 1 1 “H” “L” 1/2 1 0 0 “H” “L” System clock 1/2 1 0 1 “H” “L” No carrier wave 1 1 0 “H” “L” f(XIN)/4 (Note) 1/2 1 1 1 “H” “L” “L” level fixed Note: This carrier wave can be used only when system clock f(XIN)/8 is selected. The carrier wave output is fixed to “L” level when system clock f(XIN) is selected. Fig. 15 Carrier wave selection register 14 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS Timer 1 start (V10)←1 Timer 1 underflow “1” “0” “H” “L” a b c d Port CARR output a Set the interval “a” to timer 1. Select count source CARRY (V11)←0 b c d Set the interval “b” Set the interval “c” Set the interval “d” to reload register R1. to reload register R1. to reload register R1. Auto-control valid (V12)←1 Carrier wave output start Timer 1 stop (V10)←0 Timer 1 underflow “1” “0” “H” “L” (Note) CARRY Port CARR output “H” “L” “1” Register V12 “0” Auto-control invalid Carrier wave output start (V12)←0 (V12)←1 Auto-control invalid (V12)←0 (V12)←1 Carrier wave output stop Note: When timer 1 is stopped, the port CARR output auto-control is terminated regardless of bit 2 (V12) of register V1. Fig. 16 Port CARR output auto-control by timer 1 LOGIC OPERATION FUNCTION The 4280 Group has the 4-bit logic operation function. The logic operation between the contents of register A and the low-order 4 bits of register E is performed and its result is stored in register A. Table 5 Logic operation selection register LO Logic operation selection register LO Each logic operation can be selected by setting logic operation selection register LO. Set the contents of this register through register A with the TLOA instruction. The logic operation selected by register LO is executed with the LGOP instruction. Table 5 shows the logic operation selection register LO. at RAM back-up : 002 W at reset : 002 LO1 L O0 0 LO1 Logic operation selection bits LO0 Note: “W” represents write enabled. 0 1 1 Logic operation function 0 Exclusive logic OR operation (XOR) 1 OR operation (OR) 0 AND operation (AND) 1 Not available 15 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS RESET FUNCTION The 4280 Group has the power-on reset circuit, though it does not have RESET pin. System reset is performed automatically at power-on, and software starts program from address 0 in page 0. In order to make the built-in power-on reset circuit operate efficiently, set the voltage rising time until VDD= 0 to 2.2 V is obtained at power-on 1ms or less. f(XIN) “H” Internal reset signal “L” f(XIN) 16384 pulses Software starts (address 0 in page 0) Fig. 17 Reset release timing VDD Internal reset signal Power-on reset circuit Power-on reset circuit output voltage Reset state Voltage drop detection circuit Watchdog timer output Internal reset signal Reset released Power-on Fig. 18 Power-on reset circuit example 16 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS (1) Internal state at reset Table 6 shows port state at reset, and Figure 19 shows internal state at reset (they are retained after system is released from reset). The contents of timers, registers, flags and RAM except shown in Figure 19 are undefined, so set the initial value to them. • Program counter (PC) .............................................................. 0 Address 0 in page 0 is set to program counter. • Power down flag (P) ................................................................. 0 • Timer 1 underflow flag (T1F) ................................................... 0 • Timer control register V1 .......................................................... 0 • Carrier wave selection register C ............................................ 1 • Pull-down control register PU0 ................................................ 0 • Logic operation selection register LO ...................................... 0 • Most significant ROM code reference enable flag (URS) 0 • Carry flag (CY) ......................................................................... 0 • Register A ................................................................................. 1 • Register B ................................................................................. 1 • Stack pointer (SP) .................................................................... 1 Fig. 19 Internal state at reset Table 6 Port state at reset Name “H” output D0–D6 D7 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 1 1 1 1 State at reset State after system is released from reset High impedance state Input circuit OFF (Pull-down transistor OFF) Input port (Pull-down transistor ON) Input port (Pull-down transistor OFF) “H” output Input port (Pull-down transistor ON) G0–G3, E2 Input circuit OFF (Pull-down transistor OFF) E0, E1 Note: The contents of all output latch is initialized to “0.” VOLTAGE DROP DETECTION CIRCUIT The built-in drop detection circuit is designed to detect a drop in voltage at operating and to reset the microcomputer if the supply voltage drops below the specified value (Typ. 1.50 V) or less. The voltage drop detection circuit is stopped and power dissipation is reduced at the RAM back-up mode, when the functions except the RAM and pull-down control register (PU0) are initialized. VDD Reset voltage Microcomputer starts operation after f(XIN) is counted to 16384 times. Internal reset signal Fig. 20 Voltage drop detection circuit operation waveform 17 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS RAM BACK-UP MODE The 4280 Group has the RAM back-up mode. When the POF instruction is executed, system enters the RAM back-up state. As oscillation stops retaining RAM, the function of reset circuit and states at RAM back-up mode, power dissipation can be reduced without losing the contents of RAM. Table 7 shows the function and states retained at RAM back-up. Figure 21 shows the state transition. (1) Identification of the start condition Warm start (return from the RAM back-up state) or cold start (return from the normal reset state) can be identified by examining the state of the power down flag (P) with the SNZP instruction. (2) Warm start condition When the external wakeup signal is input after the system enters the RAM back-up state by executing the POF instruction, the CPU starts executing the software from address 0 in page 0. In this case, the P flag is “1.” (3) Cold start condition The CPU starts executing the software from address 0 in page 0 when any of the following conditions is satisfied . • reset by power-on reset circuit is performed • reset by watchdog timer is performed • reset by voltage drop detection circuit is performed In this case, the P flag is “0.” Table 7 Functions and states retained at RAM back-up Function Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2) Contents of RAM Ports D0–D6 (Note 3) Port D7 Port E0 Port E1 Port G Timer control register V1 Pull-down control register PU0 Logic operation selection register LO Timer 1 function Timer 1 underflow flag (T1F) Watchdog timer (WDT) Watchdog timer flag 1 (WDF1) Watchdog timer flag 2 (WDF2) Most significant ROM code reference enable flag (URS) RAM back-up ! O ! (“H” output) (PU02)=0 (Note 3) ! (“H” output) (PU02)=1 ! (input) (PU00)=0 (Note 4) ! (input cut-off) (PU00)=1 ! (input) (PU01)=0 (Note 4) ! (input cut-off) (PU01)=1 ! (input) ! (input) ! O ! ! ! ! ! ! ! Notes 1: “O” represents that the function can be retained, and “!” represents that the function is initialized. Registers and flags other than the above are undefined at RAM back-up, and set an initial value after returning. 2:The stack pointer (SP) points the level of the stack register and is initialized to “112” at RAM back-up. 3: The contents of port output latch is initialized to “0.” However, port continues to output “H” level. 4: The state of this bit is equal to the state at reset. 18 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS (4) Return signal An external wakeup signal is used to return from the RAM back-up mode. Table 8 shows the return condition for each return source. Table 8 Return source and return condition Return source Ports D7, E0, E1 Ports G, E2 Return condition Remarks Return by an external “H” level Only key-on wakeup function of the port whose pull-down transistor is input. turned ON is valid. Return by an external “H” level Key-on wakeup function is always valid. input. (5) Pull-down control register PU0 • Pull-down control register PU0 Register PU0 controls the ON/OFF of pull-down transistor, input, key-on wakeup function of ports E0, E1 and D7. Set the contents of this register through register A with the TPU0A instruction. Table 9 Pull-down control register Pull-down control register PU0 PU0 2 PU0 1 PU0 0 Port D7 pull-down control bit Port E1 pull-down control bit Port E0 pull-down control bit 0 1 0 1 0 1 at reset : 0002 at RAM back-up : state retained W Pull-down transistor OFF, input circuit OFF, key-on wakeup invalid Pull-down transistor ON, input circuit ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Note: “W” represents write enabled. A (Stabilizing time a ) Reset f(XIN) oscillation POF instruction is executed B f(XIN) stop Return input (Stabilizing time a ) (RAM back-up mode) Stabilizing time a : Microcomputer starts its operation after f(XIN) is counted to16384 times. Fig. 21 State transition Power down flag P POF instruction Reset input S Q Software start P = “1” ? No Cold start Yes R q Set source q Clear source Warm start POF instruction is executed Reset input Fig. 22 Set source and clear source of the P flag Fig. 23 Start condition identified example using the SNZP instruction 19 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS CLOCK CONTROL The clock control circuit consists of the following circuits. • System clock generating circuit • Control circuit to stop the clock oscillation • Control circuit to return from the RAM back-up state CCK instruction XIN XOUT Frequency divider (divided by 8) OSC Multiplexer Internal clock generating circuit (divided by 4) STCK Internal power-on reset circuit INSTCK POF instruction R S Q Pull-down control register PU0 Port D7 Ports E0, E1 Ports E2, G0–G3 Fig. 24 Clock control circuit structure Clock signal f(XIN) is obtained by externally connecting a ceramic resonator. Connect this external circuit to pins XIN and XOUT at the shortest distance as shown Figure 26. A feedback resistor is built-in between XIN pin and XOUT pin. 4280 XIN 4 XOUT 5 ROM ORDERING METHOD Please submit the information described below when ordering Mask ROM. (1) Mask ROM Order Confirmation Form................................. 1 (2) Data to be written into mask ROM .......................... EPROM (three sets containing the identical data) (3) Mark Specification Form .................................................... 1 CIN Use the resonator manufacturer’s recommended value because constants such as capacitance depend on the resonator. COUT Fig. 25 Ceramic resonator external circuit 20 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS LIST OF PRECAUTIONS Œ Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up; • connect a bypass capacitor (approx. 0.01 µF) between pins V DD and VSS at the shortest distance, • equalize its wiring in width and length, and • use the thickest wire. In the One Time PROM version, port E2 is also used as VPP pin. Connect this pin to V SS through the resistor about 5 kΩ which is assigned to E 2/V PP pin as close as possible at the shortest distance.  Notes on unused pins (Note in order to set the output latch to “0” to make pins open) • After system is released from reset, a port is in a highimpedance state until the output latch of the port is set to “0” by software. Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur. • To set the output latch periodically is recommended because the value of output latch may change by noise or a program run away (caused by noise). (Note when connecting to V SS and VDD) • Connect the unused pins to V SS and VDD at the shortest distance and use the thick wire against noise. Ž Timer • Count source Stop timer 1 counting to change its count source. • Watchdog timer Be sure that the timing to execute the WRST instruction in order to operate WDT efficiently. • Writing to reload register R1 When writing data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows.  Program counter Make sure that the program counter does not specify after the last page of the built-in ROM. 21 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS SYMBOL The symbols shown below are used in the following list of instruction function and the machine instructions. Symbol A B DR ER C V1 PU0 LO X Y DP PC PCH PCL SK SP CY R1 T1 T1F WDT WDF1 WDF2 URS P STCK INSTCK Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) Carrier wave selection register C (3 bits) Timer control register V1 (3 bits) Pull-down control register PU0 (3 bits) Logic operation selection register LO (2 bits) Register X (2 bits) Register Y (4 bits) Data pointer (6 bits) (It consists of registers X and Y) Program counter (10 bits) High-order 3 bits of program counter Low-order 7 bits of program counter Stack register (10 bits ! 4) Stack pointer (2 bits) Carry flag Timer 1 reload register Timer 1 Timer 1 underflow flag Watchdog timer Watchdog timer flag 1 ← ↔ ? () — M(DP) a p, a Contents D E G CARR x y p n j A 3A 2A1A0 Symbol Port D (8 bits) Port E (3 bits) Port G (4 bits) Port CARR (1 bit) Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal constant which represents the immediate value Hexadecimal constant which represents the immediate value Binary notation of hexadecimal variable A (same for others) Direction of data movement Data exchange between a register and memory Decision of state shown before “?” Contents of registers and memories Negate, Flag unchanged after executing instruction RAM address pointed by the data pointer Label indicating address a6 a5 a 4 a 3 a2 a1 a 0 Label indicating address a6 a5 a 4 a 3 a2 a1 a 0 in page p3 p2 p1 p 0 Hex. number C + Hex. number x (also same for others) Contents Watchdog timer flag 2 Most significant ROM code reference enable flag C Power down flag + System clock Instruction clock x Note : The 4280 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped. 22 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS LIST OF INSTRUCTION FUNCTION Grouping Mnemonic Comparison TAB TBA Register to register transfer TAY TYA TEAB Function (A) ← (B) (B) ← (A) Grouping Mnemonic LA n Function (A) ← n n = 0 to 15 Grouping Mnemonic SEAM operation SEA n Function (A) = (M(DP)) ? (A) = n ? n = 0 to 15 TABP p (A) ← (Y) (Y) ← (A) (ER7–ER4) ← (B) (ER3–ER0) ← (A) TABE (B) ← (ER 7–ER4) (A) ← (ER 3–ER0) (DR2–DR0) ← (A2–A0) Arithmetic operation (X) ← x, x = 0 to 3 (Y) ← y, y = 0 to 15 (Y) ← (Y) + 1 (Y) ← (Y) – 1 (A) ← (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 XAM j (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 XAMD j (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (Y) ← (Y) – 1 RAR XAMI j (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (Y) ← (Y) + 1 SB j Bit operation LGOP An (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p p=0 to 7 (PC L ) ← ( DR 2 –DR 0 , A 3–A0) When URS=0 (B) ← (ROM(PC))7 to 4 (A) ← (ROM(PC))3 to 0 When URS=1 (CY) ← (ROM(PC)) 8 (B) ← (ROM(PC))7 to 4 (A) ← (ROM(PC))3 to 0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 Ba Branch operation BL p, a (PCL) ← a 6–a 0 (PCH) ← p (PCL) ← a 6–a 0 BA a BLA p, a (PCL) ← (a6–a4, A 3– A0) (PCH) ← p (PCL) ← (a6–a4, A 3– A0) TDA LXY x, y RAM addresses BM a (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← 2 (PCL) ← a 6–a 0 AM AMC (A) ← (A) + (M(DP)) (A) ← (A) + (M(DP)) + (CY) (CY) ← Carry Subroutine operation BML p, a INY DEY TAM j (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p p= 0 to 7 (PCL) ← a 6–a 0 (A) ← (A) + n n = 0 to 15 (CY) ← 1 (CY) ← 0 BMLA p, (SP) ← (SP) + 1 (SK(SP)) ← (PC) a (PCH) ← p p= 0 to 7 (PCL) ← (a6–a4, A 3– A0) SC RC SZC CMA Return operation RT (PC) ← (SK(SP)) (SP) ← (SP) – 1 (CY) = 0 ? (A) ← (A) → CY → A3A2A 1A 0 Logic operation instruction XOR, OR, AND (Mj(DP)) ← 1 j = 0 to 3 RAM to register transfer RTS (PC) ← (SK(SP)) (SP) ← (SP) – 1 RB j (Mj(DP)) ← 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 SZB j 23 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS LIST OF INSTRUCTION FUNCTION (CONTINUED) Grouping Mnemonic TV1A TAB1 Function (V12–V10) ← (A2–A0) (B) ← (T17–T14) (A) ← (T13–T10) Grouping Mnemonic NOP POF SNZP Function (PC) ← (PC) + 1 RAM back-up (P) = 1 ? STCK changes to f(XIN) (LO1, LO0) ← (A1, A0) (URS) ← 1 (PU0 2– PU00) ← (A2–A0) (WDF1) ← 0 T1AB at timer 1 stop (V10=0): Other operation (R17–R1 4) ← (B) (T17–T14) ← (B) (R13–R1 0) ← (A) (T13–T10) ← (A) at timer 1 operating: (V10=1) (R17–R1 4) ← (B) (R13–R1 0) ← (A) WRST CCK TLOA URSC TPU0A Timer operation SNZ1 (T1F) = 1 ? After skipping the next instruction (T1F) ← 0 control operation TCA (C 2–C0) ← (A2–A0) (CARR) ← 0 Carrier wave TAC OCRA CLD RD (A 2–A 0) ← (C2–C0) (CARR) ← (A3) (D) ← 1 (D(Y)) ← 0 (Y) = 0 to 7 (D(Y)) ← 1 (Y) = 0 to 7 SD Input/Output operation SZD (D(Y)) = 0 ? (Y) = 7 OEA IAE OGA IAG (E 1, E 0) ← (A1, A0) (A 2–A 0) ← (E2–E0) (G) ← (A) (A) ← (G) 24 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS INSTRUCTION CODE TABLE D8–D4 D3– D0 Hex. notation 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 00 NOP BA 01 BLA CLD 02 SZB 0 SZB 1 SZB 2 SNZP INY RD SD RC SC SZB 3 SZD 03 BL BL 04 05 06 XAM 0 XAM 1 XAM 2 XAM 3 RT RTS IAE T1AB TAB1 TLOA CCK TCA TAM 0 TAM 1 TAM 2 TAM 3 XAMI 0 XAMI 1 XAMI 2 XAMI 3 XAMD 0 XAMD 1 XAMD 2 XAMD 3 TPU0A 10000 11000 10111 11111 10–17 18–1F BM BM BM B B B B 07 BML BML BML BML BML BML 08 09 0A A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 10 A 11 A 12 A 13 A 14 A 15 0B LA 0 LA 1 LA 2 LA 3 LA 4 LA 5 LA 6 LA 7 LA 8 LA 9 LA 10 LA 11 LA 12 LA 13 LA 14 LA 15 0C LXY 0,0 LXY 0,1 LXY 0,2 LXY 0,3 LXY 0,4 LXY 0,5 LXY 0,6 LXY 0,7 LXY 0,8 LXY 0,9 LXY 0,10 LXY 011 LXY 0,12 LXY 0,13 LXY 0,14 LXY 0,15 0D LXY 1,0 LXY 1,1 LXY 1,2 LXY 1,3 LXY 1,4 LXY 1,5 LXY 1,6 LXY 1,7 LXY 1,8 LXY 1,9 LXY 1,10 LXY 1,11 LXY 1,12 LXY 1,13 LXY 1,14 LXY 1,15 0E LXY 2,0 LXY 2,1 LXY 2,2 LXY 2,3 LXY 2,4 LXY 2,5 LXY 2,6 LXY 2,7 LXY 2,8 LXY 2,9 LXY 2,10 LXY 2,11 LXY 2,12 LXY 2,13 LXY 2,14 LXY 2,15 0F LXY 3,0 LXY 3,1 LXY 3,2 LXY 3,3 LXY 3,4 LXY 3,5 LXY 3,6 LXY 3,7 LXY 3,8 LXY 3,9 LXY 3,10 LXY 3,11 LXY 3,12 LXY 3,13 LXY 3,14 LXY 3,15 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F TAC BMLA LGOP SNZT1 OGA TABP 0 TABP 1 URSC TABP 2 TABP 3 OEA TABP 4 TABP 5 TABP 6 TABP 7 BL BL BM BM BM BM BM BM BM BL BL BL B B B B B SEAn SEAM BML OCRA BML DEY IAG TDA BL B B B B B B B AM AMC TYA TEAB TABE BM BM BM BM BM BM TV1A CMA RAR TAB SZC RB 0 RB 1 RB 2 RB 3 SB 0 SB 1 SB 2 SB 3 POF TBA WRST TAY The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-order 4 bits of the machine language code, and D8–D4 show the high-order 5 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use the code marked “–.” The codes for the second word of a two-word instruction are described below. The second word BL BML BA BLA BMLA SEA SZD 1 1 1 1 1 0 0 1aaa 0aaa 1aaa 1aaa 0aaa 1011 0010 aaaa aaaa aaaa 0ppp 0ppp nnnn 1011 25 MITSUBISHI MICROCOMPUTERS MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS MACHINE INSTRUCTIONS Parameter Instruction code Mnemonic D 8 D 7 D6 D5 D4 D 3 D 2 D1 D0 TAB TBA TAY TYA TEAB TABE TDA LXY x, y 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 0 1 1 0 0 0 1 0 0 0 1 Hexadecimal notation Function Skip condition Carry flag CY Number of words Number of cycles Detailed description Type of instructions 01 00 01 E E F 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) (ER7–ER 4) ← (B) (ER3–ER0) ← (A) (B) ← (ER7–ER 4) (A) ← (ER3–ER 0) (DR2–DR 0) ← (A2–A0) (X) ← x, x = 0 to 3 (Y) ← y, y = 0 to 15 – – – – – – – Continuous description – – – – – – – – Transfers the contents of register B to register A. Transfers the contents of register A to register B. Transfers the contents of register Y to register A. Transfers the contents of register A to register Y. Transfers the contents of registers A and B to register E. Transfers the contents of register E to registers A and B. Transfers the contents of register A to register D. Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. Register to register transfer 00C 01 02 02 A A 9 x1 x0 y3 y2 y1 y0 0Cy +x RAM addresses INY 0 0 0 0 1 0 0 1 1 01 3 1 1 (Y) ← (Y) + 1 (Y) = 0 – Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. DEY 0 0 0 0 1 0 1 1 1 017 1 1 (Y) ← (Y) – 1 (Y) = 15 – TAM j 0 0 1 1 0 0 1 j1 j0 06 4 +j 1 1 (A) ← (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 – – After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. XAM j RAM to register transfer 0 0 1 1 0 0 0 j1 j0 06 j 1 1 (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 – – After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. XAMD j 0 0 1 1 0 1 1 j1 j0 06C +j 1 1 (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (Y) ← (Y) – 1 (Y) = 15 – After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. XAMI j 0 0 1 1 0 1 0 j1 j0 06 8 +j 1 1 (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (Y) ← (Y) + 1 (Y) = 0 – After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. 26 27 MITSUBISHI MICROCOMPUTERS MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS MACHINE INSTRUCTIONS (CONTINUED) Parameter Instruction code Mnemonic D 8 D 7 D6 D5 D4 D 3 D 2 D1 D0 LA n 0 1 0 1 1 n3 n 2 n 1 n 0 Hexadecimal notation Function Skip condition Carry flag CY Number of words Number of cycles Detailed description Type of instructions 0B n 1 1 (A) ← n n = 0 to 15 Continuous description – Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. TABP p 0 1 0 0 1 0 p2 p1 p0 09 p 1 3 (SK(SP)) ← (PC) (SP) ← (SP) + 1 (PCH) ← p, p=0 to 7 (PCL) ← (DR2–DR 0, A3–A0) When URS=0, (B) ← (ROM(PC))7 to 4 (A) ← (ROM(PC))3 to 0 When URS=1, (CY) ← (ROM(PC))8 (B) ← (ROM(PC))7 to 4 (A) ← (ROM(PC))3 to 0 (SP) ← (SP) – 1 (PC) ← (SK(SP)) – – Transfers bits 7 to 4 to register B and bits 3 to 0 to register A when URS flag is cleared to “0.” These bits 7 to 0 are the ROM pattern in address (DR2 DR 1 DR 0 A3 A2 A1 A0) specified by registers A and D in page p. 0/1 When this instruction is executed, 1 stage of stack register is used. Transfers bit 8 of ROM pattern is transferred to flag CY when URS flag is set to “1” (after the URSC instruction is executed). One of stack is used when the TABP p instruction is executed. AM Arithmetic operation 0 0 0 0 0 1 0 1 0 00 A 1 1 (A) ← (A) + (M(DP)) – – Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged. AMC 0 0 0 0 0 1 0 1 1 00 B 1 1 (A) ← (A) + (M(DP))+ (CY) (CY) ← Carry (A) ← (A) + n n = 0 to 15 – 0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. – Adds the value n in the immediate field to register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. An 0 1 0 1 0 n3 n 2 n 1 n 0 0A n 1 1 Overflow = 0 SC RC SZC CMA RAR LGOP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 0 0 0 1 0 1 0 1 1 00 00 02 01 01 04 7 6 F C D 1 1 1 1 1 1 1 1 1 1 1 1 1 (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) → CY → A 3A 2A1A 0 Logic operation instruction XOR, OR, AND – – (CY) = 0 – – – 1 0 – – Sets (1) to carry flag CY. Clears (0) to carry flag CY. Skips the next instruction when the contents of carry flag CY is “0.” Stores the one‘s complement for register A‘s contents in register A. 0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. – Execute the logic operation selected by logic operation selection register LO between the contents of register A and register E, and stores the result in register A. 28 29 MITSUBISHI MICROCOMPUTERS MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS MACHINE INSTRUCTIONS (CONTINUED) Parameter Instruction code Mnemonic D 8 D 7 D6 D5 D4 D 3 D 2 D1 D0 SB j 0 0 1 0 1 1 1 j1 j0 Hexadecimal notation Function Skip condition Carry flag CY Number of words Number of cycles Detailed description Type of instructions 05 C +j 1 1 (Mj(DP)) ← 1 j = 0 to 3 – – Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Bit operation RB j 0 0 1 0 0 1 1 j1 j0 04 C +j j 1 1 (Mj(DP)) ← 0 j = 0 to 3 – – Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). SZB j 0 0 0 1 0 0 0 j1 j0 02 1 1 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15 (Mj(DP)) = 0 j = 0 to 3 (A) = (M(DP)) (A) = n n = 0 to 15 – Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0.” SEAM Comparison operation SEA n 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 02 02 6 5 1 2 1 2 – – Skips the next instruction when the contents of register A is equal to the contents of M(DP). Skips the next instruction when the contents of register A is equal to the value n in the immediate field. n3 n 2 n 1 n 0 0B n 1 8 +a a 1 1 (PCL) ← a6–a0 – – Branch within a page : Branches to address a in the identical page. Ba 1 a 6 a 5 a4 a3 a 2 a 1 a 0 BL p, a 0 0 0 1 1 p3 p 2 p 1 p 0 03 p 2 2 (PCH) ← p (PCL) ← a6–a0 (Note) – – Branch out of a page : Branches to address a in page p. Branch operation 1 1 a 6 a 5 a4 a3 a 2 a 1 a 0 18 a +a 00 1 2 2 (PCL) ← (a6–a4, A3–A0) – – Branch within a page : Branches to address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the loworder 4 bits of the address a in the identical page with register A. BA a 0 1 0 1 0 0 0 0 0 0 1 a 6 a 5 a4 a3 a 2 a 1 a 0 18 a +a 01 0 2 2 (PCH) ← p (PCL) ← (a6–a4, A3–A0) (Note) – – Branch out of a page : Branches to address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the loworder 4 bits of the address a in page p with register A. BLA p, a 0 1 0 1 0 0 1 0 0 0 0 a 6 a 5 a4 p3 p 2 p 1 p 0 18 p +a Note : p is 0 to 7 for M34280E1, and p is 0 to 7 for M34280M1. 30 31 MITSUBISHI MICROCOMPUTERS MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS MACHINE INSTRUCTIONS (CONTINUED) Parameter Instruction code Mnemonic D 8 D 7 D6 D5 D4 D 3 D 2 D1 D0 BM a 1 0 a 6 a 5 a4 a3 a 2 a 1 a 0 Hexadecimal notation Function Skip condition Carry flag CY Number of words Number of cycles Detailed description Type of instructions 1 a a 1 1 (SK(SP)) ← (PC) (SP) ← (SP) + 1 (PCH) ← 2 (PCL) ← a 6–a0 – – Call the subroutine in page 2 : Calls the subroutine at address a in page 2. Subroutine operation BML p, a 0 0 1 1 1 p3 p 2 p 1 p 0 07 p 2 2 (SK(SP)) ← (PC) (SP) ← (SP) + 1 (PCH) ← p – – Call the subroutine : Calls the subroutine at address a in page p. 1 0 a 6 a 5 a4 a3 a 2 a 1 a 0 1aa (PCL) ← a 6–a0 (Note) 2 2 (SK(SP)) ← (PC) (SP) ← (SP) + 1 (PCH) ← p (PCL) ← (a 6–a4, A3–A0) (Note) – – Call the subroutine : Calls the subroutine at address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the low-order 4 bits of address a in page p with register A. BMLA p, a 0 1 0 0 1 0 1 0 0 0 0 05 1a 0 p a 6 a 5 a4 p3 p 2 p 1 p 0 Return operation RT 0 0 1 0 0 0 1 0 0 04 4 1 2 (PC) ← (SK(SP)) (SP) ← (SP) – 1 – – Returns from subroutine to the routine called the subroutine. RTS 0 0 1 0 0 0 1 0 1 04 5 1 2 (PC) ← (SK(SP)) (SP) ← (SP) – 1 Skip at uncondition – Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition. TAB1 0 0 1 0 1 0 1 1 1 057 1 1 (B) ← (T17–T14) (A) ← (T13–T10) – – Transfers the contents of timer 1 to registers A and B. T1AB Timer operation 0 0 1 0 0 0 1 1 1 047 1 1 at timer 1 stop (V10=0) (R17–R1 4) ← (B), (R1 3–R10) ← (A) (T17–T14) ← (B), (T13–T10) ← (A) at timer 1 operating (V1 0=1) (R17–R1 4) ← (B), (R1 3–R10) ← (A) – – Transfers the contents of registers A and B to timer 1. TV1A SNZ1 0 0 0 0 1 1 0 0 1 0 1 0 0 0 1 1 1 0 05B 042 1 1 1 1 (V12–V10) ← (A2–A0) (T1F) = 1 ? After skipping the next instruction (T1F) ← 0 – (T1F) = 1 – – Transfers the contents of register A to registers V1. Skips the next instruction when the contents of T1F flag is “1.” After skipping, clears (0) to T1F flag. control operation TAC TCA OCRA 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 040 05A 086 1 1 1 1 1 1 (A 2–A 0) ← (C2–C0) (C 2–C0) ← (A2–A0), (CARR) ← 0 (CARR) ← (A3) – – – – – – Transfers the contents of register A to register C. Transfers the contents of register C to register A. In this case, port CARR output latch is cleared to “0.” Transfers the contents of bit 3 (A3) of register A to port CARR output latch. Note : p is 0 to 7 for M34280E1, and p is 0 to 7 for M34280M1. 32 Carrier wave 33 MITSUBISHI MICROCOMPUTERS MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS MACHINE INSTRUCTIONS (CONTINUED) Parameter Instruction code Mnemonic D 8 D 7 D6 D5 D4 D 3 D 2 D1 D0 CLD RD 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 Hexadecimal notation Function Skip condition Carry flag CY Number of words Number of cycles Detailed description Type of instructions 011 014 1 1 1 1 (D) ← 0 (D(Y)) ← 0 (Y) = 0 to 7 – – – – Clears (0) to port D (high-impedance state). Clears (0) to a bit of port D specified by register Y (high-impedance state). SD Input/Output operation 0 0 0 0 1 0 1 0 1 015 1 1 (D(Y)) ← 1 (Y) = 0 to 7 – – Sets (1) to a bit of port D specified by register Y. SZD 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 1 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 1 024 02B 084 056 080 028 00 00 0 D 2 2 (D(Y)) = 0 ? (Y) = 7 (D(Y)) = 0 (Y) = 7 – Skips the next instruction when a bit of port D specified by register Y is “0.” OEA IAE OGA IAG NOP POF 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 (E 1, E0) ← (A1, A 0) (A 2–A0) ← (E2–E0) (G) ← (A) (A) ← (G) (PC) ← (PC) + 1 RAM back-up – – – – – – – – – – – – Outputs the contents of register A to port E. Transfers the contents of port E to register A. Outputs the contents of register A to port G. Transfers the contents of port G to register A. No operation Puts the system in RAM back-up state. SNZP 0 0 0 0 0 0 0 1 1 00 3 1 1 (P) = 1 ? (P) = 1 – Skips the next instruction when P flag is “1.” After skipping, P flag remains unchanged. Other operation CCK 0 0 1 0 1 1 0 0 1 05 9 1 1 STCK changes to f(X IN) – – System clock (STCK) changes to f(XIN) from f(XIN)/8. Execute this CCK instruction at address 0 in page 0. Transfers the contents of register A to the logic operation selection register LO. Sets the most significant ROM code reference enable flag (URS) to “1.” Transfers the contents of register A to register PU0. Initializes the watchdog timer flag (WDF1). TLOA URSC TPU0A WRST 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 0 1 1 0 1 1 1 0 0 1 1 05 08 08 00 8 2 F F 1 1 1 1 1 1 1 1 (LO1, LO0) ← (A1, A0) (URS) ← 1 (PU0 2–PU00) ← (A2–A0) (WDF1) ← 0 – – – – – – – – 34 35 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS CONTROL REGISTERS Timer control register V1 V12 V11 V10 Carrier wave output auto-control bit Timer 1 count source selection bit Timer 1 control bit 0 1 0 1 0 1 at reset : 0002 at RAM back-up : 0002 W Auto-control output by timer 1 is invalid Auto-control output by timer 1 is valid Carrier output (CARRY) Bit 5 of watchdog timer (WDT) Stop (Timer 1 state retained) Operating Pull-down control register PU0 PU0 2 PU0 1 PU0 0 Port D7 pull-down control bit Port E 1 pull-down control bit Port E 0 pull-down control bit 0 1 0 1 0 1 at reset : 0002 at RAM back-up : state retained W Pull-down transistor OFF, input circuit OFF, key-on wakeup invalid Pull-down transistor ON, input circuit ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Carrier wave selection register C C2 at reset : 1112 C2 C1 C0 000 001 010 011 100 101 Frequency System clock/12 System clock/12 System clock/8 System clock/8 System clock at RAM back-up : 1112 Carrier wave Duty 1/3 1/2 1/4 1/2 1/2 No carrier wave 1/2 “L” level fixed R/W C1 Carrier wave selection bits C0 110 111 f(XIN)/4 (Note 2) Logic operation selection register LO at reset : 002 at RAM back-up : 002 W LO1 Logic operation selection bits LO0 LO1 L O0 Logic operation function 0 0 Exclusive logic OR operation (XOR) 0 1 OR operation (OR) 1 0 AND operation (AND) 1 1 Not available Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: f(XIN ) is valid only when f(XIN)/8 is selected as the system clock. 36 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS ABSOLUTE MAXIMUM RATINGS Symbol VDD VI VO Pd Topr Tstg Supply voltage Input voltage Output voltage Power dissipation Operating temperature range Storage temperature range Ta = 25 °C Parameter Conditions Ratings –0.3 to 5 –0.3 to VDD+0.3 –0.3 to VDD+0.3 300 –20 to 85 –40 to 125 Unit V V V mW °C °C RECOMMENDED OPERATING CONDITIONS (Ta = –20 °C to 85 °C, VDD = 1.8 V to 3.6 V, unless otherwise noted) Symbol VDD VRAM VSS VIH VIH VIL VIL Parameter Supply voltage RAM back-up voltage (at RAM back-up mode) Supply voltage “H” level input voltage Ports D7, E, G “H” level input voltage XIN “L” level input voltage Ports D7, E, G “L” level input voltage XIN VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V Limits Conditions Min. 1.8 1.4 0 0.7VDD 0.8VDD 0 0 VDD VDD 0.2VDD Typ. Max. 3.6 3.6 Unit V V V V V V IOH(peak) “H” level peak output current Ports D, E1, G IOH(peak) “H” level peak output current Port E0 IOH(peak) “H” level peak output current CARR IOL(peak) “L” level peak output current CARR IOH (avg) “H” level average output current Ports D, E1, G IOH (avg) “H” level average output current Port E0 IOH (avg) “H” level average output current CARR IOL (avg) “L” level average output current CARR f(XIN) VDET TDET TPON System clock frequency 0.2VDD V –4 mA –24 mA –20 mA 4 –2 –12 –10 2 4 mA mA mA mA mA MHz kHz V ms ms when STCK = f(XIN)/8 selected Ceramic resonance when STCK = f(XIN ) selected Ceramic resonance 1.10 Ta=25 °C Supply voltage is -10V/s and drops under detected voltage. VDD = 0 to 2.2 V 1.40 1.50 0.16 500 1.80 1.56 1.2 1 Voltage drop detection circuit detection voltage Voltage drop detection circuit low voltage determination time Power-on reset circuit valid power source rising time Note: The average output current ratings are the average current value during 100 ms. 37 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS ELECTRICAL CHARACTERISTICS (Ta = –20 °C to 85 °C, VDD = 3 V, unless otherwise noted) Symbol V OL V OH V OH V OH IIL IIH IOZ Parameter “L” level output voltage Port CARR “H” level output voltage Ports D, E1, G “H” level output voltage Port E0 “H” level output voltage CARR “L” level input current Ports D7, E, G “H” level input current Ports E0, E1 Output current at off-state Ports D, E0, E1 Supply current (when operating) IDD Supply current (at RAM back-up) R PH R OSC Pull-down resistor value Ports D7, E, G Feedback resistor value between XIN–X OUT Ta = 25 °C V DD = 3 V, VI = 3 V 75 700 Test conditions IOL = 2 mA IOH = –2 mA IOH = –12 mA IOH = –10 mA V I = V SS V I = V DD Pull-down transistor in off-state V O = V SS f(XIN ) = 4.0 MHz f(XIN ) = 500 kHz 400 350 1 0.1 150 2.1 1.5 1.0 –1 1 –1 800 700 3 0.5 300 3200 Limits Min. Typ. Max. 0.9 Unit V V V V µA µA µA µA µA µA kΩ kΩ BASIC TIMING DIAGRAM Machine cycle Pin name STCK D0–D7,E0,E1 G0–G3 D7 E0–E2 G0–G3 Mi Mi+1 Parameter System clock Ports D, E0, E1, G output Ports D7, E, G input 38 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS BUILT-IN PROM VERSION In addition to the mask ROM versions, the 4280 Group has the One Time PROM versions whose PROMs can only be written to and not be erased. The built-in PROM version has functions similar to those of the mask ROM versions, but it has PROM mode that enables writing to built-in PROM. Table 10 Product of built-in PROM version PROM size Product (! 9 bits) M34280E1FP 1024 words M34280E1GP 1024 words Table 10 shows the product of built-in PROM version. Figure 26 and 27 show the pin configurations of built-in PROM versions. The One Time PROM version has pin-compatibility with the mask ROM version. RAM size (! 4 bits) 32 words 32 words Package 20P2N-A 20P2E/F-A ROM type One Time PROM [shipped in blank] One Time PROM [shipped in blank] PIN CONFIGURATION (TOP VIEW) VSS E2 E1 XIN XOUT E0 G0 G1 G2 G3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD CARR D0 D1 D2 D3 D4 D5 D6 D7 Outline 20P2N-A 20P2E/F-A Fig. 26 Pin configuration of built-in PROM version M34280E1FP/GP 39 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS (1) PROM mode (serial input/output) The M34280E1FP/GP has a PROM mode in addition to a normal operation mode. It has a function to serially input/output the command codes, addresses, and data required for operation (e.g., read and program) on the built-in PROM using only a few pins. This mode can be selected by setting pins SDA (serial data input/output), SCLK (serial clock input), PGM and VPP to “H” after connecting wires as shown in Figure 1 and powering on the VDD pin, and then applying 12.5V to the VPP pin. In the PROM mode, three types of software commands (read, program, and program verify) can be used. Clock-synchronous serial I/O is used, beginning from the LSB (LSB first). Refer to the Mitsubishi Data Book “DEVELOPMENT SUPPORT TOOLS FOR MICROCOMPUTERS” about the serial programmer for the Mitsubishi single-chip microcomputers. PIN CONFIGURATION (TOP VIEW) Vss Vpp VSS E2 E1 1 2 3 4 5 6 20 VDD 19 CARR 18 D0 17 D1 16 D2 15 D3 14 D4 13 D5 12 D6 11 D7 VDD M34280E1FP/GP ∗ SCLK XIN XOUT E0 SDA G0 7 G1 8 G2 9 G3 10 PGM Outline 20P2N-A 20P2E/F-A ∗ : connected to the ceramic resonance circuit Note: The state of disconnected pins are the same as that at reset. Fig. 27 Pin configuration of built-in PROM version (continued) 40 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS (2) Functional outline In the PROM mode, data is transferred with the clocksynchronous serial input/output. The input data is read through the SDA pin into the internal circuit synchronously with the rising edge of the serial clock pulse. The output data is output from the SDA pin synchronously with the falling edge of the serial clock pulse. Data is transferred in units of 8 bits. Table 11 Software command Number of transfer First command Command Read Program Program verify Number of transfer Command Read Program Program verify code input 1516 2516 3516 In the first transfer, the command code is input. Then, address input or data input/output is performed according to the contents of the command code. Table 11 shows the software command used in the PROM mode. The following explains each software command. Second Read address L (input) Program address L (input) Program address L (input) Third Read address H (input) Program address H (input) Program address H (input) Fourth Read data L (output) Program data L (input) Program data L (input) Fifth Read data H (output) Program data H (input) Program data H (input) Sixth Seventh Verify data L (output) Verify data H (output) (3) Read Input the command code 1516 in the first transfer. Proceed and input the low-order 8 bits and the high-order 8 bits of the address and pull the PGM pin to “L.” When this is done, the contents of input address is read and stored into the internal data latch. When the PGM pin is released back to “H” and serial clock is input to the SCLK pin, the low-order 8 bits and high-order 8 bits of read data which have been stored into the data latch, are serially output from the SDA pin. tCH SCLK A0 A7 tCH tCH SDA 1 010 10 00 A8 A9 0 00 00 0 D0 D7 D8 00 00 00 0 Command code input (1516) Read address input (L) Read address input (H) tCR tWR tRC Read data output (L) Read data output (H) PGM Read Note: When outputting the read data, the SDA pin is switched for output at the first falling of the serial clock. The SDA pin is placed in the high-impedance state during the th(C–E) period after the last rising edge of the serial clock (at the 16th bit). Fig. 28 Timing at reading 41 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS (4) Program Input command code 25 16 in the first transfer. Proceed and input the low-order 8 bits and high-order 8 bits of the address and the low-order 8 bits and high-order 8 bits of program data, and pull the PGM pin to “L.” When this is done, the program data is programmed to the specified address. tCH SCLK A0 A7 tCH tCH tCH SDA 1 0100 10 0 A8 A9 0 00 000 D0 D7 D8 0 000 000 Command code input (2516) Program address input (L) Program address input (H) Program data input (L) Program data input (H) tCP tWP PGM Program Fig. 29 Timing at programming (5) Program verify Input command code 35 16 in the first transfer. Proceed and input the low-order 8 bits and high-order 8 bits of the address and the low-order 8 bits and high-order 8 bits of program data, and pull the PGM pin to “L.” When this is done, the program data is programmed to the specified address. Then, when the PGM pin is pulled to “L” again after it is released back to “H,” the address programmed with the program command is read and verified and stored into the internal data latch. When the PGM pin is released back to “H” and serial clock is input to the SCLK pin, the verify data that has been stored into the data latch is serially output from the SDA pin. tCH SCLK A0 A7 tCH tCH tCH SDA 1 0101 10 0 A8 A9 0 00 000 D0 D7 D8 0 000 00 0 Command code input (3516) Program address input (L) Program address input (H) Program data input (L) Program data input (H) tCP tWP PGM Program tCH SCLK D0 D7 D8 00 00 00 0 SDA tCR PGM Verify tWR tRC Verify data output (L) Verify data output (H) Note: When outputting the verify data, the SDA pin is switched for output at the first falling of the serial clock. The SDA pin is placed in the high-impedance state during the th(C–E) period after the last rising edge of the serial clock (at the 16th bit). Fig. 30 Timing at program verifying 42 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS PROGRAM ALGORITHM FLOW CHART START VDD = 4V,VPP = 4V VDD = 4V,VPP = 12.5V ADRS = first location X=0 WRITE PROGRAM-VERIFY COMMAND 3516 WRITE PROGRAM DATA DIN PROGRAM ONE PULSE OF 0.2ms X=X+1 YES X = 25? NO FAIL VERIFY BYTE? PASS PASS WRITE PROGRAM COMMAND 2516 VERIFY BYTE? FAIL WRITE PROGRAM DATA DIN PROGRAM PULSE OF 0.2Xms DURATION INC ADRS NO LAST ADRS? YES READ COMMAND 1516 VERIFY ALL BYTE? PASS FAIL DEVICE FAILED DEVICE PASSED 43 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS TIMING REQUIREMENT CONDITION AND SWITCHING CHARACTERISTICS (Ta = 25 °C, VDD = 4.0 V, VPP = 12.5 V) Symbol tCH tCR tWR tRC tCP tWP tOWP tC(CK) tW(CKH) tW(CKL) tr(CK) tf(CK) td(C–Q) th(C–Q) th(C–E) tsu(D–C) th(C–D) Parameter Serial transfer width time Read wait time after transfer Read pulse width Transfer wait time after read Program wait time after transfer Program pulse width Added program pulse width SCLK input cycle time SCLK “H” pulse width SCLK “L” pulse width SCLK rising time SCLK falling time SDA output delay time SDA output hold time SDA output hold time (only for 16th bit) SDA input set-up time SDA input hold time Limits Min. Max. 2.0 2.0 500 2.0 2.0 0.19 0.19 1.0 450 450 40 40 0 0 100 60 180 180 0.21 5.25 Unit µs µs ns µs µs ms ms µs ns ns ns ns ns ns ns ns ns TIMING DIAGRAM tf(CK) tW(CKL) SCLK td(C-Q) SDA output tr(CK) tC(CK) tW(CKH) th(C-Q) th(C-E) tsu(D-C) SDA input th(C-D) Measurement condition Output timing voltage: VOL = 0.8 V, VOH = 2.0 V Input timing voltage: VIL = 0.2 VDD, VIH = 0.8 VDD 44 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS (6) Notes on handling Œ A high-voltage is used for writing. Take care that overvoltage is not applied. Take care especially at turning on the power.  For the M34280E1FP/GP, Mitsubishi Electric corp. does not perform PROM writing test and screening in the assembly process and following processes. In order to improve reliability after writing, performing writing and test according to the flow shown in Figure 31 before using is recommended. Writing with PROM programmer Screening (Leave at 150 °C for 40 hours) (Note) Verify test with PROM programmer Function test in target device Note: Since the screening temperature is higher than storage temperature, never expose the microcomputer to 150 °C exceeding 100 hours. Fig. 31 Flow of writing and test of the product shipped in blank 45 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS GZZ-SH54-86B 720 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34280M1-XXXFP/GP MITSUBISHI ELECTRIC P lease fill in all items marked V . Mask ROM number Date: Receipt Issuance signature 27C512 Low-order 8-bit data 000016 1.00K 03FF16 100016 1.00K 13FF16 FFFF16 Most significant bit data Section head S u p e r v i s o r signature signature Company name V Customer Responsible Supervisor officer TEL ( Date issued Date: ) V 1. Confirmation Specify the name of the product being ordered (check in the approximate box). Three sets of EPROMs are required for each pattern if this order is performed by EPROMs. One floppy disk is required for each pattern if this order is performed by floppy disk. Microcomputer name: M34280M1-XXXFP M34280M1-XXXGP Ordering by the EPROMs Specify the type of EPROMs submitted (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM area (hexadecimal notation) EPROM Type: 27C64 Low-order 8-bit data 0000 16 1.00K 03FF 16 1000 16 1.00K 13FF 16 1FFF 16 27C128 Low-order 8-bit data 0000 16 1.00K 03FF 16 1000 16 1.00K 13FF 16 3FFF 16 27C256 Low-order 8-bit data 000016 1.00K 03FF16 100016 1.00K 13FF16 7FFF16 Most significant bit data Most significant bit data Most significant bit data Set “FF 16” in the shaded area. 46 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS GZZ-SH54-86B 720 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34280M1-XXXFP/GP MITSUBISHI ELECTRIC Mask ROM number Ordering by floppy disk We will produce masks based on the mask files generated by the mask file generating utility. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this mask file. Thus, extreme care must be taken to verify the mask file in the submitted floppy disk. The submitted floppy disk must be-3.5 inch 2HD type and DOS/V format. And the number of the mask files must be 1 in one floppy disk. File code Mask file name (hexadecimal notation) .MSK (equal or less than eight characters) ₎ 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (20P2N-A for M34280M1-XXXFP, 20P2E/F-A for M34280M1-XXXGP) and attach to the Mask ROM Order Confirmation Form. ₎ 3. Comments 47 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS PACKAGE OUTLINE 20P2N-A EIAJ Package Code SOP20-P-300-1.27 20 Plastic 20pin 300mil SOP JEDEC Code – Weight(g) 0.26 11 Lead Material Cu Alloy e b2 HE E e1 Recommended Mount Pad Symbol 1 10 F A G D b A2 x M A1 e y A A1 A2 b c D E e HE L L1 z Z1 x y b2 e1 I2 c z Z1 Detail G Detail F Dimension in Millimeters Min Nom Max 2.1 – – 0.2 0.1 0 – 1.8 – 0.5 0.4 0.35 0.25 0.2 0.18 12.7 12.6 12.5 5.4 5.3 5.2 – 1.27 – 8.1 7.8 7.5 0.8 0.6 0.4 – 1.25 – – 0.585 – – – 0.735 – – 0.25 0.1 – – 0° – 8° – 0.76 – – 7.62 – – 1.27 – L1 20P2E/F-A EIAJ Package Code SSOP20-P-225-0.65 JEDEC Code – Weight(g) 0.08 Lead Material Alloy 42/Cu Alloy L Plastic 20pin 225mil SSOP e b2 20 11 HE E F Recommended Mount Pad Symbol 1 10 e1 A G D b e x M A2 A1 y c z Z1 Detail G Detail F A A1 A2 b c D E e HE L L1 z Z1 x y b2 e1 I2 Dimension in Millimeters Min Nom Max 1.45 – – 0.2 0.1 0 – 1.15 – 0.32 0.22 0.17 0.2 0.15 0.13 6.6 6.5 6.4 4.5 4.4 4.3 – 0.65 – 6.6 6.4 6.2 0.7 0.5 0.3 – 1.0 – – 0.325 – – – 0.475 – – 0.13 0.1 – – 0° – 10° – 0.35 – – 5.8 – – 1.0 – L1 48 L I2 I2 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS 20P2N-A (20-PIN SOP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if neede d). A. Standard Mitsubishi Mark 20 11 Mitsubishi IC catalog name Mitsubishi lot number (6-digit or 7-digit) Mitsubishi IC catalog name 1 10 B. Customer’s Par ts Number + Mitsubishi IC Catalog Name 20 11 Mask ROM number (3-digit) Mitsubishi lot number (6-digit or 7-digit) Customer’s Par ts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name and Mitsubishi lot number Notes 1 : The mark field should be wr itten right aligned. 2 : T he fonts and siz e of characters are standard Mitsubishi type. 3 : Customer’s Par ts Number can be up to 13 characters: Only 0 to 9, A to Z, +, -, /, (, ), &, ©, . (period), and , (comma) are usable. 1 10 C. Special Mark Required 20 11 Mask ROM number (3-digit) Mitsubishi lot number (6-digit or 7-digit) Note 1 : If the Special Mark is to be Printed, indicate the desired layout of the mar k in the left figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit, or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer’s trade mar k logo must be used in the Special Mar k, check the box below. Please submit a clean original of the logo. For the new special character fonts, a clean font original (ideally logo drawing) must be submitted. Special logo required Special Mark (Customer’s Trade Mar k) Mitsubishi IC catalog name 1 10 49 MITSUBISHI MICROCOMPUTERS 4280 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS 20P2E/F-A (20-PIN SSOP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B), and enter the Mitsubishi IC catalog name and the special mark (if needed). A. Standard Mitsubishi Mark 20 11 Mitsubishi IC catalog name Mitsubishi lot number (4-digit or 5-digit) Mitsubishi IC catalog name 1 10 B. Customer’s Par ts Number + Mitsubishi IC Catalog Name 20 11 ROM number (3-digit) Mitsubishi lot number (4-digit or 5-digit) Customer’s Par ts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name and Mitsubishi lot number Mitsubishi IC catalog name and Mitsubishi lot number Notes 1 : The mark field should be wr itten right aligned. 2 : T he fonts and size of characters are standard Mitsubishi type. 3 : Customer’s Par ts Number can be up to 4 char acters: Only 0 to 9, A to Z, +, -, /, (, ), &, ©, . (period), and , (comma) are usable. 1 10 50 Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials • • • These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. • • • • © 1999 MITSUBISHI ELECTRIC CORP. Effective June. 1999. Specifications subject to change without notice. REVISION DESCRIPTION LIST Rev. No. 1.0 2.0 First Edition • 20P2E/F-A package added • Figure XA-2: A resistor is added 4280 GROUP DATA SHEET Revision Description Rev. date 980420 990611 (1/1)