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4501 - SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER - Renesas Technology Corp

型  号:
4501
大  小:
844.83KB 共116页
厂  商:
RENESAS[RenesasTechnologyCorp]
主  页:
http://www.renesas.com
功能介绍:
4501 - SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER - Renesas Technology Corp
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4501 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER REJ03B0104-0301 Rev.3.01 2005.02.07 DESCRIPTION The 4501 Group is a 4-bit single-chip microcomputer designed with CMOS technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with two 8-bit timers (each timer has a reload register), interrupts, and 10-bit A/D converter. The various microcomputers in the 4501 Group include variations of the built-in memory size as shown in the table below. q Timers Timer 1 ...................................... 8-bit timer with a reload register Timer 2 ...................................... 8-bit timer with a reload register q Interrupt ........................................................................ 4 sources q Key-on wakeup function pins ................................................... 12 q Input/Output port ...................................................................... 14 q A/D converter .................. 10-bit successive comparison method q Watchdog timer q Clock generating circuit (ceramic resonator/RC oscillation) q LED drive directly enabled (port D) qPower-on reset circuit q Voltage drop detection circuit ........................... VRST: Typ. 3.5 V (Ta = 25 °C) FEATURES q Minimum instruction execution time ................................ 0.68 µs (at 4.4 MHz oscillation frequency, in high-speed mode) q Supply voltage ............................................................. 2.7 to 5.5 V (System is in the reset state when the voltage is under the detection voltage of voltage drop detection circuit) APPLICATION Electrical household appliance, consumer electronic products, office automation equipment, etc. Part number M34501M2-XXXFP M34501M4-XXXFP M34501E4FP (Note) ROM (PROM) size (✕ 10 bits) 2048 words 4096 words 4096 words RAM size (✕ 4 bits) 128 words 256 words 256 words Package PRSP0020DA-A PRSP0020DA-A PRSP0020DA-A ROM type Mask ROM Mask ROM One Time PROM Note: Shipped in blank. Rev.3.01 2005.02.07 REJ03B0104-0301 page 1 of 112 4501 Group PIN CONFIGURATION VDD VSS XIN XOUT CNVSS RESET P21/AIN1 P20/AIN0 D3/K D2/C 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 P00 P01 P02 P03 P10 P11 P12/CNTR P13/INT D0 D1 Outline PRSP0020DA-A (20P2N-A) Pin configuration (top view) (4501 Group) M34501Mx-XXXFP M34501E4FP Rev.3.01 2005.02.07 REJ03B0104-0301 page 2 of 112 4501 Group Rev.3.01 2005.02.07 REJ03B0104-0301 4 4 2 4 BLOCK DIAGRAM Block diagram (4501 Group) I/O port Port P1 Port P2 Port D Port P0 page 3 of 112 System clock generating circuit XIN -XOUT Power-on reset circuit Voltage drop detection circuit Internal peripheral functions Timer Timer 1 (8 bits) Timer 2 (8 bits) Watchdog timer (16 bits) Memory ROM 2048, 4096 words ✕ 10 bits A/D converter (10 bits ✕ 2 ch) 4500 Series CPU core ALU (4 bits) Register A (4 bits) Register B (4 bits) Register E (8 bits) Register D (3 bits) Stack register SK (8 levels) Interrupt stack register SDP (1level) RAM 128, 256 words ✕ 4 bits 4501 Group PERFORMANCE OVERVIEW Parameter Number of basic instructions Minimum instruction execution time Memory sizes ROM M34501M2 M34501M4/E4 RAM M34501M2 M34501M4/E4 Input/Output D0–D3 I/O ports Function 111 0.68 µs (at 4.4 MHz oscillation frequency, in high-speed mode) 2048 words ✕ 10 bits 4096 words ✕ 10 bits 128 words ✕ 4 bits 256 words ✕ 4 bits Four independent I/O ports. Input is examined by skip decision. Ports D2 and D3 are equipped with a pull-up function and a key-on wakeup function. Both functions can be switched by software. Ports D2 and D3 are also used as ports C and K, respectively. 4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both functions can be switched by software. 4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both functions can be switched by software. Ports P12 and P13 are also used as CNTR and INT, respectively. 2-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both functions can be switched by software. Ports P20 and P21 are also used as AIN0 and AIN1, respectively. 1-bit I/O; Port C is also used as port D2. 1-bit I/O; Port K is also used as port D3. 1-bit I/O; CNTR pin is also used as port P12. 1-bit input; INT pin is also used as port P13. Two independent I/O ports. AIN0–AIN1 is also used as ports P20, P21, respectively. 8-bit programmable timer with a reload register. 8-bit programmable timer with a reload register and has a event counter. 10-bit wide, This is equipped with an 8-bit comparator function. 2 channel (AIN0 pin, AIN1 pin) 4 (one for external, two for timer, one for A/D) 1 level 8 levels CMOS silicon gate 20-pin plastic molded SOP (PRSP0020DA-A) –20 °C to 85 °C 2.7 to 5.5 V (System is in the reset state when the voltage is under the detection voltage of voltage drop detection circuit) 1.7 mA (Ta=25°C, VDD = 5.0 V, 4.0 MHz oscillation frequency, in high-speed mode, output transistors in the cut-off state) 0.1 µA (Ta=25°C, VDD = 5 V, output transistors in the cut-off state) P00–P03 I/O P10–P13 I/O P20, P21 I/O Timers A/D converter C K CNTR INT AIN0, AIN1 Timer 1 Timer 2 I/O I/O Timer I/O Interrupt input Analog input Analog input Sources Nesting Subroutine nesting Device structure Package Operating temperature range Supply voltage Interrupt Power Active mode dissipation (typical value) RAM back-up mode Rev.3.01 2005.02.07 REJ03B0104-0301 page 4 of 112 4501 Group PIN DESCRIPTION Pin VDD VSS CNVSS RESET Name Power supply Ground CNVSS Reset input/output Input/Output — — — I/O Function Connected to a plus power supply. Connected to a 0 V power supply. Connect CNVSS to VSS and apply “L” (0V) to CNVSS certainly. An N-channel open-drain I/O pin for a system reset. When the watchdog timer, the built-in power-on reset or the voltage drop detection circuit causes the system to be reset, the RESET pin outputs “L” level. I/O pins of the system clock generating circuit. When using a ceramic resonator, connect it between pins XIN and XOUT. A feedback resistor is built-in between them. When using the RC oscillation, connect a resistor and a capacitor to XIN, and leave XOUT pin open. Each pin of port D has an independent 1-bit wide I/O function. Each pin has an output latch. For input use, set the latch of the specified bit to “1.” Input is examined by skip decision. The output structure is N-channel open-drain. Ports D2 and D 3 are equipped with a pull-up function and a key-on wakeup function. Both functions can be switched by software. Ports D2 and D3 are also used as ports C and K, respectively. Port P0 serves as a 4-bit I/O port, and it can be used as inputs when the output latch is set to “1.” The output structure is N-channel open-drain. Port P0 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Port P1 serves as a 4-bit I/O port, and it can be used as inputs when the output latch is set to “1.” The output structure is N-channel open-drain. Port P1 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Ports P12 and P13 are also used as CNTR and INT, respectively. Port P2 serves as a 2-bit I/O port, and it can be used as inputs when the output latch is set to “1.” The output structure is N-channel open-drain. Port P2 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Ports P20 and P21 are also used as AIN0 and AIN1, respectively. 1-bit I/O port. Port C can be used as inputs when the output latch is set to “1.” The output structure is N-channel open-drain. Port C has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Port C is also used as port D2. 1-bit I/O port. Port K can be used as inputs when the output latch is set to “1.” The output structure is N-channel open-drain. Port K has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Port K is also used as port D3. CNTR pin has the function to input the clock for the timer 2 event counter, and to output the timer 1 or timer 2 underflow signal divided by 2. This pin is also used as port P12. INT pin accepts external interrupts. It has the key-on wakeup function which can be switched by software. This pin is also used as port P13. A/D converter analog input pins. AIN0 and AIN1 are also used as ports P20 and P21, respectively. XIN XOUT D0–D3 System clock input System clock output I/O port D Input Output I/O P00–P03 I/O I/O P10–P13 I/O port P1 I/O P20, P21 I/O port P2 I/O Port C I/O port C I/O Port K I/O port K I/O CNTR Timer input/output I/O INT AIN0–AIN1 Interrupt input Analog input Input Input MULTIFUNCTION Pin D2 D3 P12 P13 Multifunction C K CNTR INT Pin C K CNTR INT Multifunction D2 D3 P12 P13 Pin P20 P21 Multifunction AIN0 AIN1 Pin AIN0 AIN1 Multifunction P20 P21 Notes 1: Pins except above have just single function. 2: The input/output of D2, D3, P12 and P13 can be used even when C, K, CNTR (input) and INT are selected. 3: The input of P12 can be used even when CNTR (output) is selected. 4: The input/output of P20, P21 can be used even when AIN0, AIN1 are selected. Rev.3.01 2005.02.07 REJ03B0104-0301 page 5 of 112 4501 Group DEFINITION OF CLOCK AND CYCLE q Operation source clock The operation source clock is the source clock to operate this product. In this product, the following clocks are used. • External ceramic resonator • External RC oscillation • Clock (f(XIN)) by the external clock • Clock (f(RING)) of the on-chip oscillator which is the internal oscillator. q System clock The system clock is the basic clock for controlling this product. The system clock is selected by the bits 2 and 3 of the clock control register MR. Table Selection of system clock Register MR System clock MR3 MR2 (Note 1) 0 0 f(XIN) or f(RING) 0 1 f(XIN)/2 or f(RING)/2 1 0 f(XIN)/4 or f(RING)/4 1 1 f(XIN)/8 or f(RING)/8 q Instruction clock The instruction clock is a signal derived by dividing the system clock by 3. The one instruction clock cycle generates the one machine cycle. q Machine cycle The machine cycle is the standard cycle required to execute the instruction. Operation mode High-speed mode Middle-speed mode Low-speed mode Default mode Notes 1: The on-chip oscillator clock is f(RING), the clock by the ceramic resonator, RC oscillation or external clock is f(XIN). 2: T he default mode is selected after system is released from reset and is returned from RAM back-up. PORT FUNCTION Port Port D D0, D1 D2/C D3/K Pin Input Output I/O (4) Output structure N-channel open-drain I/O unit 1 Control instructions SD, RD SZD, CLD SCP, RCP SNZCP IAK, OKA OP0A IAP0 Control registers PU2, K2 Remark Built-in programmable pull-up functions Key-on wakeup functions (programmable) Built-in programmable pull-up functions Key-on wakeup functions (programmable) Built-in programmable pull-up functions Key-on wakeup functions (programmable) Built-in programmable pull-up functions Key-on wakeup functions (programmable) Port P0 P00–P03 I/O (4) N-channel open-drain 4 PU0, K0 Port P1 P10, P11 P12/CNTR, P13/INT Port P2 P20/AIN0 P21/AIN1 I/O (4) N-channel open-drain 4 OP1A IAP1 PU1, K1 W6, I1 I/O (2) N-channel open-drain 2 OP2A IAP2 PU2, K2 Q1 Rev.3.01 2005.02.07 REJ03B0104-0301 page 6 of 112 4501 Group CONNECTIONS OF UNUSED PINS Pin XIN XOUT Connection Connect to VSS. Open. Usage condition System operates by the on-chip oscillator. (Note 1) System operates by the external clock. (The ceramic resonator is selected with the CMCK instruction.) System operates by the RC oscillator. (The RC oscillation is selected with the CRCK instruction.) System operates by the on-chip oscillator. (Note 1) D0, D1 D2/C D3/K P00–P03 P10, P11 P12/CNTR P13/INT Open. (Output latch is set to “1.”) Open. (Output latch is set to “0.”) Connect to VSS. Open. (Output latch is set to “1.”) Open. (Output latch is set to “0.”) Connect to VSS. Open. (Output latch is set to “1.”) Open. (Output latch is set to “0.”) Connect to VSS. Open. (Output latch is set to “1.”) Open. (Output latch is set to “0.”) Connect to VSS. Open. (Output latch is set to “1.”) Open. (Output latch is set to “0.”) Connect to VSS. Open. (Output latch is set to “1.”) Open. (Output latch is set to “0.”) Connect to VSS. P20/AIN0 P21/AIN1 The key-on wakeup function is not selected. (Note 4) The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) The key-on wakeup function is not selected. (Note 4) The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) The key-on wakeup function is not selected. (Note 4) The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) The key-on wakeup function is not selected. The input to INT pin is disabled. (Notes 4, 5) The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) The key-on wakeup function is not selected. (Note 4) The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) Notes 1: When the ceramic resonator or the RC oscillation is not selected by program, system operates by the on-chip oscillator (internal oscillator). 2: When the pull-up function is left valid, the supply current is increased. Do not select the pull-up function. 3: When the key-on wakeup function is left valid, the system returns from the RAM back-up state immediately after going into the RAM back-up state. Do not select the key-on wakeup function. 4: When selecting the key-on wakeup function, select also the pull-up function. 5: Clear the bit 3 (I13) of register I1 to “0” to disable to input to INT pin (after reset: I13 = “0”) (Note when connecting to VSS) q Connect the unused pins to VSS using the thickest wire at the shortest distance against noise. Rev.3.01 2005.02.07 REJ03B0104-0301 page 7 of 112 4501 Group PORT BLOCK DIAGRAMS Register Y Decoder Skip decision (SZD instruction) D0 , D 1 S RQ (Note 1) CLD instruction SD instruction RD instruction Pull-up transistor Register Y Decoder K22 Key-on wakeup “L” level detection circuit Skip decision (SZD instruction) S Skip decision (SNZCP instruction) PU22 CLD instruction SD instruction RD instruction SCP instruction RCP instruction (Note 1) D2/C (Note 2) RQ S RQ Pull-up transistor Register Y Decoder K23 Key-on wakeup “L” level detection circuit Skip decision (SZD instruction) CLD instruction S IAK instruction Register A PU23 (Note 1) D3/K (Note 2) SD instruction RD instruction A0 OKA instruction RQ D TQ Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to ports D2/C and D3/K must be VDD or less. Port block diagram (1) Rev.3.01 2005.02.07 REJ03B0104-0301 page 8 of 112 4501 Group Pull-up transistor PU0i (Note 2) Register A IAP0 instruction Ai (Note 2) Ai OP0A instruction D T Q K0i (Note 1) P00, P01 (Note 4) Key-on wakeup input “L” level detection circuit Pull-up transistor PU0j Register A IAP0 instruction Aj (Note 3) Aj OP0A instruction D T Q K0j Key-on wakeup “L” level detection circuit (Note 3) (Note 1) P02, P03 (Note 4) Notes 1: This symbol represents a parasitic diode on the port. 2: i represents 0 or 1. 3: j represents 2 or 3. 4: Applied potential to port P0 must be VDD or less. Port block diagram (2) Rev.3.01 2005.02.07 REJ03B0104-0301 page 9 of 112 4501 Group Pull-up transistor K1i (Note 2) PU1i (Note 2) Key-on wakeup input “L” level detection circuit IAP1 instruction Register A Ai (Note 2) Ai OP1A instruction D T Q (Note 1) P10, P11 (Note 3) Pull-up transistor K12 PU12 Key-on wakeup input “L” level detection circuit W 21 W 20 Clock input for timer 2 event counter IAP1 instruction Register A A2 A2 OP1A instruction (Note 1) P12/CNTR (Note 3) D W60 T Q 0 1 Timer 1 or timer 2 underflow signal divided by 2 K13 “L” level detection circuit K13 Pull-up transistor PU13 Key-on wakeup input External 0 interrupt External interrupt circuit IAP1 instruction (Note 1) P13/INT (Note 3) Register A A3 A3 D T Q OP1A instruction Notes 1: This symbol represents a parasitic diode on the port. 2: i represents 0 or 1. 3: Applied potential to port P1 must be VDD or less. Port block diagram (3) Rev.3.01 2005.02.07 REJ03B0104-0301 page 10 of 112 4501 Group K20 Pull-up transistor PU20 Key-on wakeup input “L” level detection circuit Register A A0 A0 IAP2 instruction (Note 1) P20/AIN0 (Note 3) Q Q1 Decoder D T OP2A instruction Analog input K21 Pull-up transistor PU21 Key-on wakeup input Register A A1 A1 OP2A instruction “L” level detection circuit IAP2 instruction (Note 1) P21/AIN1 (Note 3) D T Q Q1 Decoder Analog input Notes 1: This symbol represents a parasitic diode on the port. 2: i represents 0 or 1. 3: Applied potential to port P2 must be VDD or less. Port block diagram (4) Rev.3.01 2005.02.07 REJ03B0104-0301 page 11 of 112 4501 Group (Note) P13/INT I13 I12 Falling 0 1 One-sided edge detection circuit I11 0 EXF0 1 Both edges detection circuit External 0 interrupt Rising K13 Wakeup Skip Timer 1 count start synchronization circuit input SNZI0 instruction • This symbol represents a parasitic diode on the port. External interrupt circuit structure Rev.3.01 2005.02.07 REJ03B0104-0301 page 12 of 112 4501 Group FUNCTION BLOCK OPERATIONS CPU (1) Arithmetic logic unit (ALU) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4bit data addition, comparison, AND operation, OR operation, and bit manipulation. (CY) (M(DP)) Addition (A) Fig. 1 AMC instruction execution example ALU (2) Register A and carry flag Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to “1” when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A0 is stored in carry flag CY with the RAR instruction (Figure 2). Carry flag CY can be set to “1” with the SC instruction and cleared to “0” with the RC instruction. SC instruction RC instruction CY A3 A2 A1 A0 RAR instruction (3) Registers B and E Register B is a 4-bit register used for temporary storage of 4-bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3). Register E is undefined after system is released from reset and returned from the RAM back-up. Accordingly, set the initial value. A0 CY A3 A2 A1 Fig. 2 RAR instruction execution example Register B TAB instruction Register A B3 B2 B1 B0 A3 A2 A1 A0 (4) Register D Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 4). Register D is undefined after system is released from reset and returned from the RAM back-up. Accordingly, set the initial value. TEAB instruction Register E E7 E6 E5 E4 E3 E2 E1 E0 TABE instruction B3 B2 B1 B0 Register B A3 A2 A1 A0 Register A TBA instruction Fig. 3 Registers A, B and register E TABP p instruction Specifying address ROM 8 4 0 p6 p5 PCH p4 p3 p2 p1 p0 PCL DR2 DR1DR0 A3 A2 A1 A0 Low-order 4bits Register A (4) Middle-order 4 bits Register B (4) Immediate field value p The contents of The contents of register D register A Fig. 4 TABP p instruction execution example Rev.3.01 2005.02.07 REJ03B0104-0301 page 13 of 112 4501 Group (5) Stack registers (SKS) and stack pointer (SP) Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when; • branching to an interrupt service routine (referred to as an interrupt service routine), • performing a subroutine call, or • executing the table reference instruction (TABP p). Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. The contents of registers SKs are destroyed when 8 levels are exceeded. The register SK nesting level is pointed automatically by 3-bit stack pointer (SP). The contents of the stack pointer (SP) can be transferred to register A with the TASP instruction. Figure 5 shows the stack registers (SKs) structure. Figure 6 shows the example of operation at subroutine call. Program counter (PC) Executing BM instruction SK0 SK1 SK2 SK3 SK4 SK5 SK6 SK7 Executing RT instruction (SP) = 0 (SP) = 1 (SP) = 2 (SP) = 3 (SP) = 4 (SP) = 5 (SP) = 6 (SP) = 7 Stack pointer (SP) points “7” at reset or returning from RAM back-up mode. It points “0” by executing the first BM instruction, and the contents of program counter is stored in SK0. When the BM instruction is executed after eight stack registers are used ((SP) = 7), (SP) = 0 and the contents of SK0 is destroyed. Fig. 5 Stack registers (SKs) structure (6) Interrupt stack register (SDP) Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (SDP) is used to temporarily store the contents of data pointer, carry flag, skip flag, register A, and register B just before an interrupt until returning to the original routine. Unlike the stack registers (SKs), this register (SDP) is not used when executing the subroutine call instruction and the table reference instruction. (SP) ← 0 (SK0) ← 000116 (PC) ← SUB1 Main program Address 000016 NOP 000116 BM SUB1 000216 NOP Subroutine SUB1 : NOP · · · RT (7) Skip flag Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt stack register (SDP) and the skip condition is retained. (PC) ← (SK0) (SP) ← 7 Note : Returning to the BM instruction execution address with the RT instruction, and the BM instruction becomes the NOP instruction. Fig. 6 Example of operation at subroutine call Rev.3.01 2005.02.07 REJ03B0104-0301 page 14 of 112 4501 Group (8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed. Program counter consists of PC H ( most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7). Make sure that the PCH does not specify after the last page of the built-in ROM. Program counter p6 p5 p4 p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0 PCH Specifying page PCL Specifying address Fig. 7 Program counter (PC) structure Data pointer (DP) Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0 (9) Data pointer (DP) Data pointer (DP) is used to specify a RAM address and consists of registers Z, X, and Y. Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure 8). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 9). • Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the RAM back-up. After system is returned from the RAM back-up, set these registers. Register Y (4) Specifying RAM digit Register X (4) Specifying RAM file Register Z (2) Specifying RAM file group Fig. 8 Data pointer (DP) structure Specifying bit position Set D3 D2 D1 D0 0 0 0 1 1 Port D output latch Register Y (4) Fig. 9 SD instruction execution example Rev.3.01 2005.02.07 REJ03B0104-0301 page 15 of 112 4501 Group PROGRAM MEMOY (ROM) The program memory is a mask ROM. 1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 10 shows the ROM map of M34501M4. Table 1 ROM size and pages Part number M34501M2 M34501M4 M34501E4 ROM (PROM) size (✕ 10 bits) 2048 words 4096 words 4096 words Pages 16 (0 to 15) 32 (0 to 31) 32 (0 to 31) 98 000016 007F16 008016 00FF16 010016 017F16 018016 7 6 5 4 3 2 10 Page 0 Interrupt address page Subroutine special page Page 1 Page 2 Page 3 A part of page 1 (addresses 008016 to 00FF16) is reserved for interrupt addresses (Figure 11). When an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and the instruction at the interrupt address is executed. When using an interrupt service routine, write the instruction generating the branch to that routine at an interrupt address. Page 2 (addresses 010016 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. ROM pattern (bits 7 to 0) of all addresses can be used as data areas with the TABP p instruction. 0FFF16 Page 31 Fig. 10 ROM map of M34501M4/M34501E4 008016 008216 008416 008616 008816 008A16 008C16 008E16 98 765 432 10 External 0 interrupt address Timer 1 interrupt address Timer 2 interrupt address A/D interrupt address 00FF16 Fig. 11 Page 1 (addresses 008016 to 00FF16) structure Rev.3.01 2005.02.07 REJ03B0104-0301 page 16 of 112 4501 Group DATA MEMORY (RAM) 1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers Z, X, and Y. Set a value to the data pointer certainly when executing an instruction to access RAM. Table 2 shows the RAM size. Figure 12 shows the RAM map. • Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the RAM back-up. After system is returned from the RAM back-up, set these registers. Table 2 RAM size Part number M34501M2 M34501M4 M34501E4 RAM size 128 words ✕ 4 bits (512 bits) 256 words ✕ 4 bits (1024 bits) 256 words ✕ 4 bits (1024 bits) RAM 256 words ✕ 4 bits (1024 bits) Register Z Register X 0 1 2 0 3 ... 6 7 ........ 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 256 words (1024 bits) M34501M4/E4 128 words (512 bits) M34501M2 Z=0, X=0 to 15 Z=0, X=0 to 7 Fig. 12 RAM map Rev.3.01 2005.02.07 REJ03B0104-0301 page 17 of 112 Register Y 4501 Group INTERRUPT FUNCTION The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. An interrupt occurs when the following 3 conditions are satisfied. • An interrupt activated condition is satisfied (request flag = “1”) • Interrupt enable bit is enabled (“1”) • Interrupt enable flag is enabled (INTE = “1”) Table 3 shows interrupt sources. (Refer to each interrupt request flag for details of activated conditions.) Table 3 Interrupt sources Priority Interrupt name level 1 External 0 interrupt 2 3 4 Timer 1 interrupt Timer 2 interrupt A/D interrupt Activated condition Level change of INT pin Timer 1 underflow Timer 2 underflow Completion of A/D conversion Interrupt address Address 0 in page 1 Address 4 in page 1 Address 6 in page 1 Address C in page 1 (1) Interrupt enable flag (INTE) The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to “1” with the EI instruction and disabled when INTE flag is cleared to “0” with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to “0,” so that other interrupts are disabled until the EI instruction is executed. Table 4 Interrupt request flag, interrupt enable bit and skip instruction Interrupt name External 0 interrupt Timer 1 interrupt Timer 2 interrupt A/D interrupt Interrupt request flag EXF0 T1F T2F ADF Skip instruction SNZ0 SNZT1 SNZT2 SNZAD Interrupt enable bit V10 V12 V13 V22 (2) Interrupt enable bit Use an interrupt enable bit of interrupt control registers V1 and V2 to select the corresponding interrupt or skip instruction. Table 4 shows the interrupt request flag, interrupt enable bit and skip instruction. Table 5 shows the interrupt enable bit function. Table 5 Interrupt enable bit function Interrupt enable bit 1 0 Occurrence of interrupt Enabled Disabled Skip instruction Invalid Valid (3) Interrupt request flag When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to “ 1. ” E ach interrupt request flag is cleared to “0” when either; • an interrupt occurs, or • the next instruction is skipped with a skip instruction. Each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Once set, the interrupt request flag retains set until a clear condition is satisfied. Accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. If more than one interrupt request flag is set when the interrupt disable state is released, the interrupt priority level is as follows shown in Table 3. Rev.3.01 2005.02.07 REJ03B0104-0301 page 18 of 112 4501 Group (4) Internal state during an interrupt The internal state of the microcomputer during an interrupt is as follows (Figure 14). • Program counter (PC) An interrupt address is set in program counter. The address to be executed when returning to the main routine is automatically stored in the stack register (SK). • Interrupt enable flag (INTE) INTE flag is cleared to “0” so that interrupts are disabled. • Interrupt request flag Only the request flag for the current interrupt source is cleared to “0.” • Data pointer, carry flag, skip flag, registers A and B The contents of these registers and flags are stored automatically in the interrupt stack register (SDP). • Program counter (PC) ............................................................... Each interrupt address • Stack register (SK) The address of main routine to be .................................................................................................... executed when returning • Interrupt enable flag (INTE) .................................................................. 0 (Interrupt disabled) • Interrupt request flag (only the flag for the current interrupt source) ................................................................................... 0 • Data pointer, carry flag, registers A and B, skip flag ........ Stored in the interrupt stack register (SDP) automatically Fig. 14 Internal state when interrupt occurs (5) Interrupt processing When an interrupt occurs, a program at an interrupt address is executed after branching a data store sequence to stack register. Write the branch instruction to an interrupt service routine at an interrupt address. Use the RTI instruction to return from an interrupt service routine. Interrupt enabled by executing the EI instruction is performed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI instruction is executed just before the RTI instruction, interrupts are enabled after returning the main routine. (Refer to Figure 13) INT pin (L→H or H→L input) EXF0 V10 Address 0 in page 1 Timer 1 underflow T1F V12 Address 4 in page 1 Timer 2 underflow T2F V13 Address 6 in page 1 Main routine Interrupt service routine Interrupt occurs Completion of A/D conversion Activated condition A DF Request flag (state retained) V22 Enable bit INTE Address C in page 1 Enable flag Fig. 15 Interrupt system diagram • • • • EI R TI Interrupt is enabled : Interrupt enabled state : Interrupt disabled state Fig. 13 Program example of interrupt processing Rev.3.01 2005.02.07 REJ03B0104-0301 page 19 of 112 4501 Group (6) Interrupt control registers • Interrupt control register V1 Interrupt enable bits of external 0, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A. • Interrupt control register V2 The A/D interrupt enable bit is assigned to register V2. Set the contents of this register through register A with the TV2A instruction. The TAV2 instruction can be used to transfer the contents of register V2 to register A. Table 6 Interrupt control registers Interrupt control register V1 V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit Not used External 0 interrupt enable bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : 00002 R/W Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) (Note 2) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) (Note 2) This bit has no function, but read/write is enabled. Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) (Note 2) Interrupt control register V2 V23 V22 V21 V20 Not used A/D interrupt enable bit Not used Not used 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : 00002 R/W This bit has no function, but read/write is enabled. Interrupt disabled (SNZAD instruction is valid) Interrupt enabled (SNZAD instruction is invalid) (Note 2) This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: These instructions are equivalent to the NOP instrucion. (7) Interrupt sequence Interrupts only occur when the respective INTE flag, interrupt enable bits (V10, V12, V13, V22), and interrupt request flag are “1.” The interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. The interrupt occurs after 3 machine cycles only when the three interrupt conditions are satisfied on execution of other than one-cycle instructions (Refer to Figure 16). Rev.3.01 2005.02.07 REJ03B0104-0301 page 20 of 112 4501 Group q When an interrupt request flag is set after its interrupt is enabled (Note 1) Rev.3.01 2005.02.07 REJ03B0104-0301 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 Interrupt disabled state Interrupt enabled state Retaining level of system clock for 4 periods or more is necessary. Interrupt activated condition is satisfied. Flag cleared 2 to 3 machine cycles (Notes 2, 3) The program starts from the interrupt address. f (XIN) (default mode) Fig. 16 Interrupt sequence f (XIN) (low-speed mode) page 21 of 112 f (XIN) (middle-speed mode) f (XIN) (high-speed mode) 1 machine cycle T1 T2 System clock Interrupt enable flag (INTE) EI instruction execution cycle INT External interrupt EXF0 Timer 1, Timer 2, and A/D interrupts T1F, T2F ADF Notes 1: The 4501 Group operates in the default mode after system is released from reset (system clock = operation source clock divided by 8). 2: The address is stacked to the last cycle. 3: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied. 4501 Group EXTERNAL INTERRUPTS The 4501 Group has the external 0 interrupt. An external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). The external interrupt can be controlled with the interrupt control register I1. Table 7 External interrupt activated conditions Name External 0 interrupt INT Input pin Activated condition When the next waveform is input to INT pin • Falling waveform (“H”→“L”) • Rising waveform (“L”→“H”) • Both rising and falling waveforms Valid waveform selection bit I11 I12 (Note) P13/INT I13 I12 Falling 0 1 One-sided edge detection circuit I11 0 EXF0 1 Both edges detection circuit External 0 interrupt Rising K13 Wakeup Skip Timer 1 count start synchronization circuit input SNZI0 instruction • This symbol represents a parasitic diode on the port. Fig. 17 External interrupt circuit structure (1) External 0 interrupt request flag (EXF0) External 0 interrupt request flag (EXF0) is set to “1” when a valid waveform is input to INT pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF0 flag can be examined with the skip instruction (SNZ0). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF0 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip instruction. • External 0 interrupt activated condition External 0 interrupt activated condition is satisfied when a valid waveform is input to INT pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 0 interrupt is as follows. ➀ Set the bit 3 of register I1 to “1” for the INT pin to be in the input enabled state. ➁ Select the valid waveform with the bits 1 and 2 of register I1. ➂ Clear the EXF0 flag to “0” with the SNZ0 instruction. ➃ Set the NOP instruction for the case when a skip is performed with the SNZ0 instruction. ➄ Set both the external 0 interrupt enable bit (V1 0) and the INTE flag to “1.” The external 0 interrupt is now enabled. Now when a valid waveform is input to the INT pin, the EXF0 flag is set to “ 1 ” a nd the external 0 interrupt occurs. Rev.3.01 2005.02.07 REJ03B0104-0301 page 22 of 112 4501 Group (2) External interrupt control registers • Interrupt control register I1 Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the TI1A instruction. The TAI1 instruction can be used to transfer the contents of register I1 to register A. Table 8 External interrupt control register Interrupt control register I1 I13 INT pin input control bit (Note 2) 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W INT pin input disabled INT pin input enabled Falling waveform (“L” level of INT pin is recognized with the SNZI0 instruction)/“L” level Rising waveform (“H” level of INT pin is recognized with the SNZI0 instruction)/“H” level One-sided edge detected Both edges detected Disabled Enabled I12 Interrupt valid waveform for INT pin/ return level selection bit (Note 2) I11 I10 INT pin edge detection circuit control bit INT pin timer 1 control enable bit Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction when the bit 0 (V10 ) of register V1 to “0”. In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is performed with the SNZ0 instruction. Rev.3.01 2005.02.07 REJ03B0104-0301 page 23 of 112 4501 Group (3) Notes on interrupts ➀ Note [1] on bit 3 of register I1 When the input of the INT pin is controlled with the bit 3 of register I1 in software, be careful about the following notes. • Depending on the input state of the P13/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 18➀) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to Figure 18➁). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 18➂). ➂ Note [3] on bit 2 of register I1 When the interrupt valid waveform of the P13/INT pin is changed with the bit 2 of register I1 in software, be careful about the following notes. • Depending on the input state of the P13/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 20➀) and then, change the bit 2 of register I1 is changed. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to Figure 20➁). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 20➂). ••• ••• LA 4 TV1A LA 8 TI1A NOP SNZ0 NOP ; (✕✕✕02) ; The SNZ0 instruction is valid ........... ➀ ; (1✕✕✕2) ; Control of INT pin input is changed ........................................................... ➁ ; The SNZ0 instruction is executed (EXF0 flag cleared) ........................................................... ➂ LA 4 TV1A LA 12 TI1A NOP SNZ0 NOP ; (✕✕✕02) ; The SNZ0 instruction is valid ........... ➀ ; (✕1✕✕2) ; Interrupt valid waveform is changed ........................................................... ➁ ; The SNZ0 instruction is executed (EXF0 flag cleared) ........................................................... ➂ ••• ✕ : these bits are not used here. Fig. 18 External 0 interrupt program example-1 ➁ Note [2] on bit 3 of register I1 When the bit 3 of register I1 is cleared to “0”, the RAM back-up mode is selected and the input of INT pin is disabled, be careful about the following notes. • When the key-on wakeup function of port P13 is not used (register K1 3 = “ 0 ” ), clear bits 2 and 3 of register I1 before system enters to the RAM back-up mode. (refer to Figure 19➀). ✕ : these bits are not used here. Fig. 20 External 0 interrupt program example-3 ••• LA 0 TI1A DI EPOF POF ; (00✕✕2) ; Input of INT disabled ........................ ➀ ; RAM back-up ✕ : these bits are not used here. Fig. 19 External 0 interrupt program example-2 Rev.3.01 2005.02.07 REJ03B0104-0301 ••• page 24 of 112 ••• 4501 Group TIMERS The 4501 Group has the following timers. • Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt request flag is set to “1,” new data is loaded from the reload register, and count continues (auto-reload function). • Fixed dividing frequency timer The fixed dividing frequency timer has the fixed frequency dividing ratio (n). An interrupt request flag is set to “1” after every n count of a count pulse. FF16 n : Counter initial value Count starts n Reload Reload The contents of counter 1st underflow 2nd underflow 0016 Time n+1 count Timer interrupt “1” “0” request flag An interrupt occurs or a skip instruction is executed. n+1 count Fig. 21 Auto-reload function The 4501 Group timer consists of the following circuits. • Prescaler : frequency divider • Timer 1 : 8-bit programmable timer • Timer 2 : 8-bit programmable timer (Timers 1 and 2 have the interrupt function, respectively) • 16-bit timer Table 9 Function related timers Circuit Prescaler Timer 1 Structure Frequency divider 8-bit programmable binary down counter (link to INT input) Timer 2 8-bit programmable binary down counter • Timer 1 underflow • Prescaler output (ORCLK) • CNTR input • System clock 16-bit timer • Instruction clock 16-bit fixed dividing frequency binary down counter 65536 • Watchdog timer (The 16th bit is counted twice) 1 to 256 Count source • Instruction clock • Prescaler output (ORCLK) Frequency dividing ratio 4, 16 1 to 256 Use of output signal • Timer 1 and 2 count sources • Timer 2 count source • CNTR output • Timer 1 interrupt • CNTR output • Timer 2 interrupt Control register W1 W1 W2 W6 W2 W6 Prescaler and timers 1 and 2 can be controlled with the timer control registers W1, W2 and W6. The 16-bit timer is a free counter which is not controlled with the control register. Each function is described below. Rev.3.01 2005.02.07 REJ03B0104-0301 page 25 of 112 4501 Group System clock Instruction clock Prescaler Division circuit divided by 8 divided by 4 XIN MR3, MR2 11 10 01 00 W13 0 1/4 1/16 W12 0 1 Clock generation circuit divided by 2 Internal clock generating circuit (divided by 3) 1 ORCLK I1 2 Falling P13/INT I1 3 0 1 Rising One-sided edge detection circuit Both edges detection circuit I10 W22 I1 1 0 1 R (Note 1) SQ W10 1 0 Timer 1 underflow signal (Note 2) W11 0 1 Timer 1 (8) Reload register R1 (8) T1AB (TAB1) (TR1AB) T1AB (TAB1) T1F Timer 1 interrupt Register B Register A Timer 1 underflow signal W21,W20 00 01 10 11 W23 (Note 2) 0 1 Timer 2 (8) Reload register R2 (8) (T2AB) T2F Timer 2 interrupt (TAB2) Register B Register A (TAB2) W60 P12/CNTR 0 1 P12 output W61 0 1 1/2 1/2 Timer 2 underflow signal 16-bit timer (WDT) Instruction clock 1 16 S WRST instruction (Note 3) Reset signal (Note 5) DWDT instruction + WRST instruction (Note 4) R S WEF Q Data is set automatically from each reload register when timer 1 or 2 underflows (auto-reload function) Notes 1: Timer 1 count start synchronous circuit is set by the valid edge of P13/INT pin selected by bits 1 (I11) and 2 (I12) of register I1. 2: Count source is stopped by clearing to “0.” 3: When the WRST instruction is executed at WDF1 flag = “1,” WDF1 flag is cleared to “0” and the next instruction is skipped. When the WRST instruction is executed at Watchdog WDF1 flag = “0,” skip is not executed. reset signal 4: When the DWDT and WRST instructions are executed continuously, WEF flag is cleared to “0” and reset by watchdog timer is not executed. 5: The WEF flag is set to “1” at system reset or RAM back-up mode. WDF1 Q R D TR Q WDF2 Reset signal Fig. 22 Timers structure Rev.3.01 2005.02.07 REJ03B0104-0301 page 26 of 112 4501 Group Table 10 Timer control registers Timer control register W1 W13 W12 W11 W10 Prescaler control bit Prescaler dividing ratio selection bit Timer 1 control bit Timer 1 count start synchronous circuit control bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : 00002 R/W Stop (state initialized) Operating Instruction clock divided by 4 Instruction clock divided by 16 Stop (state retained) Operating Count start synchronous circuit not selected Count start synchronous circuit selected Timer control register W2 W23 W22 W21 Timer 2 count source selection bits W20 Timer 2 control bit Timer 1 count auto-stop circuit selection bit (Note 2) 0 0 1 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W Stop (state retained) Operating Count auto-stop circuit not selected Count auto-stop circuit selected Count source Timer 1 underflow signal Prescaler output (ORCLK) CNTR input System clock 0 1 0 1 W21 W20 Timer control register W6 W63 W62 W61 W60 Not used Not used CNTR output selection bit P12/CNTR function selection bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Timer 1 underflow signal divided by 2 output Timer 2 underflow signal divided by 2 output P12(I/O)/CNTR input (Note 3) P12 (input)/CNTR input/output (Note 3) Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: This function is valid only when the timer 1 count start synchronization circuit is selected. 3: CNTR input is valid only when CNTR input is selected as the timer 2 count source. (1) Timer control registers • Timer control register W1 Register W1 controls the count operation of timer 1, the selection of count start synchronous circuit, and the frequency dividing ratio and count operation of prescaler. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A. • Timer control register W2 Register W2 controls the selection of timer 1 count auto-stop circuit, and the count operation and count source of timer 2. Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A. • Timer control register W6 Register W6 controls the P12/CNTR pin function and the selection of CNTR output. Set the contents of this register through register A with the TW6A instruction. The TAW6 instruction can be used to transfer the contents of register W6 to register A.. (2) Prescaler Prescaler is a frequency divider. Its frequency dividing ratio can be selected. The count source of prescaler is the instruction clock. Use the bit 2 of register W1 to select the prescaler dividing ratio and the bit 3 to start and stop its operation. Prescaler is initialized, and the output signal (ORCLK) stops when the bit 3 of register W1 is cleared to “0.” Rev.3.01 2005.02.07 REJ03B0104-0301 page 27 of 112 4501 Group (3) Timer 1 (interrupt function) Timer 1 is an 8-bit binary down counter with the timer 1 reload register (R1). Data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB instruction. Stop counting and then execute the T1AB instruction to set data to timer 1. Data can be written to reload register (R1) with the TR1AB instruction. When writing data to reload register R1 with the TR1AB instruction, the downcount after the underflow is started from the setting value of reload register R1. Timer 1 starts counting after the following process; ➀ set data in timer 1, and ➁ set the bit 1 of register W1 to “1.” However, INT pin input can be used as the start trigger for timer 1 count operation by setting the bit 0 of register W1 to “1.” Also, in this time, the auto-stop function by timer 1 underflow can be performed by setting the bit 2 of register W2 to “1.” When a value set is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes “0”), the timer 1 interrupt request flag (T1F) is set to “1,” new data is loaded from reload register R1, and count continues (auto-reload function). Data can be read from timer 1 with the TAB1 instruction. When reading the data, stop the counter and then execute the TAB1 instruction. (5) Timer interrupt request flags (T1F, T2F) Each timer interrupt request flag is set to “ 1 ” w hen each timer underflows. The state of these flags can be examined with the skip instructions (SNZT1, SNZT2). Use the interrupt control register V1 to select an interrupt or a skip instruction. An interrupt request flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with a skip instruction. (6) Count start synchronization circuit (timer 1) Timer 1 has the count start synchronous circuit which synchronizes the input of INT pin, and can start the timer count operation. Timer 1 count start synchronous circuit function is selected by setting the bit 0 of register W1 to “1.” The control by INT pin input can be performed by setting the bit 0 of register I1 to “1.” The count start synchronous circuit is set by level change (“H”→“L” or “L”→“H”) of INT pin input. This valid waveform is selected by bits 1 (I11) and 2 (I12) of register I1 as follows; • I11 = “0”: Synchronized with one-sided edge (falling or rising) • I11 = “1”: Synchronized with both edges (both falling and rising) When register I11=“0” (synchronized with the one-sided edge), the rising or falling waveform can be selected by the bit 2 of register I1; • I12 = “0”: Falling waveform • I12 = “1”: Rising waveform When timer 1 count start synchronous circuit is used, the count start synchronous circuit is set, the count source is input to each timer by inputting valid waveform to INT pin. Once set, the count start synchronous circuit is cleared by clearing the bit I10 to “0” or reset. However, when the count auto-stop circuit is selected (register W22 = “1”), the count start synchronous circuit is cleared (auto-stop) at the timer 1 underflow. (4) Timer 2 (interrupt function) Timer 2 is an 8-bit binary down counter with the timer 2 reload register (R2). Data can be set simultaneously in timer 2 and the reload register (R2) with the T2AB instruction. Stop counting and then execute the T2AB instruction to set data to timer 2. Timer 2 starts counting after the following process; ➀ set data in timer 2, ➁ select the count source with the bits 0 and 1 of register W2, and ➂ set the bit 3 of register W2 to “1.” When a value set is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes “0”), the timer 2 interrupt request flag (T2F) is set to “1,” new data is loaded from reload register R2, and count continues (auto-reload function). Data can be read from timer 2 with the TAB2 instruction. When reading the data, stop the counter and then execute the TAB2 instruction. (7) Count auto-stop circuit (timer 1) Timer 1 has the count auto-stop circuit which is used to stop timer 1 automatically by the timer 1 underflow when the count start synchronous circuit is used. The count auto-stop cicuit is valid by setting the bit 2 of register W2 to “1”. It is cleared by the timer 1 underflow and the count source to timer 1 is stopped. This function is valid only when the timer 1 count start synchronous circuit is selected. Rev.3.01 2005.02.07 REJ03B0104-0301 page 28 of 112 4501 Group (8) Timer input/output pin (P12/CNTR pin) CNTR pin is used to input the timer 2 count source and output the timer 1 and timer 2 underflow signal divided by 2. The P12/CNTR pin function can be selected by bit 0 of register W6. The CNTR output signal can be selected by bit 1 of register W6. When the CNTR input is selected for timer 2 count source, timer 2 counts the falling waveform of CNTR input. (9) Precautions Note the following for the use of timers. • Prescaler Stop the prescaler operation to change its frequency dividing ratio. • Count source Stop timer 1 or 2 counting to change its count source. • Reading the count value Stop timer 1 or 2 counting and then execute the TAB1 or TAB2 instruction to read its data. • Writing to the timer Stop timer 1 or 2 counting and then execute the T1AB or T2AB instruction to write its data. • Writing to reload register R1 When writing data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows. CNTR input (Note) Timer 2 count 0316 0216 0116 0016 FF16 FE16 Timer 2 interrupt request flag (T2F) Note: This is an example when “FF16” is set to timer 2 reload register R2L. Fig. 23 Count timing diagram at CNTR input • Timer 1 and timer 2 count start timing and count time when operation starts Count starts from the first rising edge of the count source (2) after timer 1 and timer 2 operations start (1). Time to first underflow (3) is shorter (for up to 1 period of the count source) than time among next underflow (4) by the timing to start the timer and count source operations after count starts. When selecting CNTR input as the count source of timer 2, timer 2 operates synchronizing with the falling edge of CNTR input. (2) Count Source Count Source (CNTR input) Timer Value 3 2 1 0 3 2 1 0 3 2 Timer Underflow Signal (3) (1) Timer (4) Fig. 24 Timer count start timing and count time when operation starts (T1, T2) Rev.3.01 2005.02.07 REJ03B0104-0301 page 29 of 112 4501 Group WATCHDOG TIMER Watchdog timer provides a method to reset the system when a program run-away occurs. Watchdog timer consists of timer WDT(16-bit binary counter), watchdog timer enable flag (WEF), and watchdog timer flags (WDF1, WDF2). The timer WDT downcounts the instruction clocks as the count source from “FFFF16” after system is released from reset. After the count is started, when the timer WDT underflow occurs (after the count value of timer WDT reaches “FFFF16,” the next count pulse is input), the WDF1 flag is set to “1.” If the WRST instruction is never executed until the timer WDT underflow occurs (until timer WDT counts 65534), WDF2 flag is set to “1,” and the RESET pin outputs “L” level to reset the microcomputer. Execute the WRST instruction at each period of 65534 machine cycle or less by software when using watchdog timer to keep the microcomputer operating normally. When the WEF flag is set to “1” after system is released from reset, the watchdog timer function is valid. When the DWDT instruction and the WRST instruction are executed continuously, the WEF flag is cleared to “ 0 ” a nd the watchdog timer function is invalid. The WEF flag is set to "1" at system reset or RAM back-up mode. The WRST instruction has the skip function. When the WRST instruction is executed while the WDF1 flag is “1”, the WDF1 flag is cleared to “0” and the next instruction is skipped. When the WRST instruction is executed while the WDF1 flag is “0”, the next instruction is not skipped. The skip function of the WRST instruction can be used even when the watchdog timer function is invalid. FFFF 1 6 Value of 16-bit timer (WDT) 000016 WDF1 flag ➁ ➁ 65534 count (Note) WDF2 flag ➃ RESET pin output ➀ Reset released ➂ WRST instruction executed (skip executed) ➄ System reset ➀ After system is released from reset (= after program is started), timer WDT starts count down. ➁ When timer WDT underflow occurs, WDF1 flag is set to “1.” ➂ When the WRST instruction is executed, WDF1 flag is cleared to “0,” the next instruction is skipped. ➃ When timer WDT underflow occurs while WDF1 flag is “1,” WDF2 flag is set to “1” and the watchdog reset signal is output. ➄ The output transistor of RESET pin is turned “ON” by the watchdog reset signal and system reset is executed. Note: The number of count is equal to the number of machine cycle because the count source of watchdog timer is the instruction clock. Fig. 25 Watchdog timer function Rev.3.01 2005.02.07 REJ03B0104-0301 page 30 of 112 4501 Group When the watchdog timer is used, clear the WDF1 flag at the period of 65534 machine cycles or less with the WRST instruction. When the watchdog timer is not used, execute the DWDT instruction and the WRST instruction continuously (refer to Figure 26). The watchdog timer is not stopped with only the DWDT instruction. The contents of WDF1 flag and timer WDT are initialized at the RAM back-up mode. When using the watchdog timer and the RAM back-up mode, initialize the WDF1 flag with the WRST instruction just before the microcomputer enters the RAM back-up state (refer to Figure 27) The watchdog timer function is valid after system is returned from the RAM back-up. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously every system is returned from the RAM back-up, and stop the watchdog timer function. WRST ••• ; WDF1 flag cleared DI DWDT WRST ••• ; Watchdog timer function enabled/disabled ; WEF and WDF1 flags cleared Fig. 26 Program example to start/stop watchdog timer WRST ; WDF1 flag cleared NOP DI ; Interrupt disabled EPOF ; POF instruction enabled POF ↓ Oscillation stop (RAM back-up mode) Fig. 27 Program example to enter the RAM back-up mode when using the watchdog timer Rev.3.01 2005.02.07 REJ03B0104-0301 page 31 of 112 ••• ••• ••• 4501 Group A/D CONVERTER The 4501 Group has a built-in A/D conversion circuit that performs conversion by 10-bit successive comparison method. Table 11 shows the characteristics of this A/D converter. This A/D converter can also be used as an 8-bit comparator to compare analog voltages input from the analog input pin with preset values. Table 11 A/D converter characteristics Characteristics Parameter Successive comparison method Conversion format Resolution Relative accuracy Conversion speed Analog input pin 10 bits Linearity error: ±2LSB Differential non-linearity error: ±0.9LSB 46.5 µ s (High-speed mode at 4.0 MHz oscillation frequency) 2 Register B (4) Register A (4) 4 IAP2 (P20, P21) OP2A (P20, P21) TAQ1 TQ1A 2 Q13 Q12 Q11 Q10 4 4 4 8 TABAD 8 TADAB TALA Instruction clock 1/6 2 Q13 0 A/D control circuit 2-channel multi-plexed analog switch 1 ADF (1) A/D interrupt P20/AIN0 P21/AIN1 1 Comparator 0 Successive comparison register (AD) (10) 10 10 1 Q13 8 0 1 Q13 DAC operation signal 0 1 Q13 DAC DA converter (Note 1) 8 8 VDD 8 VSS Comparator register (8) (Note 2) Notes 1: This switch is turned ON only when A/D converter is operating and generates the comparison voltage. 2: Writing/reading data to the comparator register is possible only in the comparator mode (Q13=1). The value of the comparator register is retained even when the mode is switched to the A/D conversion mode (Q13=0) because it is separated from the successive comparison register (AD). Also, the resolution in the comparator mode is 8 bits because the comparator register consists of 8 bits. Fig. 28 A/D conversion circuit structure Rev.3.01 2005.02.07 REJ03B0104-0301 page 32 of 112 4501 Group Table 12 A/D control registers A/D control register Q1 Q13 Q12 Q11 Analog input pin selection bits Q10 A/D operation mode selection bit Not used at reset : 00002 0 1 0 1 Q11 Q10 0 0 0 1 1 0 1 1 A/D conversion mode Comparator mode This bit has no function, but read/write is enabled. Selected pins AIN0 AIN1 Not available Not available at RAM back-up : state retained R/W Note: “R” represents read enabled, and “W” represents write enabled. (1) Operating at A/D conversion mode The A/D conversion mode is set by setting the bit 3 of register Q1 to “0.” (6) Operation description A/D conversion is started with the A/D conversion start instruction (ADST). The internal operation during A/D conversion is as follows: ➀ When the A/D conversion starts, the register AD is cleared to “00016.” ➁ N ext, the topmost bit of the register AD is set to “ 1, ” a nd the comparison voltage Vref is compared with the analog input voltage VIN. ➂ When the comparison result is Vref < VIN, the topmost bit of the register AD remains set to “1.” When the comparison result is Vref > VIN, it is cleared to “0.” The 4501 Group repeats this operation to the lowermost bit of the register AD to convert an analog value to a digital value. A/D conversion stops after 62 machine cycles (46.5 µs when f(X IN) = 4.0 MHz in high-speed mode) from the start, and the conversion result is stored in the register AD. An A/D interrupt activated condition is satisfied and the ADF flag is set to “1” as soon as A/D conversion completes (Figure 29). (2) Successive comparison register AD Register AD stores the A/D conversion result of an analog input in 10-bit digital data format. The contents of the high-order 8 bits of this register can be stored in register B and register A with the TABAD instruction. The contents of the low-order 2 bits of this register can be stored into the high-order 2 bits of register A with the TALA instruction. However, do not execute these instructions during A/D conversion. When the contents of register AD is n, the logic value of the comparison voltage Vref generated from the built-in DA converter can be obtained with the reference voltage VDD by the following formula: Logic value of comparison voltage Vref Vref = V DD ✕n 1024 n: The value of register AD (n = 0 to 1023) (3) A/D conversion completion flag (ADF) A/D conversion completion flag (ADF) is set to “1” when A/D conversion completes. The state of ADF flag can be examined with the skip instruction (SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction. The ADF flag is cleared to “0” when the interrupt occurs or when the next instruction is skipped with the skip instruction. (4) A/D conversion start instruction (ADST) A/D conversion starts when the ADST instruction is executed. The conversion result is automatically stored in the register AD. (5) A/D control register Q1 Register Q1 is used to select the operation mode and one of analog input pins. Rev.3.01 2005.02.07 REJ03B0104-0301 page 33 of 112 4501 Group Table 13 Change of successive comparison register AD during A/D conversion At starting conversion 1st comparison 2nd comparison 3rd comparison After 10th comparison completes ✼1: 1st comparison result ✼3: 3rd comparison result ✼9: 9th comparison result Change of successive comparison register AD ------------- Comparison voltage (Vref) value VDD 2 VDD 2 VDD 2 VDD VDD 4 VDD VDD 4 ○ ○ ○ ○ 1 ✼1 ✼1 0 1 ✼2 0 0 1 ------------- 0 0 0 0 0 0 0 0 0 ------------------------------------------------------------- ± ± ± ± ± 8 VDD 1024 A/D conversion result ------------- ✼1 ✼2 ✼3 ------------- ----- ✼8 ✼9 ✼A 2 ✼2: 2nd comparison result ✼8: 8th comparison result ✼A: 10th comparison result (7) A/D conversion timing chart Figure 29 shows the A/D conversion timing chart. ADST instruction 62 machine cycles A/D conversion completion flag (ADF) DAC operation signal Fig. 29 A/D conversion timing chart (8) How to use A/D conversion How to use A/D conversion is explained using as example in which the analog input from P21/AIN1 pin is A/D converted, and the highorder 4 bits of the converted data are stored in address M(Z, X, Y) = (0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1), and the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM. The A/D interrupt is not used in this example. ➀ Select the AIN1 pin function and A/D conversion mode with the register Q1 (refer to Figure 30). ➁ Execute the ADST instruction and start A/D conversion. ➂ Examine the state of ADF flag with the SNZAD instruction to determine the end of A/D conversion. ➃ Transfer the low-order 2 bits of converted data to the high-order 2 bits of register A (TALA instruction). ➄ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2). ➅ Transfer the high-order 8 bits of converted data to registers A and B (TABAD instruction). ➆ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1). ➇ Transfer the contents of register B to register A, and then, store into M(Z, X, Y) = (0, 0, 0). (Bit 3) (Bit 0) 0 0 0 1 A/D control register Q1 A IN1 p in selected A/D conversion mode Fig. 30 Setting registers Rev.3.01 2005.02.07 REJ03B0104-0301 page 34 of 112 4501 Group (9) Operation at comparator mode The A/D converter is set to comparator mode by setting bit 3 of the register Q1 to “1.” Below, the operation at comparator mode is described. (12) Comparator operation start instruction (ADST instruction) In comparator mode, executing ADST starts the comparator operating. The comparator stops 8 machine cycles after it has started (6 µs at f(XIN) = 4.0 MHz in high-speed mode). When the analog input voltage is lower than the comparison voltage, the ADF flag is set to “1.” (10) Comparator register In comparator mode, the built-in DA comparator is connected to the 8-bit comparator register as a register for setting comparison voltages. The contents of register B is stored in the high-order 4 bits of the comparator register and the contents of register A is stored in the low-order 4 bits of the comparator register with the TADAB instruction. When changing from A/D conversion mode to comparator mode, the result of A/D conversion (register AD) is undefined. However, because the comparator register is separated from register AD, the value is retained even when changing from comparator mode to A/D conversion mode. Note that the comparator register can be written and read at only comparator mode. If the value in the comparator register is n, the logic value of comparison voltage Vref generated by the built-in DA converter can be determined from the following formula: Logic value of comparison voltage Vref Vref = VDD 256 ✕n (13) Notes for the use of A/D conversion 1 Note the following when using the analog input pins also for port P2 function: • Selection of analog input pins Even when P20 /AIN0, P21/AIN1 are set to pins for analog input, they continue to function as port P2 input/output. Accordingly, when any of them are used as I/O port and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to “1.” Also, the port input function of the pin functions as an analog input is undefined. • TALA instruction When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is “0.” (14) Notes for the use of A/D conversion 2 Do not change the operating mode (both A/D conversion mode and comparator mode) of A/D converter with the bit 3 of register Q1 while the A/D converter is operating. When the operating mode of A/D converter is changed from the comparator mode to A/D conversion mode with the bit 3 of register Q1, note the following; • Clear the bit 2 of register V2 to “0” to change the operating mode of the A/D converter from the comparator mode to A/D conversion mode with the bit 3 of register Q1. • The A/D conversion completion flag (ADF) may be set when the operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode. Accordingly, set a value to the bit 3 of register Q1, and execute the SNZAD instruction to clear the ADF flag. n: The value of register AD (n = 0 to 255) (11) Comparison result store flag (ADF) In comparator mode, the ADF flag, which shows completion of A/D conversion, stores the results of comparing the analog input voltage with the comparison voltage. When the analog input voltage is lower than the comparison voltage, the ADF flag is set to “1.” The state of ADF flag can be examined with the skip instruction (SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction. The ADF flag is cleared to “0” when the interrupt occurs or when the next instruction is skipped with the skip instruction. ADST instruction 8 machine cycles Comparison result store flag(ADF) DAC operation signal Comparator operation completed. (The value of ADF is determined) Fig. 31 Comparator operation timing chart → Rev.3.01 2005.02.07 REJ03B0104-0301 page 35 of 112 4501 Group (15) Definition of A/D converter accuracy The A/D conversion accuracy is defined below (refer to Figure 32). • Relative accuracy ➀ Zero transition voltage (V0T) This means an analog input voltage when the actual A/D conversion output data changes from “0” to “1.” ➁ Full-scale transition voltage (VFST) This means an analog input voltage when the actual A/D conversion output data changes from “1023” to ”1022.” ➂ Linearity error This means a deviation from the line between V0T and VFST of a converted value between V0T and VFST. ➃ Differential non-linearity error This means a deviation from the input potential difference required to change a converter value between V0T and VFST by 1 LSB at the relative accuracy. • Absolute accuracy This means a deviation from the ideal characteristics between 0 to VDD of actual A/D conversion characteristics. Vn: Analog input voltage when the output data changes from “n” to “n+1” (n = 0 to 1022) • 1LSB at relative accuracy → VFST–V0T (V) 1022 VDD 1024 • 1LSB at absolute accuracy → (V) Output data 1023 1022 Full-scale transition voltage (VFST) Differential non-linearity error = b–a [LSB] a Linearity error = c [LSB] a b a n+1 n Actual A/D conversion characteristics c a: 1LSB by relative accuracy b: Vn+1–Vn c: Difference between ideal Vn a n d a ct u a l V n Ideal line of A/D conversion between V0–V1022 1 0 V0 V1 Zero transition voltage (V0T) Vn Vn+1 V1022 Analog voltage VDD Fig. 32 Definition of A/D conversion accuracy Rev.3.01 2005.02.07 REJ03B0104-0301 page 36 of 112 4501 Group RESET FUNCTION System reset is performed by applying “L” level to RESET pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended operating conditions. Then when “H” level is applied to RESET pin, software starts from address 0 in page 0. f(XIN) RESET On-chip oscillator (internal oscillator) is counted 5359 times. Program starts (address 0 in page 0) Fig. 33 Reset release timing Reset input = On-chip oscillator (internal oscillator) is 1 machine cycle or more counted 5359 times. 0.85VDD RESET 0.3VDD Program starts (address 0 in page 0) (Note) Note: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions. Fig. 34 RESET pin input waveform and reset operation Rev.3.01 2005.02.07 REJ03B0104-0301 page 37 of 112 4501 Group (1) Power-on reset Reset can be automatically performed at power on (power-on reset) by the built-in power-on reset circuit. When the built-in power-on reset circuit is used, the time for the supply voltage to rise from 0 V to 2.0 V must be set to 100 µs or less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and VSS at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage. 100 µs or less VDD (Note 3) Pull-up transistor (Note 1) (Note 2) Power-on reset circuit output RESET pin (Note 1) Internal reset signal Power-on reset circuit Volgate drop detection circuit Watchdog reset signal WEF Internal reset signal Reset state Power-on Reset released This symbol represents a parasitic diode. Notes 1: 2: Applied potential to RESET pin must be VDD or less. 3: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions. Fig. 35 Structure of reset pin and its peripherals, and power-on reset operation Table 14 Port state at reset Name D0, D1 D2/C, D3/K P00, P01, P02, P03 P10, P11, P12/CNTR, P13/INT P20/AIN0, P21/AIN1 Notes 1: Output latch is set to “1.” 2: Pull-up transistor is turned OFF. Function D 0, D 1 D 2, D 3 P00–P03 P10–P13 P20, P21 High-impedance (Note 1) High-impedance (Notes 1, 2) High-impedance (Notes 1, 2) High-impedance (Notes 1, 2) High-impedance (Notes 1, 2) State Rev.3.01 2005.02.07 REJ03B0104-0301 page 38 of 112 4501 Group (2) Internal state at reset Figure 36 shows internal state at reset (they are the same after system is released from reset). The contents of timers, registers, flags and RAM except shown in Figure 36 are undefined, so set the initial value to them. • Program counter (PC) .......................................................................................................... 0 00000 Address 0 in page 0 is set to program counter. • Interrupt enable flag (INTE) .................................................................................................. 0 • Power down flag (P) ............................................................................................................. 0 • External 0 interrupt request flag (EXF0) .............................................................................. 0 • Interrupt control register V1 .................................................................................................. 0 000 • Interrupt control register V2 .................................................................................................. 0 000 • Interrupt control register I1 ................................................................................................... 0 000 • Timer 1 interrupt request flag (T1F) ..................................................................................... 0 • Timer 2 interrupt request flag (T2F) ..................................................................................... 0 • Watchdog timer flags (WDF1, WDF2) .................................................................................. 0 • Watchdog timer enable flag (WEF) ...................................................................................... 1 • Timer control register W1 ..................................................................................................... 0 000 • Timer control register W2 ..................................................................................................... 0 000 • Timer control register W6 ..................................................................................................... 0 000 • Clock control register MR ..................................................................................................... 0 110 • Key-on wakeup control register K0 ...................................................................................... 0 000 • Key-on wakeup control register K1 ...................................................................................... 0 000 • Key-on wakeup control register K2 ...................................................................................... 0 000 • Pull-up control register PU0 ................................................................................................. 0 000 • Pull-up control register PU1 ................................................................................................. 0 000 • Pull-up control register PU2 ................................................................................................. 0 000 • A/D conversion completion flag (ADF) ................................................................................. 0 • A/D control register Q1 ......................................................................................................... 0 000 • Carry flag (CY) ...................................................................................................................... 0 • Register A ............................................................................................................................. 0 000 • Register B ............................................................................................................................. 0 000 • Register D ............................................................................................................................. ✕ ✕✕ • Register E ............................................................................................................................. ✕ ✕✕✕✕✕✕✕ • Register X ............................................................................................................................. 0 000 • Register Y ............................................................................................................................. 0 000 • Register Z ............................................................................................................................. ✕ ✕ • Stack pointer (SP) ................................................................................................................ 1 11 • Oscillation clock ..................................................................... On-chip oscillator (operating) • Ceramic resonator circuit ..................................................................................... Operating • RC oscillation circuit ...................................................................................................... Stop 0 0 0 0 0 0 0 0 (Interrupt disabled) (Interrupt disabled) (Interrupt disabled) (Prescaler and timer 1 stopped) (Timer 2 stopped) “ ✕ ” r epresents undefined. Fig. 36 Internal state at reset Rev.3.01 2005.02.07 REJ03B0104-0301 page 39 of 112 4501 Group VOLTAGE DROP DETECTION CIRCUIT The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value. Q S R EPOF instruction +POF2 instruction (continuous execution) Reset signal Return input (Note 1) VDD VRST – + (Note 2) Voltage drop detection circuit reset signal Voltage drop detection circuit Notes 1: In the RAM back-up mode by the POF2 instruction, the voltage drop detection circuit stops. 2: When the VDD (supply voltage) is VRST (detection voltage) or less, the voltage drop detection circuit reset signal is output. Fig. 37 Voltage drop detection circuit VDD VRST (detection voltage) Voltage drop detection circuit reset signal Note 3 The microcomputer starts operation after the on-chip oscillator (internal oscillator) is counted 5359 times. RESET pin Notes 1: After system is released from reset, the on-chip oscillator (internal oscillator) is selected as the operation clock of the microcomputer. 2: Refer to the voltage drop detection circuit characteristics in the electrical characteristics for the rating value of VRST (detection voltage). 3: The VRST (detection voltage) does not include hysteresis. Fig. 38 Voltage drop detection circuit operation waveform example Rev.3.01 2005.02.07 REJ03B0104-0301 page 40 of 112 4501 Group RAM BACK-UP MODE The 4501 Group has the RAM back-up mode. When the POF or POF2 instruction is executed continuously after the EPOF instruction, system enters the RAM back-up state. The POF or POF2 instruction is equal to the NOP instruction when the EPOF instruction is not executed before the POF or POF2 instruction. As oscillation stops retaining RAM, the function of reset circuit and states at RAM back-up mode, current dissipation can be reduced without losing the contents of RAM. In the RAM back-up mode by the POF instruction, system enters the RAM back-up mode and the voltage drop detection cicuit keeps operating. In the RAM back-up mode by the POF2 instruction, all internal periperal functions stop. Table 15 shows the function and states retained at RAM back-up. Figure 39 shows the state transition. Table 15 Functions and states retained at RAM back-up RAM back-up Function Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2) Contents of RAM Port level Selected oscillation circuit Timer control register W1 Timer control registers W2, W6 Clock control register MR Interrupt control registers V1, V2 Interrupt control register I1 Timer 1 function Timer 2 function A/D conversion function Voltage drop detection circuit A/D control register Q1 Pull-up control registers PU0 to PU2 Key-on wakeup control registers K0 to K2 External 0 interrupt request flag (EXF0) Timer 1 interrupt request flag (T1F) Timer 2 interrupt request flag (T2F) Watchdog timer flags (WDF1) Watchdog timer enable flag (WEF) 16-bit timer (WDT) A/D conversion completion flag (ADF) Interrupt enable flag (INTE) POF ✕ O (Note 6) O ✕ O ✕ ✕ O ✕ (Note 3) ✕ O (Note 5) O O O ✕ ✕ (Note 3) ✕ ✕ ✕ POF2 ✕ O (Note 6) O ✕ O ✕ ✕ O ✕ (Note 3) ✕ ✕ O O O ✕ ✕ (Note 3) ✕ ✕ ✕ (1) Identification of the start condition Warm start (return from the RAM back-up state) or cold start (return from the normal reset state) can be identified by examining the state of the power down flag (P) with the SNZP instruction. (2) Warm start condition When the external wakeup signal is input after the system enters the RAM back-up state by executing the EPOF instruction and POF or POF2 instruction continuously, the CPU starts executing the program from address 0 in page 0. In this case, the P flag is “1.” ✕ (Note 4) ✕ (Note 4) ✕ (Note 4) ✕ (Note 4) (3) Cold start condition The CPU starts executing the program from address 0 in page 0 when; • reset pulse is input to RESET pin, or • reset by watchdog timer is performed, or • voltage drop detection circuit is detected by the voltage drop In this case, the P flag is “0.” Notes 1: “O” represents that the function can be retained, and “ ✕” represents that the function is initialized. Registers and flags other than the above are undefined at RAM back-up, and set an initial value after returning. 2: The stack pointer (SP) points the level of the stack register and is initialized to “7” at RAM back-up. 3: The state of the timer is undefined. 4: Initialize the watchdog timer flag WDF1 with the WRST instruction, and then execute the POF or POF2 instruction. 5: This function is operating in the RAM back-up mode. When the voltage drop is detected, system reset occurs. 6: As for the D2/C pin, the output latch of port C is set to “1” at the RAM back-up. However, the output latch of port D2 is retained. As for the other ports, their output levels are retained at the RAM back-up. Rev.3.01 2005.02.07 REJ03B0104-0301 page 41 of 112 4501 Group (4) Return signal An external wakeup signal is used to return from the RAM back-up mode because the oscillation is stopped. Table 16 shows the return condition for each return source. (5) Control registers • Key-on wakeup control register K0 Register K0 controls the port P0 key-on wakeup function. Set the contents of this register through register A with the TK0A instruction. In addition, the TAK0 instruction can be used to transfer the contents of register K0 to register A. • Key-on wakeup control register K1 Register K1 controls the port P1 key-on wakeup function. Set the contents of this register through register A with the TK1A instruction. In addition, the TAK1 instruction can be used to transfer the contents of register K0 to register A. • Key-on wakeup control register K2 Register K2 controls the ports P2, D2/C and D3/K key-on wakeup function. Set the contents of this register through register A with the TK2A instruction. In addition, the TAK2 instruction can be used to transfer the contents of register K2 to register A. • Pull-up control register PU0 Register PU0 controls the ON/OFF of the port P0 pull-up transistor. Set the contents of this register through register A with the TPU0A instruction. • Pull-up control register PU1 Register PU1 controls the ON/OFF of the port P1 pull-up transistor. Set the contents of this register through register A with the TPU1A instruction. • Pull-up control register PU2 Register PU2 controls the ON/OFF of the ports P2, D2/C and D3/ K pull-up transistor. Set the contents of this register through register A with the TPU2A instruction. • Interrupt control register I1 Register I1 controls the valid waveform of the external 0 interrupt, the input control of INT pin and the return input level. Set the contents of this register through register A with the TI1A instruction. In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A. External wakeup signal Table 16 Return source and return condition Return source Return condition Port P0 Return by an external “L” level input. Port P1 (Note) Port P2 Ports D2/C, D3/K Port P13/INT (Note) Return by an external “H” level or “ L ” l evel input. The return level can be selected with the bit 2 (I12) of register I1. When the return level is input, the EXF0 flag is not set. Remarks The key-on wakeup function can be selected by one port unit. Set the port using the key-on wakeup function to “H” level before going into the RAM back-up state. Select the return level (“L” level or “H” level) with the bit 2 of register I1 according to the external state before going into the RAM back-up state. Note: When the bit 3 (K1 3) of register K1 is “0”, the key-on wakeup of the INT pin is valid (“H” or “L” level). It is “1”, the key-on wakeup of port P13 is valid (“L” level). Rev.3.01 2005.02.07 REJ03B0104-0301 page 42 of 112 4501 Group D RAM back-up (Voltage drop detection circuit is operating.) POF instruction execution B Operating Operation source clock: ceramic resonator POF2 instruction execution E RAM back-up (All functions of microcomputer stop) Key-on wakeup (Stabilizing time b ) On-chip oscillator: stop RC oscillation circuit: stop CMCK instruction execution (Note 3) POF instruction execution Key-on wakeup (Stabilizing time b ) A Operating POF2 instruction execution Operation source clock: on-chip oscillator clock Ceramic resonator: operating (Note 2) RC oscillation circuit: stop CRCK instruction execution (Note 3) Key-on wakeup (Stabilizing time a ) Voltage drop detected Reset (Stabilizing time a ) Key-on wakeup (Stabilizing time a ) POF instruction execution C Operating Operation source clock: RC oscillation POF2 instruction execution Key-on wakeup (Stabilizing time c ) Operation source clock: stop On-chip oscillator: stop Ceramic resonator: stop Key-on wakeup (Stabilizing time c ) Operation source clock: stop Stabilizing time a : Microcomputer starts its operation after counting the on-chip oscillator clock 5359 times by hardware. Stabilizing time b : Microcomputer starts its operation after counting the f(XIN) 5359 times by hardware. Stabilizing time c : Microcomputer starts its operation after counting the f(XIN) 165 times by hardware. Notes 1: Continuous execution of the EPOF instruction and the POF or POF2 instruction is required to go into the RAM back-up state. 2: Through the ceramic resonator is operating, the on-chip oscillator clock is selected as the operation source clock. 3: The oscillator clock corresponding to each instruction is selected as the operation source clock, and the on-chip oscillator is stopped. Fig. 39 State transition POF or EPOF instruction + POF2 instruction Reset input Power down flag P S Q Program start P = “1” ? No Cold start Yes R POF or EPOF instruction + POF2 instruction q Clear source • • • • • • Reset input q Set source ••••••• Warm start Fig. 40 Set source and clear source of the P flag Fig. 41 Start condition identified example using the SNZP instruction Rev.3.01 2005.02.07 REJ03B0104-0301 page 43 of 112 4501 Group Table 17 Key-on wakeup control register Key-on wakeup control register K0 K03 K02 K01 K00 Port P03 key-on wakeup control bit Port P02 key-on wakeup control bit Port P01 key-on wakeup control bit Port P00 key-on wakeup control bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup control register K1 K13 K12 K11 K10 Port P13/INT key-on wakeup control bit Port P12/CNTR key-on wakeup control bit Port P11 key-on wakeup control bit Port P10 key-on wakeup control bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W P13 key-on wakeup not used/INT pin key-on wakeup used P13 key-on wakeup used/INT pin key-on wakeup not used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup control register K2 K23 K22 K21 K20 Port D3/K key-on wakeup control bit Port D2/C key-on wakeup control bit Port P21/AIN1 key-on wakeup control bit Port P20/AIN0 key-on wakeup control bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Note: “R” represents read enabled, and “W” represents write enabled. Rev.3.01 2005.02.07 REJ03B0104-0301 page 44 of 112 4501 Group Table 18 Pull-up control register and interrupt control register Pull-up control register PU0 PU03 PU02 PU01 PU00 Port P03 pull-up transistor control bit Port P02 pull-up transistor control bit Port P01 pull-up transistor control bit Port P00 pull-up transistor control bit Pull-up control register PU1 PU13 PU12 PU11 PU10 Port P13/INT pull-up transistor control bit Port P12/CNTR pull-up transistor control bit Port P11 pull-up transistor control bit Port P10 pull-up transistor control bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at RAM back-up : state retained W at RAM back-up : state retained W Pull-up control register PU2 PU23 PU22 PU21 PU20 Port D3/K pull-up transistor control bit Port D2/C pull-up transistor control bit Port P21/AIN1 pull-up transistor control bit Port P20/AIN0 pull-up transistor control bit 0 1 0 1 0 1 0 1 at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at RAM back-up : state retained W Interrupt control register I1 I13 INT pin input control bit (Note 2) 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W INT pin input disabled INT pin input enabled Falling waveform (“L” level of INT pin is recognized with the SNZI0 instruction)/“L” level Rising waveform (“H” level of INT pin is recognized with the SNZI0 instruction)/“H” level One-sided edge detected Both edges detected Disabled Enabled I12 Interrupt valid waveform for INT pin/ return level selection bit (Note 2) I11 I10 INT pin edge detection circuit control bit INT pin timer 1 control enable bit Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction when the bit 0 (V10 ) of register V1 to “0”. In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is performed with the SNZ0 instruction. Rev.3.01 2005.02.07 REJ03B0104-0301 page 45 of 112 4501 Group CLOCK CONTROL The clock control circuit consists of the following circuits. • On-chip oscillator (internal oscillator) • Ceramic resonator • RC oscillation circuit • Multi-plexer (clock selection circuit) • Frequency divider • Internal clock generating circuit The system clock and the instruction clock are generated as the source clock for operation by these circuits. Figure 42 shows the structure of the clock control circuit. The 4501 Group operates by the on-chip oscillator clock (f(RING)) which is the internal oscillator after system is released from reset. Also, the ceramic resonator or the RC oscillation can be used for the source oscillation (f(X IN)) of the 4501 Group. The CMCK instruction or CRCK instruction is executed to select the ceramic resonator or RC oscillator, respectively. Division circuit divided by 8 divided by 4 MR3, MR2 11 10 01 00 System clock Internal clock generation circuit (divided by 3) On-chip oscillator (internal oscillator) (Note 1) Instruction clock Counter divided by 2 Multiplexer QS QR RC oscillation circuit QS R XIN XOUT CRCK instruction Wait time (Note 2) control circuit Program start signal Ceramic resonator circuit QS R QS R CMCK instruction RESET pin Key-on wakeup signal POF or EPOF instruction + POF2 instruction Notes 1: System operates by the on-chip oscillator clock (f(RING)) until the CMCK or CRCK instruction is executed after system is released from reset. 2: The wait time control circuit is used to generate the time required to stabilize the f(XIN) oscillation. After the certain oscillation stabilizing wait time elapses, the program start signal is output. This circuit operates when system is released from reset or returned from RAM back-up. Fig. 42 Clock control circuit structure Rev.3.01 2005.02.07 REJ03B0104-0301 page 46 of 112 4501 Group (1) Selection of source oscillation (f(XIN)) The ceramic resonator or RC oscillation can be used for the source oscillation of the MCU. After system is released from reset, the MCU starts operation by the clock output from the on-chip oscillator which is the internal oscillator. When the ceramic resonator is used, execute the CMCK instruction. When the RC oscillation is used, execute the CRCK instruction. The oscillation circuit by the CMCK or CRCK instruction can be selected only at once. The oscillation circuit corresponding to the first executed one of these two instructions is valid. Other oscillation circuit and the on-chip oscillator stop. Execute the CMCK or the CRCK instruction in the initial setting routine of program (executing it in address 0 in page 0 is recommended). Also, when the CMCK or the CRCK instruction is not executed in program, the MCU operates by the on-chip oscillator. Reset On-chip oscillator operation CMCK instruction CRCK instruction • Ceramic resonator valid • RC oscillation valid • On-chip oscillator stop • On-chip oscillator stop • Ceramic resonator stop • RC oscillation stop Fig. 43 Switch to ceramic resonance/RC oscillation 4501 o eh n uc n * DnodnCtRuCsK itnsetrCMtiCK iin sptrrogtriaom. a uc on XOUT (2) On-chip oscillator operation When the MCU operates by the on-chip oscillator as the source oscillation (f(X IN)) without using the ceramic resonator or the RC oscillator, connect XIN pin to VSS and leave XOUT pin open (Figure 44). The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. XIN Fig. 44 Handling of XIN and XOUT when operating on-chip oscillator 4501 (3) Ceramic resonator When the ceramic resonator is used as the source oscillation (f(XIN)), connect the ceramic resonator and the external circuit to pins XIN a nd XOUT a t the shortest distance. Then, execute the CMCK instruction. A feedback resistor is built in between pins XIN and XOUT (Figure 45). * Execute the CMCK instruction in program. XOUT Note: Externally connect a damping resistor Rd depending on the oscillation frequency. Rd (A feedback resistor is built-in.) Use the resonator manufacturer’s recommended value COUT because constants such as capacitance depend on the resonator. XIN CIN (4) RC oscillation When the RC oscillation is used as the source oscillation (f(XIN)), connect the XIN pin to the external circuit of resistor R and the capacitor C at the shortest distance and leave XOUT pin open. Then, execute the CRCK instruction (Figure 46). The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits. Fig. 45 Ceramic resonator external circuit 4501 R C XIN XOUT * ExsercuuctteiotnhenCpRoCgKam. in t irr Fig. 46 External RC oscillation circuit Rev.3.01 2005.02.07 REJ03B0104-0301 page 47 of 112 4501 Group (5) External clock When the external signal clock is used as the source oscillation (f(XIN)), connect the XIN pin to the clock source and leave XOUT pin open. Then, execute the CMCK instruction (Figure 47). Be careful that the maximum value of the oscillation frequency when using the external clock differs from the value when using the ceramic resonator (refer to the recommended operating condition). Also, note that the RAM back-up mode (POF and POF2 instructions) cannot be used when using the external clock. 4501 * ExsercuuctteiotnhenCpMoCKam. in t i r gr XOUT VD D VSS XIN (6) Clock control register MR Register MR controls system clock. Set the contents of this register through register A with the TMRA instruction. In addition, the TAMR instruction can be used to transfer the contents of register MR to register A. Table 19 Clock control register MR Clock control register MR MR3 System clock selection bits MR2 MR1 MR0 Not used Not used External oscillation circuit Fig. 47 External clock input circuit at reset : 11002 MR3 MR2 0 0 0 1 1 0 1 1 0 1 0 1 at RAM back-up : 11002 System clock R/W f(XIN) (high-speed mode) f(XIN)/2 (middle-speed mode) f(XIN)/4 (low-speed mode) f(XIN)/8 (default mode) This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Note : “R” represents read enabled, and “W” represents write enabled. ROM ORDERING METHOD Please submit the information described below when ordering Mask ROM. (1) Mask ROM Order Confirmation Form ..................................... 1 (2) Data to be written into mask ROM ............................... EPROM (three sets containing the identical data) (3) Mark Specification Form .......................................................... 1 ✽For the mask ROM confirmation and the mark specifications, refer to the “Renesas Technology Corp.” Homepage (http://www.renesas.com/en/rom). Rev.3.01 2005.02.07 REJ03B0104-0301 page 48 of 112 4501 Group LIST OF PRECAUTIONS ➀ Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up; • connect a bypass capacitor (approx. 0.1 µF) between pins VDD and VSS at the shortest distance, • equalize its wiring in width and length, and • use relatively thick wire. In the One Time PROM version, CNVSS pin is also used as VPP pin. Accordingly, when using this pin, connect this pin to VSS through a resistor about 5 kΩ (connect this resistor to CNVSS/ VPP pin as close as possible). ➁ Register initial values 1 The initial value of the following registers are undefined after system is released from reset. After system is released from reset, set initial values. • Register Z (2 bits) • Register D (3 bits) • Register E (8 bits) ➂ Register initial values 2 The initial value of the following registers are undefined at RAM back-up. After system is returned from RAM back-up, set initial values. • Register Z (2 bits) • Register X (4 bits) • Register Y (4 bits) • Register D (3 bits) • Register E (8 bits) ➃ Stack registers (SKS) and stack pointer (SP) Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. ➄ Prescaler Stop the prescaler operation to change its frequency dividing ratio. ➅Timer count source Stop timer 1 or 2 counting to change its count source. ➆ Reading the count value Stop timer 1 or 2 counting and then execute the TAB1 or TAB2 instruction to read its data. ➇ Writing to the timer Stop timer 1 or 2 counting and then execute the T1AB or T2AB instruction to write its data. ➈ Writing to reload register R1 When writing data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows. 10 Timer 1 and timer 2 count start timing and count time when operation starts Count starts from the first rising edge of the count source (2) after timer 1 and timer 2 operations start (1). Time to first underflow (3) is shorter (for up to 1 period of the count source) than time among next underflow (4) by the timing to start the timer and count source operations after count starts. When selecting CNTR input as the count source of timer 2, timer 2 operates synchronizing with the falling edge of CNTR input. (2) Count Source Count Source (CNTR input) Timer Value 3 2 1 0 3 2 1 0 3 2 Timer Underflow Signal (3) (1) Timer (4) Fig. 48 Timer count start timing and count time when operation starts (T1, T2) 11 Watchdog timer • The watchdog timer function is valid after system is released from reset. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously, and clear the WEF flag to “0” to stop the watchdog timer function. • The watchdog timer function is valid after system is returned from the RAM back-up. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously every system is returned from the RAM back-up, and stop the watchdog timer function. 12 Multifunction • The input/output of D2, D3, P12 and P13 can be used even when C, K, CNTR (input) and INT are selected. • The input of P12 can be used even when CNTR (output) is selected. • The input/output of P20 and P21 can be used even when AIN0 and AIN1 are selected. 13 Program counter Make sure that the PCH does not specify after the last page of the built-in ROM. POF and POF2 instructions When the POF or POF2 instruction is executed continuously after the EPOF instruction, system enters the RAM back-up state. Note that system cannot enter the RAM back-up state when executing only the POF or POF2 instruction. Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction and the POF or POF2 instruction continuously. 14 Rev.3.01 2005.02.07 REJ03B0104-0301 page 49 of 112 4501 Group 15 P13/INT pin Note [1] on bit 3 of register I1 When the input of the INT pin is controlled with the bit 3 of register I1 in software, be careful about the following notes. Note [3] on bit 2 of register I1 When the interrupt valid waveform of the P13/INT pin is changed with the bit 2 of register I1 in software, be careful about the following notes. • Depending on the input state of the P13/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 51➀) and then, change the bit 2 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to Figure 51➁). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 51➂). • Depending on the input state of the P13/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 49➀) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction (refer to Figure 49➁). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 49➂). ••• LA 4 TV1A LA 8 TI1A NOP SNZ0 NOP ; (✕✕✕02) ; The SNZ0 instruction is valid ........... ➀ ; (1✕✕✕2) ; Control of INT pin input is changed ........................................................... ➁ ; The SNZ0 instruction is executed (EXF0 flag cleared) ........................................................... ➂ ••• LA 4 TV1A LA 12 TI1A NOP SNZ0 NOP ••• ; (✕✕✕02) ; The SNZ0 instruction is valid ........... ➀ ; (✕1✕✕2) ; Interrupt valid waveform is changed ........................................................... ➁ ; The SNZ0 instruction is executed (EXF0 flag cleared) ........................................................... ➂ Fig. 49 External 0 interrupt program example-1 Note [2] on bit 3 of register I1 When the bit 3 of register I1 is cleared to “0”, the RAM back-up mode is selected and the input of INT pin is disabled, be careful about the following notes. • When the key-on wakeup function of port P13 is not used (register K1 3 = “ 0 ” ), clear bits 2 and 3 of register I1 before system enters to the RAM back-up mode. (refer to Figure 50➀). ✕ : these bits are not used here. Fig. 51 External 0 interrupt program example-3 ••• LA 0 TI1A DI EPOF POF ; (00✕✕2) ; Input of INT disabled ........................ ➀ ; RAM back-up ✕ : these bits are not used here. Fig. 50 External 0 interrupt program example-2 Rev.3.01 2005.02.07 REJ03B0104-0301 ••• page 50 of 112 ••• ✕ : these bits are not used here. 4501 Group 16 Notes for the use of A/D conversion 1 Note the following when using the analog input pins also for port P2 function: • Selection of analog input pins Even when P20/AIN0 and P21/AIN1 are set to pins for analog input, they continue to function as port P2 input/output. Accordingly, when any of them are used as I/O port and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to “1.” Also, the port input function of the pin functions as an analog input is undefined. • TALA instruction When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is “0.” Notes for the use of A/D conversion 2 Do not change the operating mode (both A/D conversion mode and comparator mode) of A/D converter with the bit 3 of register Q1 while the A/D converter is operating. When the operating mode of A/D converter is changed from the comparator mode to A/D conversion mode with the bit 3 of register Q1, note the following; • Clear the bit 2 of register V2 to “ 0 ” ( refer to Figure 52 ➀ ) to change the operating mode of the A/D converter from the comparator mode to A/D conversion mode with the bit 3 of register Q1. • The A/D conversion completion flag (ADF) may be set when the operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode. Accordingly, set a value to the bit 3 of register Q1, and execute the SNZAD instruction to clear the ADF flag. 18 Notes for the use of A/D conversion 3 Each analog input pin is equipped with a capacitor which is used to compare the analog voltage. Accordingly, when the analog voltage is input from the circuit with high-impedance and, charge/ discharge noise is generated and the sufficient A/D accuracy may not be obtained. Therefore, reduce the impedance or, connect a capacitor (0.01 µF to 1 µF) to analog input pins (Figure 53). When the overvoltage applied to the A/D conversion circuit may occur, connect an external circuit in order to keep the voltage within the rated range as shown the Figure 54. In addition, test the application products sufficiently. Sensor AIN 17 Apply the voltage withiin the specifications to an analog input pin. Fig. 53 Analog input external circuit example-1 About 1kΩ Sensor AIN ••• LA 8 TV2A LA 0 TQ1A ; (✕0✕✕2) ; The SNZAD instruction is valid ........ ➀ ; (0✕✕✕2) ; Operation mode of A/D converter is changed from comparator mode to A/D conversion mode. Fig. 54 Analog input external circuit example-2 SNZAD NOP ✕ : these bits are not used here. Fig. 52 A/D conversion interrupt program example Rev.3.01 2005.02.07 REJ03B0104-0301 ••• page 51 of 112 4501 Group 19 Power-on reset Reset can be automatically performed at power on (power-on reset) by the built-in power-on reset circuit. When the built-in power-on reset circuit is used, the time for the supply voltage to rise from 0 V to 2.0 V must be set to 100 µs or less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and VSS at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage. Clock control Execute the CMCK or the CRCK instruction in the initial setting routine of program (executing it in addres 0 in page 0 is recommended). The oscillation circuit by the CMCK or CRCK instruction can be selected only at once. The oscillation circuit corresponding to the first executed one of these two instruction is valid. Other oscillation circuits and the on-chip oscillator stop. On-chip oscillator The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. Also, the oscillation stabilize wait time after system is released from reset is generated by the on-chip oscillator clock. When considering the oscillation stabilize wait time after system is released from reset, be careful that the variable frequency of the on-chip oscillator clock. External clock When the external signal clock is used as the source oscillation (f(X IN)), note that the RAM back-up mode (POF and POF2 instructions) cannot be used. Electric Characteristic Differences Between Mask ROM and One Time PROM Version MCU There are differences in electric characteristics, operation margin, noise immunity, and noise radiation between Mask ROM and One Time PROM version MCUs due to the difference in the manufacturing processes. When manufacturing an application system with the One time PROM version and then switching to use of the Mask ROM version, please perform sufficient evaluations for the commercial samples of the Mask ROM version. Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. 20 21 22 23 24 Rev.3.01 2005.02.07 REJ03B0104-0301 page 52 of 112 4501 Group CONTROL REGISTERS Interrupt control register V1 V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit Not used External 0 interrupt enable bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : 00002 R/W Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) (Note 2) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) (Note 2) This bit has no function, but read/write is enabled. Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) (Note 2) Interrupt control register V2 V23 V22 V21 V20 Not used A/D interrupt enable bit Not used Not used 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : 00002 R/W This bit has no function, but read/write is enabled. Interrupt disabled (SNZAD instruction is valid) Interrupt enabled (SNZAD instruction is invalid) (Note 2) This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Interrupt control register I1 I13 INT pin input control bit (Note 3) 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W INT pin input disabled INT pin input enabled Falling waveform (“L” level of INT pin is recognized with the SNZI0 instruction)/“L” level Rising waveform (“H” level of INT pin is recognized with the SNZI0 instruction)/“H” level One-sided edge detected Both edges detected Disabled Enabled I12 Interrupt valid waveform for INT pin/ return level selection bit (Note 3) I11 I10 INT pin edge detection circuit control bit INT pin timer 1 control enable bit Clock control register MR MR3 System clock selection bits MR2 MR1 MR0 Not used Not used at reset : 11002 MR3 MR2 0 0 0 1 1 0 1 1 0 1 0 1 at RAM back-up : 11002 System clock R/W f(XIN) (high-speed mode) f(XIN)/2 (middle-speed mode) f(XIN)/4 (low-speed mode) f(XIN)/8 (default mode) This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: These instructions are equivalent to the NOP instruction. 3: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction when the bit 0 (V1 0) of register V1 to “0”. In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is performed with the SNZ0 instruction. Rev.3.01 2005.02.07 REJ03B0104-0301 page 53 of 112 4501 Group Timer control register W1 W13 W12 W11 W10 Prescaler control bit Prescaler dividing ratio selection bit Timer 1 control bit Timer 1 count start synchronous circuit control bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : 00002 R/W Stop (state initialized) Operating Instruction clock divided by 4 Instruction clock divided by 16 Stop (state retained) Operating Count start synchronous circuit not selected Count start synchronous circuit selected Timer control register W2 W23 W22 W21 Timer 2 count source selection bits W20 Timer 2 control bit Timer 1 count auto-stop circuit selection bit (Note 2) 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W Stop (state retained) Operating Count auto-stop circuit not selected Count auto-stop circuit selected W21 W20 Count source 0 Timer 1 underflow signal 0 0 Prescaler output (ORCLK) 1 1 CNTR input 0 1 System clock 1 Timer control register W6 W63 W62 W61 W60 Not used Not used CNTR output selection bit P12/CNTR function selection bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Timer 1 underflow signal divided by 2 output Timer 2 underflow signal divided by 2 output P12(I/O)/CNTR input (Note 3) P12 (input)/CNTR input/output (Note 3) A/D control register Q1 Q13 Q12 Q11 Analog input pin selection bits Q10 A/D operation mode selection bit Not used at reset : 00002 0 1 0 1 Q11 Q10 0 0 0 1 1 0 1 1 A/D conversion mode Comparator mode at RAM back-up : state retained R/W This bit has no function, but read/write is enabled. Selected pins AIN0 AIN1 Not available Not available Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: This function is valid only when the timer 1 count start synchronization circuit is selected. 3: CNTR input is valid only when CNTR input is selected as the timer 2 count source. Rev.3.01 2005.02.07 REJ03B0104-0301 page 54 of 112 4501 Group Key-on wakeup control register K0 K03 K02 K01 K00 Port P03 key-on wakeup control bit Port P02 key-on wakeup control bit Port P01 key-on wakeup control bit Port P00 key-on wakeup control bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup control register K1 K13 K12 K11 K10 Port P13/INT key-on wakeup control bit Port P12/CNTR key-on wakeup control bit Port P11 key-on wakeup control bit Port P10 key-on wakeup control bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W P13 key-on wakeup not used/INT pin key-on wakeup used P13 key-on wakeup used/INT pin key-on wakeup not used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup control register K2 K23 K22 K21 K20 Port D3/K key-on wakeup control bit Port D2/C key-on wakeup control bit Port P21/AIN1 key-on wakeup control bit Port P20/AIN0 key-on wakeup control bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Note: “R” represents read enabled, and “W” represents write enabled. Rev.3.01 2005.02.07 REJ03B0104-0301 page 55 of 112 4501 Group Pull-up control register PU0 PU03 PU02 PU01 PU00 Port P03 pull-up transistor control bit Port P02 pull-up transistor control bit Port P01 pull-up transistor control bit Port P00 pull-up transistor control bit Pull-up control register PU1 PU13 PU12 PU11 PU10 Port P13/INT pull-up transistor control bit Port P12/CNTR pull-up transistor control bit Port P11 pull-up transistor control bit Port P10 pull-up transistor control bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at RAM back-up : state retained W at RAM back-up : state retained W Pull-up control register PU2 PU23 PU22 PU21 PU20 Port D3/K pull-up transistor control bit Port D2/C pull-up transistor control bit Port P21/AIN1 pull-up transistor control bit Port P20/AIN0 pull-up transistor control bit 0 1 0 1 0 1 0 1 at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at RAM back-up : state retained W Notes 1: “R” represents read enabled, and “W” represents write enabled. Rev.3.01 2005.02.07 REJ03B0104-0301 page 56 of 112 4501 Group INSTRUCTIONS The 4501 Group has the 111 instructions. Each instruction is described as follows; (1) Index list of instruction function (2) Machine instructions (index by alphabet) (3) Machine instructions (index by function) (4) Instruction code table SYMBOL The symbols shown below are used in the following list of instruction function and the machine instructions. Symbol A B DR E Q1 V1 V2 I1 W1 W2 W6 MR K0 K1 K2 PU0 PU1 PU2 X Y Z DP PC PCH PCL SK SP CY R1 R2 T1 T2 T1F T2F Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) Contents Symbol WDF1 WEF INTE EXF0 P ADF D P0 P1 P2 C K x y z p n i j A 3A 2A 1A 0 Contents Watchdog timer flag Watchdog timer enable flag Interrupt enable flag External 0 interrupt request flag Power down flag A/D conversion completion flag Port D (4 bits) Port P0 (4 bits) Port P1 (4 bits) Port P2 (2 bits) Port C (1 bit) Port K (1 bit) Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal constant Hexadecimal constant Hexadecimal constant Binary notation of hexadecimal variable A (same for others) Direction of data movement Data exchange between a register and memory Decision of state shown before “?” Contents of registers and memories Negate, Flag unchanged after executing instruction RAM address pointed by the data pointer Label indicating address a6 a5 a4 a3 a2 a1 a0 Label indicating address a6 a5 a4 a3 a2 a1 a0 in page p5 p4 p3 p2 p1 p0 Hex. C + Hex. number x (also same for others) A/D control register Q1 (4 bits) Interrupt control register V1 (4 bits) Interrupt control register V2 (4 bits) Interrupt control register I1 (4 bits) Timer control register W1 (4 bits) Timer control register W2 (4 bits) Timer control register W6 (4 bits) Clock control register MR (4 bits) Key-on wakeup control register K0 (4 bits) Key-on wakeup control register K1 (4 bits) Key-on wakeup control register K2 (4 bits) Pull-up control register PU0 (4 bits) Pull-up control register PU1 (4 bits) Pull-up control register PU2 (4 bits) Register X (4 bits) Register Y (4 bits) Register Z (2 bits) Data pointer (10 bits) (It consists of registers X, Y, and Z) Program counter (14 bits) High-order 7 bits of program counter Low-order 7 bits of program counter Stack register (14 bits ✕ 8) Stack pointer (3 bits) Carry flag Timer 1 reload register Timer 2 reload register Timer 1 Timer 2 Timer 1 interrupt request flag Timer 2 interrupt request flag ← ↔ ? () — M(DP) a p, a C + x Note : Some instructions of the 4501 Group has the skip function to unexecute the next described instruction. The 4501 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped. Rev.3.01 2005.02.07 REJ03B0104-0301 page 57 of 112 4501 Group INDEX LIST OF INSTRUCTION FUNCTION GroupMnemonic ing TAB TBA TAY TYA TEAB (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) (E7–E4) ← (B) (E3–E0) ← (A) TABE (B) ← (E7–E4) (A) ← (E3–E0) TDA TAD (DR2–DR0) ← (A2–A0) (A2–A0) ← (DR2–DR0) (A3) ← 0 TAZ (A1, A0) ← (Z1, Z0) (A3, A2) ← 0 AM TAX TASP (A) ← (X) (A2–A0) ← (SP2–SP0) (A3) ← 0 LXY x, y (X) ← x x = 0 to 15 (Y) ← y y = 0 to 15 68, 90 83, 90 AMC 81, 90 (A) ← (A) + (M(DP)) + (CY) (CY) ← Carry 62, 92 (A) ← (A) + (M(DP)) 62, 92 83, 90 84, 90 79, 90 78, 90 TABP p (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (Note) (PCL) ← (DR2–DR0, A3–A0) (B) ← (ROM(PC))7–4 (A) ← (ROM(PC))3–0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 78, 92 Function Page 77, 90 GroupMnemonic ing XAMI j Function (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 TMA j (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 LA n (A) ← n n = 0 to 15 68, 92 85, 90 Page 89, 90 83, 90 83, 90 88, 90 84, 90 Register to register transfer Arithmetic operation RAM to register transfer An (A) ← (A) + n n = 0 to 15 (A) ← (A) AND (M(DP)) (A) ← (A) OR (M(DP)) (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) → C Y → A 3A 2A 1A 0 62, 92 RAM addresses AND OR SC 63, 92 70, 92 73, 92 71, 92 76, 92 65, 92 71, 92 LZ z INY DEY TAM j (Z) ← z z = 0 to 3 (Y) ← (Y) + 1 (Y) ← (Y) – 1 (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 68, 90 68, 90 65, 90 RC 80, 90 SZC CMA XAM j (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 XAMD j (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) – 1 Note: p is 0 to 15 for M34501M2, p is 0 to 31 for M34501M4/E4. RAM to register transfer 89, 90 RAR 89, 90 Rev.3.01 2005.02.07 REJ03B0104-0301 page 58 of 112 4501 Group INDEX LIST OF INSTRUCTION FUNCTION (continued) GroupMnemonic ing SB j Function (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 SZB j (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15 Ba (PCL) ← a6–a0 (PCH) ← p (Note) (PCL) ← a6–a0 BLA p (PCH) ← p (Note) (PCL) ← (DR2–DR0, A3–A0) TI1A BM a (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← 2 (PCL) ← a6–a0 64, 94 TAW1 TW1A 64, 94 TAW2 TW2A TAW6 BMLA p (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (Note) (PCL) ← (DR2–DR0, A3–A0) RTI (PC) ← (SK(SP)) (SP) ← (SP) – 1 RT (PC) ← (SK(SP)) (SP) ← (SP) – 1 72, 94 72, 94 64, 94 TW6A (W6) ← (A) (B) ← (T17–T14) (A) ← (T13–T10) T1AB (R17–R14) ← (B) (T17–T14) ← (B) (R13–R10) ← (A) (T13–T10) ← (A) TAB2 (B) ← (T27–T24) (A) ← (T23–T20) T2AB (R27–R24) ← (B) (T27–T24) ← (B) (R23–R20) ← (A) (T23–T20) ← (A) Note: p is 0 to 15 for M34501M2, p is 0 to 31 for M34501M4/E4. Page 73, 92 GroupMnemonic ing DI EI (INTE) ← 0 (INTE) ← 1 Function Page 66, 96 66, 96 74, 96 Bit operation RB j 71, 92 SNZ0 76, 92 SNZI0 V10 = 0: (EXF0) = 1 ? After skipping, (EXF0) ← 0 V10 = 1: SNZ0 = NOP I12 = 1 : (INT) = “H” ? I12 = 0 : (INT) = “L” ? TAV1 TV1A TAV2 (A) ← (V1) (V1) ← (A) (A) ← (V2) (V2) ← (A) (A) ← (I1) (I1) ← (A) (A) ← (W1) (W1) ← (A) (A) ← (W2) (W2) ← (A) (A) ← (W6) 81, 96 87, 96 82, 96 87, 96 79, 96 84, 96 82, 96 87, 96 82, 96 88, 96 82, 96 88, 96 77, 96 75, 96 Comparison operation SEAM SEA n 74, 92 74, 92 63, 94 63, 94 TV2A 63, 94 TAI1 Branch operation BL p, a Subroutine operation BML p, a (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (Note) (PCL) ← a6–a0 Timer operation Interrupt operation TAB1 77, 96 Return operation RTS (PC) ← (SK(SP)) (SP) ← (SP) – 1 72, 94 78, 96 77, 96 Rev.3.01 2005.02.07 REJ03B0104-0301 page 59 of 112 4501 Group INDEX LIST OF INSTRUCTION FUNCTION (continued) Grouping Mnemonic TR1AB Function (R17–R14) ← (B) (R13–R10) ← (A) Page 87, 96 GroupMnemonic ing IAK (A0) ← (K) (A3–A1) ← 0 75, 96 OKA TK0A 76, 96 TAK0 (K) ← (A0) (K0) ← (A) (A) ← (K0) (K1) ← (A) (A) ← (K1) (K2) ← (A) (A) ← (K2) (PU0) ← (A) (PU1) ← (A) (PU2) ← (A) In A/D conversion mode (Q13 = 0), (B) ← (AD9–AD6) (A) ← (AD5–AD2) RD (D(Y)) ← 0 (Y) = 0 to 3 SD (D(Y)) ← 1 (Y) = 0 to 3 SZD (D(Y)) = 0 ? (Y) = 0 to 3 SCP RCP SNZCP (C) ← 1 (C) ← 0 (C) = 1 ? 73, 98 71, 98 75, 98 76, 98 73, 98 TALA (A3, A2) ← (AD1, AD0) (A1, A0) ← 0 80, 100 72, 98 In comparator mode (Q13 = 1), (B) ← (AD7–AD4) (A) ← (AD3–AD0) 69, 98 84, 98 79, 98 85, 98 80, 98 85, 98 80, 98 86, 98 86, 98 86, 98 78, 100 Function Page 67, 98 Timer operation SNZT1 V12 = 0: (T1F) = 1 ? After skipping, (T1F) ← 0 V12 = 1: SNZT1 = NOP SNZT2 V13 = 0: (T2F) = 1 ? After skipping, (T2F) ← 0 V13 = 1: SNZT2 = NOP Input/Output operation TK1A TAK1 TK2A TAK2 TPU0A TPU1A TPU2A IAP0 OP0A IAP1 OP1A IAP2 (A) ← (P0) (P0) ← (A) (A) ← (P1) (P1) ← (A) (A1, A0) ← (P21, P20) (A3, A2) ← 0 67, 98 69, 98 67, 98 69, 98 67, 98 OP2A CLD (P21, P20) ← (A1, A0) (D) ← 1 70, 98 TABAD 64, 98 Input/Output operation A/D conversion operation TADAB (AD7–AD4) ← (B) (AD3–AD0) ← (A) 79, 100 TAQ1 TQ1A ADST (A) ← (Q1) (Q1) ← (A) (ADF) ← 0 Q13 = 0: A/D conversion starting Q13 = 1: Comparator operation starting 81, 100 86, 100 62, 100 SNZAD V22 = 0: (ADF) = 1 ? After skipping, (ADF) ← 0 V22 = 1: SNZAD = NOP 74, 100 Rev.3.01 2005.02.07 REJ03B0104-0301 page 60 of 112 4501 Group INDEX LIST OF INSTRUCTION FUNCTION (continued) GroupMnemonic ing NOP POF Function (PC) ← (PC) + 1 RAM back-up (Voltage drop detection circuit valid) POF2 EPOF SNZP RAM back-up POF, POF2 instructions valid (P) = 1 ? Stop of watchdog timer function enabled (WDF1) = 1 ? After skipping, (WDF1) ← 0 Ceramic resonance circuit selected RC oscillation circuit selected (A) ← (MR) (MR) ← (A) 70, 100 66, 100 75, 100 66, 100 Page 69, 100 70, 100 Other operation DWDT WRST 88, 100 CMCK 65, 100 CRCK TAMR TMRA 65, 100 81, 100 85, 100 Rev.3.01 2005.02.07 REJ03B0104-0301 page 61 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) A n (Add n and accumulator) Instruction code D9 0 0 0 1 1 0 n n n D0 n 2 0 6 n Number of words 16 Number of cycles 1 Flag CY – Skip condition Overflow = 0 1 Operation: (A) ← (A) + n n = 0 to 15 Grouping: Arithmetic operation Description: Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation. Number of words 16 ADST (A/D conversion STart) Instruction code D9 1 0 1 0 0 1 1 1 1 D0 1 2 2 9 F Number of cycles 1 Flag CY – Skip condition – 1 Operation: (ADF) ← 0 Q13 = 0: A/D conversion starting Q13 = 1: Comparator operation starting (Q13 : bit 3 of A/D control register Q1) Grouping: A/D conversion operation Description: Clears (0) to A/D conversion completion flag ADF, and the A/D conversion at the A/D conversion mode (Q13 = 0) or the comparator operation at the comparator mode (Q13 = 1) is started. AM (Add accumulator and Memory) Instruction code D9 0 0 0 0 0 0 1 0 1 D0 0 2 0 0 A Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (A) + (M(DP)) Grouping: Arithmetic operation Description: Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged. AMC (Add accumulator, Memory and Carry) Instruction code D9 0 0 0 0 0 0 1 0 1 D0 1 2 0 0 B Number of words 16 Number of cycles 1 Flag CY 0/1 Skip condition – 1 Operation: (A) ← (A) + (M(DP)) + (CY) (CY) ← Carry Grouping: Arithmetic operation Description: Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. Rev.3.01 2005.02.07 REJ03B0104-0301 page 62 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) AND (logical AND between accumulator and memory) Instruction code D9 0 0 0 0 0 1 1 0 0 D0 0 2 0 1 8 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (A) AND (M(DP)) Grouping: Arithmetic operation Description: Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A. B a (Branch to address a) Instruction code D9 0 1 1 D0 a6 a5 a4 a3 a2 a1 a0 2 1 8 +a a Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (PCL) ← a6 to a0 Grouping: Branch operation Description: Branch within a page : Branches to address a in the identical page. Note: Specify the branch address within the page including this instruction. BL p, a (Branch Long to address a in page p) Instruction code D9 0 1 Operation: 0 0 1 0 1 1 D0 p4 p3 p2 p1 p0 2 0 2 E +p p Number of words 16 Number of cycles 2 Flag CY – Skip condition – 2 a6 a5 a4 a3 a2 a1 a0 2 a a 16 (PCH) ← p (PCL) ← a6 to a0 Grouping: Branch operation Description: Branch out of a page : Branches to address a in page p. Note: p is 0 to 15 for M34501M2, and p is 0 to 31 for M34501M4/E4. BLA p (Branch Long to address (D) + (A) in page p) Instruction code D9 0 1 Operation: 0 0 0 0 0 0 1 0 0 0 0 D0 0 2 0 2 1 p 0 Number of words 16 Number of cycles 2 Flag CY – Skip condition – 2 p4 0 p3 p2 p1 p0 2 p 16 (PCH) ← p (PCL) ← (DR2–DR0, A3–A0) Grouping: Branch operation Description: Branch out of a page : Branches to address (DR2 DR 1 DR 0 A3 A 2 A 1 A 0)2 specified by registers D and A in page p. Note: p is 0 to 15 for M34501M2 and p is 0 to 31 for M34501M4/E4. Rev.3.01 2005.02.07 REJ03B0104-0301 page 63 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) BM a (Branch and Mark to address a in page 2) Instruction code D9 0 1 0 D0 a6 a5 a4 a3 a2 a1 a0 2 1 a a Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← 2 (PCL) ← a6–a0 Grouping: Subroutine call operation Description: Call the subroutine in page 2 : Calls the subroutine at address a in page 2. Note: Subroutine extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. Be careful not to over the stack because the maximum level of subroutine nesting is 8. BML p, a (Branch and Mark Long to address a in page p) Instruction code D9 0 1 Operation: 0 0 1 0 1 0 D0 p4 p3 p2 p1 p0 2 0 2 C +p p Number of words 16 Number of cycles 2 Flag CY – Skip condition – 2 a6 a5 a4 a3 a2 a1 a0 2 a a 16 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← a6–a0 Grouping: Subroutine call operation Description: Call the subroutine : Calls the subroutine at address a in page p. Note: p is 0 to 15 for M34501M2 and p is 0 to 31 for M34501M4/E4. Be careful not to over the stack because the maximum level of subroutine nesting is 8. BMLA p (Branch and Mark Long to address (D) + (A) in page p) Instruction code D9 0 1 Operation: 0 0 0 0 0 1 1 0 0 0 0 D0 0 2 0 2 3 p 0 Number of words 16 Number of cycles 2 Flag CY – Skip condition – 2 p4 0 p3 p2 p1 p0 2 p 16 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← (DR2–DR0, A3–A0) Grouping: Subroutine call operation Description: Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. Note: p is 0 to 15 for M34501M2 and p is 0 to 31 for M34501M4/E4. Be careful not to over the stack because the maximum level of subroutine nesting is 8. CLD (CLear port D) Instruction code D9 0 0 0 0 0 1 0 0 0 D0 1 2 0 1 1 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (D) ← 1 Grouping: Input/Output operation Description: Sets (1) to port D. Rev.3.01 2005.02.07 REJ03B0104-0301 page 64 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) CMA (CoMplement of Accumulator) Instruction code D9 0 0 0 0 0 1 1 1 0 D0 02 0 1 C 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (A) ← (A) Grouping: Arithmetic operation Description: Stores the one’s complement for register A’s contents in register A. CMCK (Clock select: ceraMic resonance ClocK) Instruction code D9 1 0 1 0 0 1 1 0 1 D0 0 2 2 9 A Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: Ceramic resonance circuit selected Grouping: Other operation Description: Selects the ceramic resonance circuit and stops the on-chip oscillator. CRCK (Clock select: Rc resonance ClocK) Instruction code D9 1 0 1 0 0 1 1 0 1 D0 1 2 2 9 B Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: RC resonance circuit selected Grouping: Other operation Description: Selects the RC resonance circuit and stops the on-chip oscillator. DEY (DEcrement register Y) Instruction code D9 0 0 0 0 0 1 0 1 1 D0 1 2 0 1 7 Number of words 16 Number of cycles 1 Flag CY – Skip condition (Y) = 15 1 Operation: (Y) ← (Y) – 1 Grouping: RAM addresses Description: Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. Rev.3.01 2005.02.07 REJ03B0104-0301 page 65 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) DI (Disable Interrupt) Instruction code D9 0 0 0 0 0 0 0 1 0 D0 0 2 0 0 4 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (INTE) ← 0 Grouping: Interrupt control operation Description: Clears (0) to interrupt enable flag INTE, and disables the interrupt. Note: Interrupt is disabled by executing the DI instruction after executing 1 machine cycle. DWDT (Disable WatchDog Timer) Instruction code D9 1 0 1 0 0 1 1 1 0 D0 0 2 2 9 C Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: Stop of watchdog timer function enabled Grouping: Other operation Description: Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction. EI (Enable Interrupt) Instruction code D9 0 0 0 0 0 0 0 1 0 D0 1 2 0 0 5 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (INTE) ← 1 Grouping: Interrupt control operation Description: Sets (1) to interrupt enable flag INTE, and enables the interrupt. Note: Interrupt is enabled by executing the EI instruction after executing 1 machine cycle. EPOF (Enable POF instruction) Instruction code D9 0 0 0 1 0 1 1 0 1 D0 1 2 0 5 B Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: POF instruction, POF2 instruction valid Grouping: Other operation Description: Makes the immediate after POF or POF2 instruction valid by executing the EPOF instruction. Rev.3.01 2005.02.07 REJ03B0104-0301 page 66 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) IAK (Input Accumulator from port K) Instruction code D9 1 0 0 1 1 0 1 1 1 D0 1 2 2 6 F Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A0) ← (K) (A3–A1) ← 0 Grouping: Input/Output operation Description: Transfers the contents of port K to the bit 0 (A0) of register A. Note: After this instruction is executed, “ 0 ” i s stored to the high-order 3 bits (A3– A 1 ) of register A. IAP0 (Input Accumulator from port P0) Instruction code D9 1 0 0 1 1 0 0 0 0 D0 0 2 2 6 0 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (P0) Grouping: Input/Output operation Description: Transfers the input of port P0 to register A. IAP1 (Input Accumulator from port P1) Instruction code D9 1 0 0 1 1 0 0 0 0 D0 1 2 2 6 1 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (P1) Grouping: Input/Output operation Description: Transfers the input of port P1 to register A. IAP2 (Input Accumulator from port P2) Instruction code D9 1 0 0 1 1 0 0 0 1 D0 0 2 2 6 2 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A1, A0) ← (P21, P20) (A3, A2) ← 0 Grouping: Input/Output operation Description: Transfers the input of port P2 to the low-order 2 bits (A1, A0) of register A. Note: After this instruction is executed, “ 0 ” i s stored to the high-order 2 bits (A3, A2) of register A. Rev.3.01 2005.02.07 REJ03B0104-0301 page 67 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) INY (INcrement register Y) Instruction code D9 0 0 0 0 0 1 0 0 1 D0 1 2 0 1 3 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition (Y) = 0 Operation: (Y) ← (Y) + 1 Grouping: RAM addresses Description: Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed. LA n (Load n in Accumulator) Instruction code D9 0 0 0 1 1 1 n n n D0 n 2 0 7 n Number of words 16 Number of cycles 1 Flag CY – Skip condition Continuous description 1 Operation: (A) ← n n = 0 to 15 Grouping: Arithmetic operation Description: Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. LXY x, y (Load register X and Y with x and y) Instruction code D9 1 1 x3 x2 x1 x0 y3 y2 y1 D0 y0 2 3 x y Number of words 16 Number of cycles 1 Flag CY – Skip condition Continuous description 1 Operation: (X) ← x x = 0 to 15 (Y) ← y y = 0 to 15 Grouping: RAM addresses Description: Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. LZ z (Load register Z with z) Instruction code D9 0 0 0 1 0 0 1 0 z1 D0 z0 2 0 4 8 +z 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (Z) ← z z = 0 to 3 Grouping: RAM addresses Description: Loads the value z in the immediate field to register Z. Rev.3.01 2005.02.07 REJ03B0104-0301 page 68 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) NOP (No OPeration) Instruction code D9 0 0 0 0 0 0 0 0 0 D0 0 2 0 0 0 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (PC) ← (PC) + 1 Grouping: Other operation Description: No operation; Adds 1 to program counter value, and others remain unchanged. OKA (Output port K from Accumulator) Instruction code D9 1 0 0 0 0 1 1 1 1 D0 1 2 2 1 F Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (K) ← (A0) Grouping: Input/Output operation Description: Outputs the contents of bit 0 (A0) of register A to port K. OP0A (Output port P0 from Accumulator) Instruction code D9 1 0 0 0 1 0 0 0 0 D0 0 2 2 2 0 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (P0) ← (A) Grouping: Input/Output operation Description: Outputs the contents of register A to port P0. OP1A (Output port P1 from Accumulator) Instruction code D9 1 0 0 0 1 0 0 0 0 D0 1 2 2 2 1 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (P1) ← (A) Grouping: Input/Output operation Description: Outputs the contents of register A to port P1. Rev.3.01 2005.02.07 REJ03B0104-0301 page 69 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) OP2A (Output port P2 from Accumulator) Instruction code D9 1 0 0 0 1 0 0 0 1 D0 02 2 2 2 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (P21, P20) ← (A1, A0) Grouping: Input/Output operation Description: Outputs the contents of the low-order 2 bits (A1, A0) of register A to port P2. OR (logical OR between accumulator and memory) Instruction code D9 0 0 0 0 0 1 1 0 0 D0 12 0 1 9 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (A) ← (A) OR (M(DP)) Grouping: Arithmetic operation Description: Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A. POF (Power OFf1) Instruction code D9 0 0 0 0 0 0 0 0 1 D0 0 2 0 0 2 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: RAM back-up However, voltage drop detection circuit valid Grouping: Other operation Description: Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF instruction. However, the voltage drop detection circuit is valid. Note: If the EPOF instruction is not executed before executing this instruction, this instruction is equivalent to the NOP instruction. POF2 (Power OFf2) Instruction code D9 0 0 0 0 0 0 1 0 0 D0 0 2 0 0 8 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: RAM back-up Grouping: Other operation Description: Puts the system in RAM back-up state by executing the POF2 instruction after executing the EPOF instruction. Operations of all functions are stopped. Note: If the EPOF instruction is not executed before executing this instruction, this instruction is equivalent to the NOP instruction. Rev.3.01 2005.02.07 REJ03B0104-0301 page 70 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) RAR (Rotate Accumulator Right) Instruction code D9 0 0 0 0 0 1 1 1 0 D0 1 2 0 1 D Number of words 16 Number of cycles 1 Flag CY 0/1 Skip condition – 1 Operation: → CY → A3A2A1A0 Grouping: Arithmetic operation Description: Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. RB j (Reset Bit) Instruction code D9 0 0 0 1 0 0 1 1 j D0 j 2 0 4 C +j 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (Mj(DP)) ← 0 j = 0 to 3 Grouping: Bit operation Description: Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). RC (Reset Carry flag) Instruction code D9 0 0 0 0 0 0 0 1 1 D0 0 2 0 0 6 Number of words 16 Number of cycles 1 Flag CY 0 Skip condition – 1 Operation: (CY) ← 0 Grouping: Arithmetic operation Description: Clears (0) to carry flag CY. RCP (Reset Port C) Instruction code D9 1 0 1 0 0 0 1 1 0 D0 0 2 2 8 C Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (C) ← 0 Grouping: Input/Output operation Description: Clears (0) to port C. Rev.3.01 2005.02.07 REJ03B0104-0301 page 71 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) RD (Reset port D specified by register Y) Instruction code D9 0 0 0 0 0 1 0 1 0 D0 0 2 0 1 4 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (D(Y)) ← 0 However, (Y) = 0 to 3 Grouping: Input/Output operation Description: Clears (0) to a bit of port D specified by register Y. Note: Set 0 to 3 to register Y because port D is four ports (D0–D3). When values except above are set to register Y, this instruction is equivalent to the NOP instruction. RT (ReTurn from subroutine) Instruction code D9 0 0 0 1 0 0 0 1 0 D0 0 2 0 4 4 Number of words 16 Number of cycles 2 Flag CY – Skip condition – 1 Operation: (PC) ← (SK(SP)) (SP) ← (SP) – 1 Grouping: Return operation Description: Returns from subroutine to the routine called the subroutine. RTI (ReTurn from Interrupt) Instruction code D9 0 0 0 1 0 0 0 1 1 D0 0 2 0 4 6 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (PC) ← (SK(SP)) (SP) ← (SP) – 1 Grouping: Return operation Description: Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt. RTS (ReTurn from subroutine and Skip) Instruction code D9 0 0 0 1 0 0 0 1 0 D0 1 2 0 4 5 Number of words 16 Number of cycles 2 Flag CY – Skip condition Skip at uncondition 1 Operation: (PC) ← (SK(SP)) (SP) ← (SP) – 1 Grouping: Return operation Description: Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition. Rev.3.01 2005.02.07 REJ03B0104-0301 page 72 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SB j (Set Bit) Instruction code D9 0 0 0 1 0 1 1 1 j D0 j 2 0 5 C +j 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (Mj(DP)) ← 0 j = 0 to 3 Grouping: Bit operation Description: Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). SC (Set Carry flag) Instruction code D9 0 0 0 0 0 0 0 1 1 D0 1 2 0 0 7 Number of words 16 Number of cycles 1 Flag CY 1 Skip condition – 1 Operation: (CY) ← 1 Grouping: Arithmetic operation Description: Sets (1) to carry flag CY. SCP (Set Port C) Instruction code D9 1 0 1 0 0 0 1 1 0 D0 1 2 2 8 D Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (C) ← 1 Grouping: Input/Output operation Description: Sets (1) to port C. SD (Set port D specified by register Y) Instruction code D9 0 0 0 0 0 1 0 1 0 D0 1 2 0 1 5 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (D(Y)) ← 1 (Y) = 0 to 3 Grouping: Input/Output operation Description: Sets (1) to a bit of port D specified by register Y. Note: Set 0 to 3 to register Y because port D is four ports (D0–D3). When values except above are set to register Y, this instruction is equivalent to the NOP instruction. Rev.3.01 2005.02.07 REJ03B0104-0301 page 73 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SEA n (Skip Equal, Accumulator with immediate data n) Instruction code D9 0 0 Operation: 0 0 0 0 0 1 1 1 0 1 0 n 1 n 0 n D0 1 n 2 0 0 2 7 5 16 n 16 Number of words 2 Number of cycles 2 Flag CY – Skip condition (A) = n 2 (A) = n ? n = 0 to 15 Grouping: Comparison operation Description: Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Executes the next instruction when the contents of register A is not equal to the value n in the immediate field. SEAM (Skip Equal, Accumulator with Memory) Instruction code D9 0 0 0 0 1 0 0 1 1 D0 0 2 0 2 6 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition (A) = (M(DP)) Operation: (A) = (M(DP)) ? Grouping: Comparison operation Description: Skips the next instruction when the contents of register A is equal to the contents of M(DP). Executes the next instruction when the contents of register A is not equal to the contents of M(DP). SNZ0 (Skip if Non Zero condition of external 0 interrupt request flag) Instruction code D9 0 0 0 0 1 1 1 0 0 D0 0 2 0 3 8 Number of words 16 Number of cycles 1 Flag CY – Skip condition V10 = 0: (EXF0) = 1 1 Operation: V10 = 0: (EXF0) = 1 ? After skipping, (EXF0) ← 0 V10 = 1: SNZ0 = NOP (V10 : bit 0 of the interrupt control register V1) Grouping: Interrupt operation Description: When V10 = 0 : Skips the next instruction when external 0 interrupt request flag EXF0 is “1.” After skipping, clears (0) to the EXF0 flag. When the EXF0 flag is “0,” executes the next instruction. When V10 = 1 : This instruction is equivalent to the NOP instruction. SNZAD (Skip if Non Zero condition of A/D conversion completion flag) Instruction code D9 1 0 1 0 0 0 0 1 1 D0 1 2 2 8 7 Number of words 16 Number of cycles 1 Flag CY – Skip condition V22 = 0: (ADF) = 1 1 Operation: V22 = 0: (ADF) = 1 ? After skipping, (ADF) ← 0 V22 = 1: SNZAD = NOP (V22 : bit 2 of the interrupt control register V2) Grouping: A/D conversion operation Description: When V22 = 0 : Skips the next instruction when A/D conversion completion flag ADF is “1.” After skipping, clears (0) to the ADF flag. When the ADF flag is “0,” executes the next instruction. When V22 = 1 : This instruction is equivalent to the NOP instruction. Rev.3.01 2005.02.07 REJ03B0104-0301 page 74 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SNZCP (Skip if Non Zero condition of Port C) Instruction code D9 1 0 1 0 0 0 1 0 0 D0 1 2 2 8 9 Number of words 16 Number of cycles 1 Flag CY – Skip condition (C) = 1 1 Operation: (C) = 1 ? Grouping: Input/Output operation Description: Skips the next instruction when the contents of port C is “1.” Executes the next instruction when the contents of port C is “0.” SNZI0 (Skip if Non Zero condition of external 0 Interrupt input pin) Instruction code D9 0 0 0 0 1 1 1 0 1 D0 0 2 0 3 A 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition I12 = 0 : (INT) = “L” I12 = 1 : (INT) = “H” Operation: I12 = 0 : (INT) = “L” ? I12 = 1 : (INT) = “H” ? (I12 : bit 2 of the interrupt control register I1) Grouping: Interrupt operation Description: When I1 2 = 0 : S kips the next instruction when the level of INT pin is “L.” Executes the next instruction when the level of INT pin is “H.” When I1 2 = 1 : S kips the next instruction when the level of INT pin is “H.” Executes the next instruction when the level of INT pin is “L.” Number of words 16 SNZP (Skip if Non Zero condition of Power down flag) Instruction code D9 0 0 0 0 0 0 0 0 1 D0 1 2 0 0 3 Number of cycles 1 Flag CY – Skip condition (P) = 1 1 Operation: (P) = 1 ? Grouping: Other operation Description: Skips the next instruction when the P flag is “1”. After skipping, the P flag remains unchanged. Executes the next instruction when the P flag is “0.” SNZT1 (Skip if Non Zero condition of Timer 1 inerrupt request flag) Instruction code D9 1 0 1 0 0 0 0 0 0 D0 0 2 2 8 0 Number of words 16 Number of cycles 1 Flag CY – Skip condition V12 = 0: (T1F) = 1 1 Operation: V12 = 0: (T1F) = 1 ? After skipping, (T1F) ← 0 V12 = 1: SNZT1 = NOP (V12 = bit 2 of interrupt control register V1) Grouping: Timer operation Description: When V12 = 0 : Skips the next instruction when timer 1 interrupt request flag T1F is “1.” After skipping, clears (0) to the T1F flag. When the T1F flag is “0,” executes the next instruction. When V12 = 1 : This instruction is equivalent to the NOP instruction. Rev.3.01 2005.02.07 REJ03B0104-0301 page 75 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SNZT2 (Skip if Non Zero condition of Timer 2 inerrupt request flag) Instruction code D9 1 0 1 0 0 0 0 0 0 D0 1 2 2 8 1 Number of words 16 Number of cycles 1 Flag CY – Skip condition V13 = 0: (T2F) = 1 1 Operation: V13 = 0: (T2F) = 1 ? After skipping, (T2F) ← 0 V13 = 1: SNZT2 = NOP (V13 = bit 3 of interrupt control register V1) Grouping: Timer operation Description: When V13 = 0 : Skips the next instruction when timer 2 interrupt request flag T2F is “1.” After skipping, clears (0) to the T2F flag. When the T2F flag is “0,” executes the next instruction. When V13 = 1 : This instruction is equivalent to the NOP instruction. SZB j (Skip if Zero, Bit) Instruction code D9 0 0 0 0 1 0 0 0 j D0 j 2 0 2 j Number of words 16 Number of cycles 1 Flag CY – Skip condition (Mj(DP)) = 0 j = 0 to 3 1 Operation: (Mj(DP)) = 0 ? j = 0 to 3 Grouping: Bit operation Description: Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0.” Executes the next instruction when the contents of bit j of M(DP) is “1.” SZC (Skip if Zero, Carry flag) Instruction code D9 0 0 0 0 1 0 1 1 1 D0 1 2 0 2 F Number of words 16 Number of cycles 1 Flag CY – Skip condition (CY) = 0 1 Operation: (CY) = 0 ? Grouping: Arithmetic operation Description: Skips the next instruction when the contents of carry flag CY is “0.” After skipping, the CY flag remains unchanged. Executes the next instruction when the contents of the CY flag is “1.“ SZD (Skip if Zero, port D specified by register Y) Instruction code D9 0 0 Operation: 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 1 D0 0 2 0 0 2 2 4 Number of words 16 Number of cycles 2 Flag CY – Skip condition (D(Y)) = 0 (Y) = 0 to 3 2 12 B 16 (D(Y)) = 0 ? (Y) = 0 to 3 Grouping: Input/Output operation Description: Skips the next instruction when a bit of port D specified by register Y is “0.” Executes the next instruction when the bit is “1.” Note: Set 0 to 3 to register Y because port D is four ports (D 0 – D 3 ). When values except above are set to register Y, this instruction is equivalent to the NOP instruction. Rev.3.01 2005.02.07 REJ03B0104-0301 page 76 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B) Instruction code D9 1 0 0 0 1 1 0 0 0 D0 0 2 2 3 0 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (T17–T14) ← (B) (R17–R14) ← (B) (T13–T10) ← (A) (R13–R10) ← (A) Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1. Transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1. T2AB (Transfer data to timer 2 and register R2 from Accumulator and register B) Instruction code D9 1 0 0 0 1 1 0 0 0 D0 1 2 2 3 1 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (T27–T24) ← (B) (R27–R24) ← (B) (T23–T20) ← (A) (R23–R20) ← (A) Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2. Transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2. TAB (Transfer data to Accumulator from register B) Instruction code D9 0 0 0 0 0 1 1 1 1 D0 0 2 0 1 E Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (B) Grouping: Other operation Description: Transfers the contents of register B to register A. TAB1 (Transfer data to Accumulator and register B from timer 1) Instruction code D9 1 0 0 1 1 1 0 0 0 D0 0 2 2 7 0 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (B) ← (T17–T14) (A) ← (T13–T10) Grouping: Timer operation Description: Transfers the high-order 4 bits (T17–T14) of timer 1 to register B. Transfers the low-order 4 bits (T13–T10) of timer 1 to register A. Rev.3.01 2005.02.07 REJ03B0104-0301 page 77 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAB2 (Transfer data to Accumulator and register B from timer 2) Instruction code D9 1 0 0 1 1 1 0 0 0 D0 1 2 2 7 1 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (B) ← (T27–T24) (A) ← (T23–T20) Grouping: Timer operation Description: Transfers the high-order 4 bits (T27–T24) of timer 2 to register B. Transfers the low-order 4 bits (T23–T20) of timer 2 to register A. TABAD (Transfer data to Accumulator and register B from register AD) Instruction code D9 1 0 0 1 1 1 1 0 0 D0 1 2 2 7 9 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: In A/D conversion mode (Q13 = 0), (B) ← (AD9–AD6) (A) ← (AD5–AD2) In comparator mode (Q13 = 1), (B) ← (AD7–AD4) (A) ← (AD3–AD0) (Q13 : bit 3 of A/D control register Q1) Grouping: A/D conversion operation Description: In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD9–AD6) of register AD to register B, and the middle-order 4 bits (AD5–AD2) of register AD to register A. In the comparator mode (Q13 = 1), transfers the highorder 4 bits (AD7–AD4) of comparator register to register B, and the low-order 4 bits (AD3– AD0) of comparator register to register A. D0 Number of words 16 TABE (Transfer data to Accumulator and register B from register E) Instruction code D9 0 0 0 0 1 0 1 0 1 0 2 0 2 A Number of cycles 1 Flag CY – Skip condition – 1 Operation: (B) ← (E7–E4) (A) ← (E3–E0) Grouping: Register to register transfer Description: Transfers the high-order 4 bits (E 7–E4 ) of register E to register B, and low-order 4 bits of register E to register A. TABP p (Transfer data to Accumulator and register B from Program memory in page p) Instruction code D9 0 0 1 0 0 D0 p4 p3 p2 p1 p0 2 0 8 +p p Number of words 16 Number of cycles 3 Flag CY – Skip condition – 1 Operation: (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← (DR2–DR0, A3–A0) (B) ← (ROM(PC))7–4 (A) ← (ROM(PC))3–0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 Grouping: Arithmetic operation Description: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in ad-dress (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. Note: p is 0 to 15 for M34501M2, and p is 0 to 31 for M34501M4/E4. When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used. Rev.3.01 2005.02.07 REJ03B0104-0301 page 78 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAD (Transfer data to Accumulator from register D) Instruction code D9 0 0 0 1 0 1 0 0 0 D0 1 2 0 5 1 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A2–A0) ← (DR2–DR0) (A3) ← 0 Grouping: Register to register transfer Description: Transfers the contents of register D to the low-order 3 bits (A2–A0) of register A. Note: When this instruction is executed, “ 0 ” i s stored to the bit 3 (A3) of register A. TADAB (Transfer data to register AD from Accumulator from register B) Instruction code D9 1 0 0 0 1 1 1 0 0 D0 1 2 2 3 9 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (AD7–AD4) ← (B) (AD3–AD0) ← (A) Grouping: A/D conversion operation Description: In the A/D conversion mode (Q13 = 0), this instruction is equivalent to the NOP instruction. In the comparator mode (Q13 = 1), transfers the contents of register B to the high-order 4 bits (AD7–AD4) of comparator register, and the contents of register A to the low-order 4 bits (AD3–AD0) of comparator register. (Q13 = bit 3 of A/D control register Q1) D0 Number of words 16 TAI1 (Transfer data to Accumulator from register I1) Instruction code D9 1 0 0 1 0 1 0 0 1 1 2 2 5 3 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (I1) Grouping: Interrupt operation Description: Transfers the contents of interrupt control register I1 to register A. TAK0 (Transfer data to Accumulator from register K0) Instruction code D9 1 0 0 1 0 1 0 1 1 D0 0 2 2 5 6 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (K0) Grouping: Input/Output operation Description: Transfers the contents of key-on wakeup control register K0 to register A. Rev.3.01 2005.02.07 REJ03B0104-0301 page 79 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAK1 (Transfer data to Accumulator from register K1) Instruction code D9 1 0 0 1 0 1 1 0 0 D0 1 2 2 5 9 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (K1) Grouping: Input/Output operation Description: Transfers the contents of key-on wakeup control register K1 to register A. TAK2 (Transfer data to Accumulator from register K2) Instruction code D9 1 0 0 1 0 1 1 0 1 D0 0 2 2 5 A Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (K2) Grouping: Input/Output operation Description: Transfers the contents of key-on wakeup control register K2 to register A. TALA (Transfer data to Accumulator from register LA) Instruction code D9 1 0 0 1 0 0 1 0 0 D0 1 2 2 4 9 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A3, A2) ← (AD1, AD0) (A1, A0) ← 0 Grouping: A/D conversion operation Description: Transfers the low-order 2 bits (AD1, AD0) of register AD to the high-order 2 bits (A3, A2) of register A. Note: After this instruction is executed, “ 0 ” i s stored to the low-order 2 bits (A 1 , A 0 ) of register A. TAM j (Transfer data to Accumulator from Memory) Instruction code D9 1 0 1 1 0 0 j j j D0 j 2 2 C j Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 Grouping: RAM to register transfer Description: After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Rev.3.01 2005.02.07 REJ03B0104-0301 page 80 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAMR (Transfer data to Accumulator from register MR) Instruction code D9 1 0 0 1 0 1 0 0 1 D0 0 2 2 5 2 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (MR) Grouping: Other operation Description: Transfers the contents of clock control register MR to register A. TAQ1 (Transfer data to Accumulator from register Q1) Instruction code D9 1 0 0 1 0 0 0 1 0 D0 0 2 2 4 4 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (Q1) Grouping: A/D conversion operation Description: Transfers the contents of A/D control register Q1 to register A. TASP (Transfer data to Accumulator from Stack Pointer) Instruction code D9 0 0 0 1 0 1 0 0 0 D0 0 2 0 5 0 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A2–A0) ← (SP2–SP0) (A3) ← 0 Grouping: Register to register transfer Description: Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2–A0) of register A. Note: After this instruction is executed, “ 0 ” i s stored to the bit 3 (A3) of register A. TAV1 (Transfer data to Accumulator from register V1) Instruction code D9 0 0 0 1 0 1 0 1 0 D0 0 2 0 5 4 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (V1) Grouping: Interrupt operation Description: Transfers the contents of interrupt control register V1 to register A. Rev.3.01 2005.02.07 REJ03B0104-0301 page 81 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAV2 (Transfer data to Accumulator from register V2) Instruction code D9 0 0 0 1 0 1 0 1 0 D0 1 2 0 5 5 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (A) ← (V2) Grouping: Interrupt operation Description: Transfers the contents of interrupt control register V2 to register A. TAW1 (Transfer data to Accumulator from register W1) Instruction code D9 1 0 0 1 0 0 1 0 1 D0 1 2 2 4 B Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (W1) Grouping: Timer operation Description: Transfers the contents of timer control register W1 to register A. TAW2 (Transfer data to Accumulator from register W2) Instruction code D9 1 0 0 1 0 0 1 1 0 D0 0 2 2 4 C Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (W2) Grouping: Timer operation Description: Transfers the contents of timer control register W2 to register A. TAW6 (Transfer data to Accumulator from register W6) Instruction code D9 1 0 0 1 0 1 0 0 0 D0 0 2 2 5 0 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (W6) Grouping: Timer operation Description: Transfers the contents of timer control register W6 to register A. Rev.3.01 2005.02.07 REJ03B0104-0301 page 82 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAX (Transfer data to Accumulator from register X) Instruction code D9 0 0 0 1 0 1 0 0 1 D0 0 2 0 5 2 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (X) Grouping: Register to register transfer Description: Transfers the contents of register X to register A. TAY (Transfer data to Accumulator from register Y) Instruction code D9 0 0 0 0 0 1 1 1 1 D0 1 2 0 1 F Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (Y) Grouping: Register to register transfer Description: Transfers the contents of register Y to register A. TAZ (Transfer data to Accumulator from register Z) Instruction code D9 0 0 0 1 0 1 0 0 1 D0 1 2 0 5 3 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (A1, A0) ← (Z1, Z0) (A3, A2) ← 0 Grouping: Register to register transfer Description: Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. Note: After this instruction is executed, “ 0 ” i s stored to the high-order 2 bits (A3, A2 ) of register A. TBA (Transfer data to register B from Accumulator) Instruction code D9 0 0 0 0 0 0 1 1 1 D0 0 2 0 0 E Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (B) ← (A) Grouping: Register to register transfer Description: Transfers the contents of register A to register B. Rev.3.01 2005.02.07 REJ03B0104-0301 page 83 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TDA (Transfer data to register D from Accumulator) Instruction code D9 0 0 0 0 1 0 1 0 0 D0 1 2 0 2 9 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (DR2–DR0) ← (A2–A0) Grouping: Register to register transfer Description: Transfers the contents of the low-order 3 bits (A2–A0) of register A to register D. TEAB (Transfer data to register E from Accumulator and register B) Instruction code D9 0 0 0 0 0 1 1 0 1 D0 0 2 0 1 A Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (E7–E4) ← (B) (E3–E0) ← (A) Grouping: Register to register transfer Description: Transfers the contents of register B to the high-order 4 bits (E3–E0) of register E, and the contents of register A to the low-order 4 bits (E3–E0) of register E. TI1A (Transfer data to register I1 from Accumulator) Instruction code D9 1 0 0 0 0 1 0 1 1 D0 1 2 2 1 7 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (I1) ← (A) Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control register I1. TK0A (Transfer data to register K0 from Accumulator) Instruction code D9 1 0 0 0 0 1 1 0 1 D0 1 2 2 1 B Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (K0) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to key-on wakeup control register K0. Rev.3.01 2005.02.07 REJ03B0104-0301 page 84 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TK1A (Transfer data to register K1 from Accumulator) Instruction code D9 1 0 0 0 0 1 0 1 0 D0 0 2 2 1 4 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (K1) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to keyon wakeup control register K1. TK2A (Transfer data to register K2 from Accumulator) Instruction code D9 1 0 0 0 0 1 0 1 0 D0 1 2 2 1 5 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (K2) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to keyon wakeup control register K2. TMA j (Transfer data to Memory from Accumulator) Instruction code D9 1 0 1 0 1 1 j j j D0 j 2 2 B j Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 Grouping: RAM to register transfer Description: After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. TMRA (Transfer data to register MR from Accumulator) Instruction code D9 1 0 0 0 0 1 0 1 1 D0 0 2 2 1 6 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (MR) ← (A) Grouping: Other operation Description: Transfers the contents of register A to clock control register MR. Rev.3.01 2005.02.07 REJ03B0104-0301 page 85 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TPU0A (Transfer data to register PU0 from Accumulator) Instruction code D9 1 0 0 0 1 0 1 1 0 D0 1 2 2 2 D Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (PU0) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to pullup control register PU0. TPU1A (Transfer data to register PU1 from Accumulator) Instruction code D9 1 0 0 0 1 0 1 1 1 D0 0 2 2 2 E Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (PU1) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to pullup control register PU1. TPU2A (Transfer data to register PU2 from Accumulator) Instruction code D9 1 0 0 0 1 0 1 1 1 D0 1 2 2 2 F Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (PU2) ← (A) Grouping: Input/Output operation Description: Transfers the contents of register A to pull-up control register PU2. TQ1A (Transfer data to register Q1 from Accumulator) Instruction code D9 1 0 0 0 0 0 0 1 0 D0 0 2 2 0 4 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (Q1) ← (A) Grouping: A/D conversion operation Description: Transfers the contents of register A to A/D control register Q1. Rev.3.01 2005.02.07 REJ03B0104-0301 page 86 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TR1AB (Transfer data to register R1 from Accumulator and register B) Instruction code D9 1 0 0 0 1 1 1 1 1 D0 1 2 2 3 F Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (R17–R14) ← (B) (R13–R10) ← (A) Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits (R17–R14) of reload register R1, and the contents of register A to the low-order 4 bits (R13–R10) of reload register R1. TV1A (Transfer data to register V1 from Accumulator) Instruction code D9 0 0 0 0 1 1 1 1 1 D0 1 2 0 3 F Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (V1) ← (A) Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control register V1. TV2A (Transfer data to register V2 from Accumulator) Instruction code D9 0 0 0 0 1 1 1 1 1 D0 02 0 3 E 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (V2) ← (A) Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control register V2. TW1A (Transfer data to register W1 from Accumulator) Instruction code D9 1 0 0 0 0 0 1 1 1 D0 0 2 2 0 E Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (W1) ← (A) Grouping: Timer operation Description: Transfers the contents of register A to timer control register W1. Rev.3.01 2005.02.07 REJ03B0104-0301 page 87 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TW2A (Transfer data to register W2 from Accumulator) Instruction code D9 1 0 0 0 0 0 1 1 1 D0 1 2 2 0 F 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (W2) ← (A) Grouping: Timer operation Description: Transfers the contents of register A to timer control register W2. TW6A (Transfer data to register W6 from Accumulator) Instruction code D9 1 0 0 0 0 1 0 0 1 D0 12 2 1 3 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (W6) ← (A) Grouping: Timer operation Description: Transfers the contents of register A to timer control register W6. TYA (Transfer data to register Y from Accumulator) Instruction code D9 0 0 0 0 0 0 1 1 0 D0 02 0 0 C 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (Y) ← (A) Grouping: Register to register transfer Description: Transfers the contents of register A to register Y. WRST (Watchdog timer ReSeT) Instruction code D9 1 0 1 0 1 0 0 0 0 D0 0 2 2 A 0 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition (WDF1) = 1 Operation: (WDF1) = 1 ? After skipping, (WDF1) ← 0 Grouping: Other operation Description: Skips the next instruction when watchdog timer flag WDF1 is “1.” After skipping, clears (0) to the WDF1 flag. When the WDF1 flag is “ 0, ” e xecutes the next instruction. Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction. Rev.3.01 2005.02.07 REJ03B0104-0301 page 88 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) XAM j (eXchange Accumulator and Memory data) Instruction code D9 1 0 1 1 0 1 j j j D0 j 2 2 D j Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip) Instruction code D9 1 0 1 1 1 1 j j j D0 j 2 2 F j Number of words 16 Number of cycles 1 Flag CY – Skip condition (Y) = 15 1 Operation: (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) – 1 Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. D0 Number of words 16 XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip) Instruction code D9 1 0 1 1 1 0 j j j j 2 2 E j Number of cycles 1 Flag CY – Skip condition (Y) = 0 1 Operation: (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. when the contents of register Y is not 0, the next instruction is executed. D0 2 16 Instruction code D9 Number of words Number of cycles Flag CY Skip condition Rev.3.01 2005.02.07 REJ03B0104-0301 page 89 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) Number of words Parameter Number of cycles Instruction code Mnemonic Hexadecimal notation Function Type of instructions D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TAB TBA TAY TYA 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 1 1 0 0 01E 00E 01F 00C 01A 02A 029 051 053 052 050 3xy 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) (E7–E4) ← (B) (E3–E0) ← (A) (B) ← (E7–E4) (A) ← (E3–E0) (DR2–DR0) ← (A2–A0) (A2–A0) ← (DR2–DR0) (A3) ← 0 (A1, A0) ← (Z1, Z0) (A3, A2) ← 0 (A) ← (X) (A2–A0) ← (SP2–SP0) (A3) ← 0 (X) ← x x = 0 to 15 (Y) ← y y = 0 to 15 (Z) ← z z = 0 to 3 (Y) ← (Y) + 1 (Y) ← (Y) – 1 Register to register transfer TEAB TABE TDA TAD TAZ TAX TASP LXY x, y x3 x2 x1 x0 y3 y2 y1 y0 RAM addresses LZ z INY DEY 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 0 0 1 z1 z0 1 1 1 1 048 +z 013 017 1 1 1 1 1 1 TAM j 1 0 1 1 0 0 j j j j 2Cj 1 1 (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) – 1 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 RAM to register transfer XAM j 1 0 1 1 0 1 j j j j 2Dj 1 1 XAMD j 1 0 1 1 1 1 j j j j 2Fj 1 1 XAMI j 1 0 1 1 1 0 j j j j 2Ej 1 1 TMA j 1 0 1 0 1 1 j j j j 2Bj 1 1 Rev.3.01 2005.02.07 REJ03B0104-0301 page 90 of 112 4501 Group Skip condition Carry flag CY Datailed description – – – – – – – – – – – Continuous description – (Y) = 0 (Y) = 15 – – – – – – – – – – – – Transfers the contents of register B to register A. Transfers the contents of register A to register B. Transfers the contents of register Y to register A. Transfers the contents of register A to register Y. Transfers the contents of register B to the high-order 4 bits (E3–E0) of register E, and the contents of register A to the low-order 4 bits (E3–E0) of register E. Transfers the high-order 4 bits (E7–E4) of register E to register B, and low-order 4 bits of register E to register A. Transfers the contents of the low-order 3 bits (A2–A0) of register A to register D. Transfers the contents of register D to the low-order 3 bits (A2–A0) of register A. Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. Transfers the contents of register X to register A. Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2–A0) of register A. Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. Loads the value z in the immediate field to register Z. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. when the contents of register Y is not 0, the next instruction is executed. After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. – – – – – – – (Y) = 15 – (Y) = 0 – – – Rev.3.01 2005.02.07 REJ03B0104-0301 page 91 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Number of words Parameter Number of cycles Instruction code Mnemonic Hexadecimal notation Function Type of instructions D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LA n 0 0 0 1 1 1 n n n n 07n 1 1 (A) ← n n = 0 to 15 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (Note) (PCL) ← (DR2–DR0, A3–A0) (B) ← (ROM(PC))7–4 (A) ← (ROM(PC))3–0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (A) ← (A) + (M(DP)) (A) ← (A) + (M(DP)) +(CY) (CY) ← Carry (A) ← (A) + n n = 0 to 15 TABP p 0 0 1 0 0 p4 p3 p2 p1 p0 08p +p 1 3 AM 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 n 0 0 n 1 1 n 0 1 n 00A 00B 06n 1 1 1 1 1 1 Arithmetic operation AMC An AND OR SC RC SZC CMA RAR SB j 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 1 1 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1 1 0 0 j j j 0 1 1 0 1 0 1 j j j 018 019 007 006 02F 01C 01D 05C +j 04C +j 02j 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (A) ← (A) AND (M(DP)) (A) ← (A) OR (M(DP)) (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) → C Y → A 3A 2A 1A 0 (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? Bit operation RB j SZB j SEAM 0 0 0 0 1 0 0 1 1 0 026 1 1 Comparison operation SEA n 0 0 0 0 0 0 0 1 1 1 0 1 0 n 1 n 0 n 1 n 025 07n 2 2 (A) = n ? n = 0 to 15 Note : p is 0 to 15 for M34501M2, p is 0 to 31 for M34501M4/E4. Rev.3.01 2005.02.07 REJ03B0104-0301 page 92 of 112 4501 Group Skip condition Carry flag CY Datailed description Continuous description – – Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used. – – – Overflow = 0 – Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged. 0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. – Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation. Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A. Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A. Sets (1) to carry flag CY. Clears (0) to carry flag CY. Skips the next instruction when the contents of carry flag CY is “0.” Stores the one’s complement for register A’s contents in register A. – – – – (CY) = 0 – – – – (Mj(DP)) = 0 j = 0 to 3 (A) = (M(DP)) – – 1 0 – – 0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. – – – Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0.” Executes the next instruction when the contents of bit j of M(DP) is “1.” Skips the next instruction when the contents of register A is equal to the contents of M(DP). Executes the next instruction when the contents of register A is not equal to the contents of M(DP). Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Executes the next instruction when the contents of register A is not equal to the value n in the immediate field. – (A) = n – Rev.3.01 2005.02.07 REJ03B0104-0301 page 93 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Number of words Parameter Number of cycles Instruction code Mnemonic Hexadecimal notation Function Type of instructions D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ba BL p, a 0 0 1 BLA p 0 1 BM a 0 1 0 0 0 0 1 1 1 0 0 0 0 a6 a5 a4 a3 a2 a1 a0 1 1 p4 p3 p2 p1 p0 18a +a 0Ep +p 2aa 010 2pp 1aa 1 2 1 2 (PCL) ← a6–a0 (PCH) ← p (Note) (PCL) ← a6–a0 Branch operation a6 a5 a4 a3 a2 a1 a0 0 0 1 0 0 0 0 0 2 2 (PCH) ← p (Note) (PCL) ← (DR2–DR0, A3–A0) p4 0 p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0 1 1 Subroutine operation (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← 2 (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (Note) (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (Note) (PCL) ← (DR2–DR0,A3–A0) (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 BML p, a 0 1 0 0 0 0 1 0 0 0 1 0 p4 p3 p2 p1 p0 0Cp +p 2aa 030 2pp 2 2 a6 a5 a4 a3 a2 a1 a0 0 1 1 0 0 0 0 0 BMLA p 0 1 2 2 p4 0 p3 p2 p1 p0 RTI 0 0 0 1 0 0 0 1 1 0 046 1 1 Return operation RT 0 0 0 1 0 0 0 1 0 0 044 1 2 RTS 0 0 0 1 0 0 0 1 0 1 045 1 2 Note : p is 0 to 15 for M34501M2, p is 0 to 31 for M34501M4/E4. Rev.3.01 2005.02.07 REJ03B0104-0301 page 94 of 112 4501 Group Skip condition Carry flag CY Datailed description – – – – Branch within a page : Branches to address a in the identical page. Branch out of a page : Branches to address a in page p. – – Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. – – Call the subroutine in page 2 : Calls the subroutine at address a in page 2. – – Call the subroutine : Calls the subroutine at address a in page p. – – Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. – – Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt. Returns from subroutine to the routine called the subroutine. – – Skip at uncondition – Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition. Rev.3.01 2005.02.07 REJ03B0104-0301 page 95 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Number of words Parameter Number of cycles Instruction code Mnemonic Hexadecimal notation Function Type of instructions D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DI EI SNZ0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 1 0 0 0 0 0 1 0 004 005 038 1 1 1 1 1 1 (INTE) ← 0 (INTE) ← 1 V10 = 0: (EXF0) = 1 ? After skipping, (EXF0) ← 0 V10 = 1: SNZ0 = NOP I12 = 0 : (INT) = “L” ? I12 = 1 : (INT) = “H” ? Interrupt operation SNZI0 0 0 0 0 1 1 1 0 1 0 03A 1 1 TAV1 TV1A TAV2 TV2A TAI1 TI1A TAW1 TW1A TAW2 TW2A TAW6 TW6A TAB1 T1AB 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0 1 1 1 0 0 0 0 0 1 0 1 1 1 1 1 0 1 0 1 0 0 0 1 1 0 1 1 1 0 0 1 0 1 0 0 054 03F 055 03E 253 217 24B 20E 24C 20F 250 213 270 230 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (A) ← (V1) (V1) ← (A) (A) ← (V2) (V2) ← (A) (A) ← (I1) (I1) ← (A) (A) ← (W1) (W1) ← (A) (A) ← (W2) (W2) ← (A) (A) ← (W6) (W6) ← (A) (B) ← (T17–T14) (A) ← (T13–T10) (T17–T14) ← (B) (R17–R14) ← (B) (T13–T10) ← (A) (R13–R10) ← (A) (B) ← (T27–T24) (A) ← (T23–T20) (T27–T24) ← (B) (R27–R24) ← (B) (T23–T20) ← (A) (R23–R20) ← (A) (R17–R14) ← (B) (R13–R10) ← (A) V12 = 0: (T1F) = 1 ? After skipping, (T1F) ← 0 V12 = 1: SNZT1 = NOP V13 = 0: (T2F) = 1 ? After skipping, (T2F) ← 0 V13 = 1: SNZT2 = NOP Timer operation TAB2 T2AB 1 1 0 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 1 1 271 231 1 1 1 1 TR1AB SNZT1 1 1 0 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 23F 280 1 1 1 1 SNZT2 1 0 1 0 0 0 0 0 0 1 281 1 1 Rev.3.01 2005.02.07 REJ03B0104-0301 page 96 of 112 4501 Group Skip condition Carry flag CY Datailed description – – V10 = 0: (EXF0) = 1 – – – Clears (0) to interrupt enable flag INTE, and disables the interrupt. Sets (1) to interrupt enable flag INTE, and enables the interrupt. When V10 = 0 : Skips the next instruction when external 0 interrupt request flag EXF0 is “1.” After skipping, clears (0) to the EXF0 flag. When the EXF0 flag is “0,” executes the next instruction. When V10 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register V1) When I12 = 0 : Skips the next instruction when the level of INT pin is “L.” Executes the next instruction when the level of INT pin is “H.” When I12 = 1 : Skips the next instruction when the level of INT pin is “H.” Executes the next instruction when the level of INT pin is “L.” (I12: bit 2 of interrupt control register I1) (INT) = “L” However, I12 = 0 (INT) = “H” However, I12 = 1 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Transfers the contents of interrupt control register V1 to register A. Transfers the contents of register A to interrupt control register V1. Transfers the contents of interrupt control register V2 to register A. Transfers the contents of register A to interrupt control register V2. Transfers the contents of interrupt control register I1 to register A. Transfers the contents of register A to interrupt control register I1. Transfers the contents of timer control register W1 to register A. Transfers the contents of register A to timer control register W1. Transfers the contents of timer control register W2 to register A. Transfers the contents of register A to timer control register W2. Transfers the contents of timer control register W6 to register A. Transfers the contents of register A to timer control register W6. Transfers the high-order 4 bits (T17–T14) of timer 1 to register B. Transfers the low-order 4 bits (T13–T10) of timer 1 to register A. Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1. Transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1. – – – – Transfers the high-order 4 bits (T27–T24) of timer 2 to register B. Transfers the low-order 4 bits (T23–T20) of timer 2 to register A. Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2. Transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2. – V12 = 0: (T1F) = 1 – – Transfers the contents of register B to the high-order 4 bits (R17–R14) of reload register R1, and the contents of register A to the low-order 4 bits (R13–R10) of reload register R1. When V12 = 0 : Skips the next instruction when timer 1 interrupt request flag T1F is “1.” After skipping, clears (0) to the T1F flag. When the T1F flag is “0,” executes the next instruction. When V12 = 1 : This instruction is equivalent to the NOP instruction. (V12: bit 2 of interrupt control register V1) When V13 = 0 : Skips the next instruction when timer 1 interrupt request flag T2F is “1.” After skipping, clears (0) to the T2F flag. When the T2F flag is “0,” executes the next instruction. When V13 = 1 : This instruction is equivalent to the NOP instruction. (V13: bit 3 of interrupt control register V1) V13 = 0: (T2F) =1 – Rev.3.01 2005.02.07 REJ03B0104-0301 page 97 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Number of words Parameter Number of cycles Instruction code Mnemonic Hexadecimal notation Function Type of instructions D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IAP0 OP0A IAP1 OP1A IAP2 OP2A CLD RD 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 1 0 260 220 261 221 262 222 011 014 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (A) ← (P0) (P0) ← (A) (A) ← (P1) (P1) ← (A) (A1, A0) ← (P21, P20) (A3, A2) ← 0 (P21, P20) ← (A1, A0) (D) ← 1 (D(Y)) ← 0 (Y) = 0 to 3 (D(Y)) ← 1 (Y) = 0 to 3 (D(Y)) = 0 ? (Y) = 0 to 3 SD 0 0 0 0 0 1 0 1 0 1 015 1 1 SZD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 1 0 1 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 0 1 1 0 1 1 1 1 0 0 1 1 0 1 0 1 024 02B 28D 28C 289 26F 21F 21B 256 214 259 215 25A 22D 22E 22F 2 2 Input/Output operation SCP RCP SNZCP IAK OKA TK0A TAK0 TK1A TAK1 TK2A TAK2 TPU0A TPU1A TPU2A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (C) ← 1 (C) ← 0 (C) = 1? (A0) ← (K) (A3–A1) ← 0 (K) ← (A0) (K0) ← (A) (A) ← (K0) (K1) ← (A) (A) ← (K1) (K2) ← (A) (A) ← (K2) (PU0) ← (A) (PU1) ← (A) (PU2) ← (A) Rev.3.01 2005.02.07 REJ03B0104-0301 page 98 of 112 4501 Group Skip condition Carry flag CY Datailed description – – – – – – – – – – – – – – – – Transfers the input of port P0 to register A. Outputs the contents of register A to port P0. Transfers the input of port P1 to register A. Outputs the contents of register A to port P1. Transfers the input of port P2 to the low-order 2 bits (A1, A0) of register A. Outputs the contents of the low-order 2 bits (A1, A0) of register A to port P2. Sets (1) to port D. Clears (0) to a bit of port D specified by register Y. – – Sets (1) to a bit of port D specified by register Y. (D(Y)) = 0 ? (Y) = 0 to 3 – Skips the next instruction when a bit of port D specified by register Y is “0.” Executes the next instruction when a bit of port D specified by register Y is “1.” – – (C) = 1 – – – – – – – – – – – – – – – – – – – – – – – – – Sets (1) to port C. Clears (0) to port C. Skips the next instruction when the contents of port C is “1.” Executes the next instruction when the contents of port C is “0.” Transfers the contents of port K to the bit 0 (A0) of register A. Outputs the contents of bit 0 (A0) of register A to port K. Transfers the contents of register A to key-on wakeup control register K0. Transfers the contents of key-on wakeup control register K0 to register A. Transfers the contents of register A to key-on wakeup control register K1. Transfers the contents of key-on wakeup control register K1 to register A. Transfers the contents of register A to key-on wakeup control register K2. Transfers the contents of key-on wakeup control register K2 to register A. Transfers the contents of register A to pull-up control register PU0. Transfers the contents of register A to pull-up control register PU1. Transfers the contents of register A to pull-up control register PU2. Rev.3.01 2005.02.07 REJ03B0104-0301 page 99 of 112 4501 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Number of words Parameter Number of cycles Instruction code Mnemonic Hexadecimal notation Function Type of instructions D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TABAD 1 0 0 1 1 1 1 0 0 1 279 1 1 In A/D conversion mode (Q13 = 0), (B) ← (AD9–AD6) (A) ← (AD5–AD2) In comparator mode (Q13 = 1), (B) ← (AD7–AD4) (A) ← (AD3–AD0) (A3, A2) ← (AD1, AD0) (A1, A0) ← 0 (AD7–AD4) ← (B) (AD3–AD0) ← (A) A/D conversion operation TALA TADAB 1 1 0 0 0 0 1 0 0 1 0 1 1 1 0 0 0 0 1 1 249 239 1 1 1 1 TAQ1 TQ1A ADST 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0 0 1 0 0 1 244 204 29F 1 1 1 1 1 1 (A) ← (Q1) (Q1) ← (A) (ADF) ← 0 Q13 = 0: A/D conversion starting Q13 = 1: Comparator operation starting V22 = 0: (ADF) = 1 ? After skipping, (ADF) ← 0 V22 = 1: SNZAD = NOP (PC) ← (PC) + 1 RAM back-up However, voltage drop detection circuit is valid RAM back-up POF or POF2 instruction valid (P) = 1 ? SNZAD 1 0 1 0 0 0 0 1 1 1 287 1 1 NOP POF POF2 EPOF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 1 000 002 008 05B 003 1 1 1 1 1 1 1 1 1 1 Other operation SNZP DWDT WRST 1 1 0 0 1 1 0 0 0 1 1 0 1 0 1 0 0 0 0 0 29C 2A0 1 1 1 1 Stop of watchdog timer function enabled (WDF1) = 1, after skipping, (WDF1) ← 0 Ceramic resonator selected RC oscillation selected (A) ← (MR) (MR) ← (A) CMCK CRCK TAMR TMRA 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 1 0 0 29A 29B 252 216 1 1 1 1 1 1 1 1 Rev.3.01 2005.02.07 REJ03B0104-0301 page 100 of 112 4501 Group Skip condition Carry flag CY Datailed description – – In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD9–AD6) of register AD to register B, and the middle-order 4 bits (AD5–AD2) of register AD to register A. In the comparator mode (Q13 = 1), transfers the high-order 4 bits (AD7–AD4) of comparator register to register B, and the low-order 4 bits (AD3–AD0) of comparator register to register A. (Q13: bit 3 of A/D control register Q1) Transfers the low-order 2 bits (AD1, AD0) of register AD to the high-order 2 bits (AD3, AD2) of register A. In the A/D conversion mode (Q13 = 0), this instruction is equivalent to the NOP instruction. In the comparator mode (Q13 = 1), transfers the contents of register B to the high-order 4 bits (AD7–AD4) of comparator register, and the contents of register A to the low-order 4 bits (AD3–AD0) of comparator register. (Q13 = bit 3 of A/D control register Q1) Transfers the contents of A/D control register Q1 to register A. Transfers the contents of register A to A/D control register Q1. Clears (0) to A/D conversion completion flag ADF, and the A/D conversion at the A/D conversion mode (Q13 = 0) or the comparator operation at the comparator mode (Q13 = 1) is started. (Q13 = bit 3 of A/D control register Q1) When V22 = 0 : Skips the next instruction when A/D conversion completion flag ADF is “1.” After skipping, clears (0) to the ADF flag. When the ADF flag is “0,” executes the next instruction. When V22 = 1 : This instruction is equivalent to the NOP instruction. (V22: bit 2 of interrupt control register V2) No operation; Adds 1 to program counter value, and others remain unchanged. Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF instruction. However, the voltage drop detection circuit is valid. Puts the system in RAM back-up state by executing the POF2 instruction after executing the EPOF instruction. Operations of all functions are stopped. Makes the immediate after POF or POF2 instruction valid by executing the EPOF instruction. Skips the next instruction when the P flag is “1”. After skipping, the P flag remains unchanged. Executes the next instruction when the P flag is “0.” Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction. Skips the next instruction when watchdog timer flag WDF1 is “1.” After skipping, clears (0) to the WDF1 flag. When the WDF1 flag is “0,” executes the next instruction. Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction. Selects the ceramic resonance circuit and stops the on-chip oscillator. Selects the RC oscillation circuit and stops the on-chip oscillator. Transfers the contents of clock control register MR to register A. Transfers the contents of register A to clock control register MR. – – – – – – – – – – V22 = 0: (ADF) = 1 – – – – – (P) = 1 – – – – – – (WDF1) = 1 – – – – – – – – – – Rev.3.01 2005.02.07 REJ03B0104-0301 page 101 of 112 4501 Group INSTRUCTION CODE TABLE D9–D4 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 D3–D0 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F Hex. 010000 011000 010111 011111 00 NOP – POF 01 BLA CLD – 02 03 04 – – – – RT 05 TASP TAD TAX TAZ TAV1 06 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 10 A 11 A 12 A 13 A 14 A 15 07 LA 0 LA 1 LA 2 LA 3 LA 4 LA 5 LA 6 LA 7 LA 8 LA 9 LA 10 LA 11 LA 12 LA 13 LA 14 LA 15 08 09 0A – – – – – – – – – – – – – – – – 0B – – – – – – – – – – – – – – – – 0C 0D 0E BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL 0F BL* BL* BL* BL* BL* BL* BL* BL* BL* BL* BL* BL* BL* BL* BL* BL* 10–17 18–1F BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM B B B B B B B B B B B B B B B B SZB BMLA 0 SZB 1 SZB 2 SZB 3 SZD SEAn SEAM – – TDA – – – – – – – SNZ0 – TABP TABP 0 16* TABP TABP 1 17* TABP TABP 2 18* TABP TABP 3 19* TABP TABP 4 20* TABP TABP 5 21* TABP TABP 6 22* TABP TABP 7 23* TABP TABP 8 24* TABP TABP 9 25* TABP TABP 10 26* TABP TABP 11 27* TABP TABP 12 28* TABP TABP 13 29* TABP TABP 14 30* TABP TABP 15 31* BML BML* BML BML* BML BML* BML BML* BML BML* BML BML* BML BML* BML BML* BML BML* BML BML* BML BML* BML BML* BML BML* BML BML* BML BML* BML BML* SNZP INY DI EI RC SC RD SD – DEY RTS TAV2 RTI – LZ 0 LZ 1 LZ 2 LZ 3 RB 0 RB 1 RB 2 RB 3 – – – – – EPOF SB 0 SB 1 SB 2 SB 3 POF2 AND – AM AMC TYA – TBA – OR TEAB TABE SNZI0 – CMA RAR TAB TAY – – – – – – – TV2A SZC TV1A The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-order 4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below. The second word 10 0aaa aaaa 10 0aaa aaaa 10 0p00 pppp 10 0p00 pppp 00 0111 nnnn 00 0010 1011 • * cannot be used in the M34501M2-XXXFP. BL BML BLA BMLA SEA SZD Rev.3.01 2005.02.07 REJ03B0104-0301 page 102 of 112 4501 Group INSTRUCTION CODE TABLE (continued) D9–D4 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 D3–D0 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F Hex. 110000 111111 20 – – – – 21 – – – TW6A 22 23 24 – – – – TAQ1 – – – – 25 26 27 28 29 – – – – – – – – – – CMCK CRCK 2A WRST – – – – – – – – – – – – – – – 2B TMA 0 TMA 1 TMA 2 TMA 3 TMA 4 TMA 5 TMA 6 TMA 7 TMA 8 TMA 9 TMA 10 TMA 11 TMA 12 TMA 13 TMA 14 TMA 15 2C 2D 2E 2F 30–3F OP0A T1AB OP1A T2AB OP2A – – – – – – – – – – TPU0A TPU1A – – – – – – – TAW6 IAP0 TAB1 SNZT1 – IAP1 TAB2 SNZT2 – – – – – – – – – – – – SNZAD – TAM XAM XAMI XAMD LXY 0 0 0 0 TAM XAM XAMI XAMD LXY 1 1 1 1 TAM XAM XAMI XAMD LXY 2 2 2 2 TAM XAM XAMI XAMD LXY 3 3 3 3 TAM XAM XAMI XAMD LXY 4 4 4 4 TAM XAM XAMI XAMD LXY 5 5 5 5 TAM XAM XAMI XAMD LXY 6 6 6 6 TAM XAM XAMI XAMD LXY 7 7 7 7 TAM XAM XAMI XAMD LXY 8 8 8 8 TAM XAM XAMI XAMD LXY 9 9 9 9 TAM XAM XAMI XAMD LXY 10 10 10 10 TAM XAM XAMI XAMD LXY 11 11 11 11 TAM XAM XAMI XAMD LXY 12 12 12 12 TAM XAM XAMI XAMD LXY 13 13 13 13 TAM XAM XAMI XAMD LXY 14 14 14 14 TAM XAM XAMI XAMD LXY 15 15 15 15 TAMR IAP2 TAI1 – – TAK0 – – – – – – – – – – – – – – IAK TQ1A TK1A – – – – – – – – – TW1A TK2A TMRA TI1A – – – TK0A – – – TADAB TALA TAK1 – – – – – – TAW1 TAW2 – – – TAK2 – – – – – TABAD SNZCP – – – – – – – – RCP DWDT SCP – – – – ADST TW2A OKA TPU2ATR1AB The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the loworder 4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below. The second word 10 0aaa aaaa 10 0aaa aaaa 10 0p00 pppp 10 0p00 pppp 00 0111 nnnn 00 0010 1011 BL BML BLA BMLA SEA SZD Rev.3.01 2005.02.07 REJ03B0104-0301 page 103 of 112 4501 Group Electrical characteristics Absolute maximum ratings Symbol VDD VI VI VI VO VO VO Pd Topr Tstg Parameter Supply voltage Input voltage P0, P1, P2, D2/C, D3/K, RESET, XIN Input voltage D0, D1 Input voltage AIN0–AIN1 Output voltage P0, P1, P2, D2/C, D3/K, RESET Output voltage D0, D1 Output voltage XOUT Power dissipation Operating temperature range Storage temperature range Ta = 25 °C Output transistors in cut-off state Conditions Ratings –0.3 to 6.5 –0.3 to VDD+0.3 –0.3 to 13.0 –0.3 to VDD+0.3 –0.3 to VDD+0.3 –0.3 to 13.0 –0.3 to VDD+0.3 300 –20 to 85 –40 to 125 Unit V V V V V V V mW °C °C Rev.3.01 2005.02.07 REJ03B0104-0301 page 104 of 112 4501 Group R ecommended operating conditions 1 (Ta Symbol VDD Parameter Supply voltage = – 20 ° C to 85 ° C, VDD = 2 .7 to 5.5 V, unless otherwise noted) Conditions Limits Min. 2.7 (Note 1) Typ. Max. 5.5 Unit V High-speed mode Middle-speed mode Low-speed mode Default mode f(XIN) ≤ 4.4 MHz VRAM VSS VIH VIH VIH VIH VIH VIL VIL VIL VIL IOL(peak) IOL(peak) IOL(peak) IOL(peak) IOL(avg) IOL(avg) IOL(avg) IOL(avg) ΣIOL(avg) RAM back-up voltage Supply voltage “H” level input voltage “H” level input voltage “H” level input voltage “H” level input voltage “H” level input voltage “L” level input voltage “L” level input voltage “L” level input voltage “L” level input voltage “L” level peak output current “L” level peak output current “L” level peak output current “L” level peak output current “L” level average output current “L” level average output current “L” level average output current “L” level average output current “L” level total average current (at RAM back-up mode with the POF2 instruction) 1.8 (Note 2) 0 V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA P0, P1, P2, D2, D3, XIN D 0 , D1 RESET 0.8VDD 0.8VDD 0.85VDD VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V 0.5VDD 0.7VDD 0.85VDD 0 0 0 0 VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD 12 VDD VDD VDD VDD 0.2VDD 0.16VDD 0.3VDD 0.15VDD 10 40 24 24 5.0 30 15 12 80 80 C, K CNTR, INT P0, P1, P2, D0–D3, XIN C, K RESET CNTR, INT P2, RESET D 0 , D1 D2/C, D3/K P0, P1 P2, RESET (Note 3) D0, D1 (Note 3) D2/C, D3/K (Note 3) P0, P1 (Note 3) P2, D, RESET P0, P1 Notes 1: System is in the reset state when the value is the detection voltage of the voltage drop detection circuit or less. 2: The voltage drop detection circuit is operating in the RAM back-up with the POF instruction (system enters into the reset state when the value is VRST or less). In the RAM back-up mode with the POF2 instruction, the voltage drop detection circuit stops. 3: The average output current (IOH, IOL) is the average value during 100 ms. Ceramic resonator and high-speed mode selected f [MHz] VRST (Note) External clock input (ceramic resonator selected) VRST (Note) f [MHz] 4.4 3.2 Recommended operating condition Recommended operating condition 2.7 4.2 5.5 VDD[V] 2.7 4.2 5.5 VDD[V] Note: It shows the electrical characteristics range of detected voltage for voltage drop detection circuit. System reset occurs when the supply voltage is under the detected voltage for voltage drop detection circuit. Rev.3.01 2005.02.07 REJ03B0104-0301 page 105 of 112 4501 Group Recommended operating conditions 2 (Ta = –20 °C to 85 °C, VDD = 2.7 to 5.5 V, unless otherwise noted) Symbol f(XIN) Parameter Oscillation frequency (with a ceramic resonator/ RC oscillation) (Note) f(XIN) Oscillation frequency (with a ceramic resonator selected, external clock input) ∆ f(XIN) Oscillation frequency error (at RC oscillation, error value of exteranal R, C not included) Note: use 30 pF capacitor and vary external R f(CNTR) Timer external input frequency High-speed mode Middle-speed mode Low-speed mode Default mode tw(CNTR) Timer external input period (“H” and “L” pulse width) High-speed mode Middle-speed mode Low-speed mode Default mode TPON Valid supply voltage rising time for power-on reset circuit Note: The frequency at RC oscillation is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits. Conditions High-speed mode Middle-speed mode Low-speed mode Default mode High-speed mode Middle-speed mode Low-speed mode Default mode VDD = 5.0 V ±10 %, Ta = 25 °C, –20 to 85 °C Min. Limits Typ. Max. 4.4 Unit MHz 3.2 MHz ±17 % f(XIN)/6 f(XIN)/12 f(XIN)/24 f(XIN)/48 3/f(XIN) 6/f(XIN) 12/f(XIN) 24/f(XIN) 100 Hz s VDD = 0 → 2.0 V µs Rev.3.01 2005.02.07 REJ03B0104-0301 page 106 of 112 4501 Group Electrical characteristics Symbol VOL VOL VOL VOL IIH IIH IIL IIL IDD ( Ta = – 20 ° C to 85 ° C, V DD = 2 .7 to 5.5 V, unless otherwise noted) Test conditions VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VI = VDD VI = 12 V VI = 0 V P0, P1, P2 No pull-up VI = 0 V, D2/C, D3/K, No pull-up VDD = 5.0 V f(XIN) = 4.0 MHz High-speed mode Middle-speed mode Low-speed mode Default mode –1.0 –1.0 1.7 1.3 1.1 1.0 50 0.1 5.0 3.9 3.3 3.0 100 1.0 10 6.0 30 60 0.25 1.2 1.0 2.0 3.0 150 kΩ V V MHz IOL = 12 mA IOL = 4.0 mA IOL = 5.0 mA IOL = 1.0 mA IOL = 30 mA IOL = 10 mA IOL = 15 mA IOL = 5.0 mA Limits Min. Typ. Max. 2.0 0.9 2.0 0.6 2.0 0.9 2.0 0.9 1.0 1.0 V V Unit V V Parameter “L” level output voltage P0, P1 “L” level output voltage P2, RESET “L” level output voltage D0, D1 “L” level output voltage D2/C, D3/K “H” level input current P0, P1, P2, D2/C, D3/K, RESET “H” level input current D0, D1 “L” level input current P0, P1, P2 “L” level input current D0, D1, D2/C, D3/K Supply current at active mode (Notes 1, 2) µA µA µA µA mA at RAM back-up mode (POF instruction execution) at RAM back-up mode VDD = 5.0 V µA µA Ta = 25 °C (POF2 instruction execution) VDD = 5.0 V VDD = 3.0 V RPU Pull-up resistor value P0, P1, P2, D2/C, D3/K, RESET VT+ – VT– Hysteresis INT, CNTR VT+ – VT– Hysteresis RESET f(RING) On-chip oscillator clock frequency (Note 3) VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VI = 0 V, VDD = 5.0 V Notes 1: The operation current of the voltage drop detection circuit is included. 2: When the A/D converter is used, the A/D operation current (IADD) is included. 3: When system operates by the on-chip oscillator, the system clock frequency is the on-chip oscillator clock divided by the dividing ratio selected with register MR. Rev.3.01 2005.02.07 REJ03B0104-0301 page 107 of 112 4501 Group A/D converter recommended operating conditions (Comparator mode included, Ta = –20 °C to 85 °C, unless otherwise noted) Symbol VDD VIA f(XIN) Parameter Supply voltage Analog input voltage Oscillation frequency VDD = 2.7 to 5.5 V High-speed mode Middle-speed mode Low-speed mode Default mode Ta = 25 °C Ta = –20 °C to 85 °C Conditions Min. 2.7 (Note) 3.0 0 0.1 0.2 0.4 0.8 Limits Typ. Max. 5.5 5.5 VDD+2LSB Unit V V V MHz MHz MHz MHz Note: System is in the reset state when the value is the detection voltage of the voltage drop detection circuit or less. A/D converter characteristics (Comparator mode included, Ta = –20 °C to 85 °C, unless otherwise noted) Symbol – – – V0T VFST IADD TCONV Parameter Resolution Linearity error Differential non-linearity error Zero transition voltage Full-scale transition voltage A/D operating current (Note 1) A/D conversion time Ta = 25 °C, VDD = 2.7 to 5.5 V Ta = –25 °C to 85 °C, VDD = 3.0 V to 5.5 V Ta = 25 °C, VDD = 2.7 to 5.5 V Ta = –25 °C to 85 °C, VDD = 3.0 V to 5.5 V VDD = 5.12 V VDD = 5.12 V VDD = 5.0 V f(XIN) = 4.0 MHz f(XIN) = 0.4 MHz to 4.0 MHz High-speed mode Middle-speed mode Low-speed mode Default mode – – – Comparator resolution Comparator error (Note 2) Comparator comparison time Comparator mode VDD = 5.12 V f(XIN) = 4.0 MHz High-speed mode Middle-speed mode Low-speed mode Default mode 10 5115 20 5125 0.3 ±0.9 30 5135 0.9 46.5 93.0 186 372 8 ±20 6.0 12 24 48 bits mV µs LSB mV mV mA µs Test conditions Min. Limits Typ. Max. 10 ±2.0 Unit bits LSB Notes 1: When the A/D converter is used, the IADD is included to IDD. 2: As for the error from the logic value in the comparator mode, when the contents of the comparator register is n, the logic value of the comparison voltage Vref which is generated by the built-in DA converter can be obtained by the following formula. Logic value of comparison voltage Vref Vref = VDD 256 ✕n n = Value of register AD (n = 0 to 255) Rev.3.01 2005.02.07 REJ03B0104-0301 page 108 of 112 4501 Group Voltage drop detection circuit characteristics (Ta = –20 °C to 85 °C, unless otherwise noted) Symbol VRST IRST Parameter Detection voltage (Note 1) Operation current of voltage drop detection circuit Test conditions Min. 2.7 3.3 VDD = 5.0 V Limits Typ. 3.5 50 Max. 4.2 3.7 100 Unit V Ta = 25 °C RAM back-up mode (POF instruction execution) (Note 2) µA Notes 1: The detected voltage (VRST) is defined as the voltage when reset occurs while the supply voltage (VDD) is falling. 2: The voltage drop detection circuit is operating in the RAM back-up with the POF instruction (It stops in the RAM back-up with the POF2 instruction). Basic timing diagram Machine cycle Parameter Clock Pin name Mi Mi+1 XIN : high-speed mode (System clock = f(XIN)) XIN : middle-speed mode (System clock = f(XIN)/2) XIN : low-speed mode (System clock = f(XIN)/4) XIN : default mode (System clock = f(XIN)/8) Port D output D0, D1, D2/C, D3/K Port D input D0, D1, D2/C, D3/K Port P0, P1, P2 output P00–P03 P10–P13 P20, P21 P00–P03 P10–P13 P20, P21 Port P0, P1, P2 input Timer output Timer input CNTR CNTR Interrupt input INT Rev.3.01 2005.02.07 REJ03B0104-0301 page 109 of 112 4501 Group BUILT-IN PROM VERSION In addition to the mask ROM versions, the 4501 Group has the One Time PROM versions whose PROMs can only be written to and not be erased. The built-in PROM version has functions similar to those of the mask ROM versions, but it has PROM mode that enables writing to built-in PROM. Table 20 shows the product of built-in PROM version. Figure 56 shows the pin configurations of built-in PROM versions. The One Time PROM version has pin-compatibility with the mask ROM version. Table 20 Product of built-in PROM version PROM size Part number (✕ 10 bits) M34501E4FP 4096 words RAM size (✕ 4 bits) 256 words Package PRSP0020DA-A ROM type One Time PROM [shipped in blank] (1) PROM mode The 4501 Group has a PROM mode in addition to a normal operation mode. It has a function to serially input/output the command codes, addresses, and data required for operation (e.g., read and program) on the built-in PROM using only a few pins. This mode can be selected by setting pins SDA (serial data input/output), S CLK ( serial clock input), PGM to “ H ” a fter connecting wires as shown in Figure 56 and powering on the VDD pin, and then applying 12 V to the VPP pin. In the PROM mode, three types of software commands (read, program, and program verify) can be used. Clock-synchronous serial I/O is used, beginning from the LSB (LSB first). Use the special-perpose serial programmer when performing serial read/program. As for the serial programmer for the single-chip microcomputer (serial programmer and control software), refer to the “ Renesas Microcomputer Development Support Tools ” H ompage (http:// www.renesas.com/en/tools). Writing with PROM programmer Screening (Leave at 150 °C for 40 hours) (Note) Verify test with PROM programmer Function test in target device Note: Since the screening temperature is higher than storage temperature, never expose the microcomputer to 150 °C exceeding 100 hours. (2) Notes on handling ➀ A high-voltage is used for writing. Take care that overvoltage is not applied. Take care especially at turning on the power. ➁ For the One Time PROM version shipped in blank, Renesas corp. does not perform PROM writing test and screening in the assembly process and following processes. In order to improve reliability after writing, performing writing and test according to the flow shown in Figure 55 before using is recommended (Products shipped in blank: PROM contents is not written in factory when shipped). Fig. 55 Flow of writing and test of the product shipped in blank Rev.3.01 2005.02.07 REJ03B0104-0301 page 110 of 112 4501 Group PIN CONFIGURATION (TOP VIEW) VDD VSS VDD VSS XIN XOUT VPP CNVSS RESET SCLK SDA PGM 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 P00 P01 P02 P03 P10 P11 P12/CNTR P13/INT D0 D1 M34501E4FP P21/AIN1 VDD P20/AIN0 D3/K D2/C Outline PRSP0020DA-A (20P2N-A) Fig. 56 Pin configuration of built-in PROM version Rev.3.01 2005.02.07 REJ03B0104-0301 page 111 of 112 4501 Group Package outline JEITA Package Code P-SOP20-5.3x12.6-1.27 RENESAS Code PRSP0020DA-A Previous Code 20P2N-A MASS[Typ.] 0.3g 20 11 HE *1 E F 1 Index mark *2 D 10 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. c A2 A1 Reference Symbol Dimension in Millimeters Min 12.5 5.2 Nom 12.6 5.3 1.8 0 0.1 0.2 2.1 0.35 0.18 0° 0.4 0.2 0.5 0.25 8° 7.8 1.27 8.1 1.42 0.1 0.4 0.6 0.8 Max 12.7 5.4 A D L E A2 *3 e bp y Detail F A1 A bp c HE e y L 7.5 1.12 Rev.3.01 2005.02.07 REJ03B0104-0301 page 112 of 112 REVISION DESCRIPTION LIST Rev. No. 1.0 1.1 First Edition Page 5: Page 25: Page 33: 4501 GROUP DATA SHEET Revision Description Rev. date 000711 000726 Input/Output ports; Description of AIN0–AIN3 added. Fig.18 to Fig. 20; Description of “✕” revised. (2) Successive comparison register AD; this instruction (error) → these instructions (correct) Page 42: Table 16; Return condition of port P13/INT revised bit 1 (error) → bit 2 (correct), EXF1 (error) → EXF0 (correct) Pages 49 to 51: Fig. 46 to Fig. 49; Description of “✕” revised. Page 73: Page 80: Page 88: SEAM; Instruction code 0000010110 (error) → 0000100110 (correct) Description AD3, AD2 (error) → A3, A2 (correct) WRST; Operation: (WDF) ← 1? (error) → (WDF1) = 1? (correct) Description: Skips the next instruction when watchdog timer flag WDF1 is “1.” After skipping, clears (0) to the WDF1 flag. When the WDF1 flag is “0,” executes the next instruction....... Page 91: Page 93: Description of DEY; “Subtracts 1 from the contents of register Y.” added. Description of SEAM and description of SEA n are exchanged. (WDF1) ← 0, after skipping, (WDF1) ← 1 (error) Page 101: WRST; Skip condition: (WDF) = 1 (error) → (WDF1) = 1 (correct) Description: Skips the next instruction when watchdog timer flag WDF1 is “1.” After skipping, clears (0) to the WDF1 flag. When the WDF1 flag is “0,” executes the next instruction....... Page 110: (1) PROM mode; 12.5 V (error) → 12 V (correct) Fig. 52; title revised 1.2 Pages 3, 4, 22 : Character fonts errors revised 000905 → Page 100: WRST; (WDF1) = 1, after skipping, (WDF1) ← 0 (correct) (1/3) REVISION DESCRIPTION LIST Rev. No. 2.0 4501 GROUP DATA SHEET Revision Description Rev. date 010620 The 4501/4502 Group data sheet is separated. Page 9: Port block diagram (3); Block diagram of P12/CNTR pin revised. Page 25: Fig. 22 Timers structure; Block diagram of P12/CNTR pin revised. Page 28: (9) Precautions → (8) Precautions (8) Timer input/output pin (P12/CNTR pin) added. Fig. 23 added. Page 29: Page 30: WATCHDOG TIMER revised all. Fig. 24 → Fig. 25, Fig. 25 → Fig. 26 Fig. 26 NOP instruction added Page 39: Page 61: Page 62: Page 76: Page 90: Page 92: Fig. 37 Note 3 added. BL p, a, BLA p instructions revised. BML p, a, BMLA p instructions revised. TABP p instruction revised. TABP p instruction revised. BL p, a, BLA p, BML p, a, BMLA p instructions revised. Page 100: BL, BML, BLA, BMLA instructions; The second word revised. Page 101: BL, BML, BLA, BMLA instructions; The second word revised. Page 102: ABSOLUTE MAXIMUM RATINGS; VDD –0.3 to 6.0 → –0.3 to 6.5 Page 103: RECOMMENDED OPERATING CONDITIONS 1; VRST → 2.7 Note 1 revised. Operating condition map added. Page 104: RECOMMENDED OPERATING CONDITIONS 2; VRST → 2.7 Page 105: ELECTRICAL CHARACTERISTICS; VRST → 2.7 Page 106: A/D CONVERTER RECOMMENDED OPERATING CONDITIONS; VDD (Ta = 25 °C) Min. VRST → 2.7, Note added (2/3) REVISION HISTORY Rev. Date Page 3.00 Aug 27, 2004 All pages 4 5 25 26 30 31 32 41 52 78 101 3.01 Feb 07, 2005 1 2 4 29 49 110 111 112 4501 GROUP DATA SHEET Description Summary Words standardized: On-chip oscillator, A/D converter Power dissipation “Ta=25°C” added. ____________ Description of RESET pin revised. Table 9 : Control register of timer 1 and timer 2 revised. Fig.22 : Note 5 added. Some description revised. Fig.25 : “DI” instruction added. Table 11: Revised. Table 15 Port level and Note 4 revised, Note 6 added. 22 Electric Characteristic Differences Between Mask ROM and One Time PROM Version MCU, 23 Note on Power Source Voltage added. TABAD : Description revised. TABAD : Description revised. Package name revised. Package name revised. Package name revised. • Timer 1 and timer 2 count start timing and count time when operation starts added. 10 Timer 1 and timer 2 count start timing and count time when operation starts added. Package name revised. Package name revised. Package outline revised. (3/3) Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: (408) 382-7500, Fax: (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: (1628) 585-100, Fax: (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: 2265-6688, Fax: 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: (2) 2715-2888, Fax: (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: (21) 6472-1001, Fax: (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: 6213-0200, Fax: 6278-8001 http://www.renesas.com © 2005. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon 2.0

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