557G-06LFT

DATASHEET ICS557-06 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX Description Features The ICS557-06 is a two to four differential clock mux designed for use in PCI-Express applications. The device selects one of the two differential HCSL input pairs and fans out to four pairs of differential HCSL or LVDS outputs. • • • • • • • • • Packaged in 20-pin TSSOP Pb (lead) free packaging Operating voltage of 3.3 V Low power consumption Input differential clock of up to 200 MHz Jitter 60 ps (cycle-to-cycle) Output-to-output skew of 50 ps Available in industrial temperature range (-40 to +85°C) For PCIe Gen2/3 applications, see the 5V41067A Block Diagram OE VDD 2 CLKA CLKA IN1 CLKB IN1 IN2 CLKB MUX 2 to 1 CLKC CLKC IN2 CLKD CLKD 2 SEL IDT® 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX GND Rr (IREF) PD 1 ICS557-06 REV M 070512 ICS557-06 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX PCIE FAN OUT BUFFER Pin Assignment Select Table SEL 1 20 CLKA VDDIN 2 19 CLKA IN1 3 18 CLKB IN1 4 17 CLKB PD 5 16 GND IN2 6 15 VDD IN2 7 14 CLKC OE 8 13 CLKC GND 9 12 CLKD IREF 10 11 CLKD SEL Input Pair selected 0 1 IN2/ IN2 IN1/ IN1 20-pin (173 mil) TSSOP Pin Descriptions Pin Pin Name Pin Type Pin Description 1 2 3 4 5 6 7 8 SEL VDDIN IN1 IN1 PD IN2 IN2 OE Input Power Input Input Input Input Input Input SEL=1 selects IN1/IN1. SEL =0 selects IN2/ IN2. Internal pull-up resistor. Connect to +3.3 V. Supply voltage for Input clocks. HCSL true input signal 1. HCSL complimentary input signal 1. Powers down the chip and tri-states outputs when low. Internal pull-up HCSL true input signal 2. HCSL complimentary input signal 2. Provides fast output on, tri-states output (High = enable outputs; Low = disable). Internal pull-up resistor outputs. 9 10 11 12 13 14 15 16 GND Rr(IREF) CLKD CLKD CLKC CLKC VDDOUT GND Power Output Output Output Output Output Power Power Connect to ground. Precision resistor attached to this pin is connected to the internal current Differential Complimentary output clock D. Differential True output clock D. Differential Complimentary output clock C. Differential True output clock C. Connect to +3.3 V. Supply Voltage for Output Clocks. Connect to ground. 17 CLKB Output Differential Complimentary output clock B. 18 CLKB Output Differential True output clock B. 19 CLKA Output Differential Complimentary output clock A. 20 CLKA Output Differential True output clock A. IDT® 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX 2 ICS557-06 REV M 070512 ICS557-06 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX PCIE FAN OUT BUFFER Application Information Decoupling Capacitors External Components As with any high-performance mixed-signal IC, the ICS557-06 must be isolated from system power supply noise to perform optimally. A minimum number of external components are required for proper operation. Decoupling capacitors of 0.01 μF should be connected between VDD and GND pairs (2,9 and 15,16) as close to the device as possible. Decoupling capacitors of 0.01µF must be connected between each VDD and the PCB ground plane. Current Reference Source Rr (Iref) If board target trace impedance (Z) is 50Ω, then Rr = 475Ω (1%), providing IREF of 2.32 mA, output current (IOH) is equal to 6*IREF. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. Load Resistors RL Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. Since the clock outputs are open source outputs, 50 ohm external resistors to ground are to be connected at each clock output. Output Termination The PCI-Express differential clock outputs of the ICS557-06 are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are shown in detail in the PCI-Express Layout Guidelines section. 2) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the ICS557-06. The ICS557-06 can also be configured for LVDS compatible voltage levels. See the LVDS Compatible Layout Guidelines section. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. IDT® 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX 3 ICS557-06 REV M 070512 ICS557-06 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX PCIE FAN OUT BUFFER Output Structures IREF =2.3 mA R R 475Ω 6*IREF See Output Termination Sections - Pages 3 ~ 5 General PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. 2. No vias should be used between decoupling capacitor and VDD pin. 3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from the ICS557-06.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. IDT® 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX 4 ICS557-06 REV M 070512 ICS557-06 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX PCIE FAN OUT BUFFER PCI-Express Layout Guidelines Common Recommendations for Differential Routing L1 length, Route as non-coupled 50 ohm trace. L2 length, Route as non-coupled 50 ohm trace. L3 length, Route as non-coupled 50 ohm trace. RS RT Dimension or Value 0.5 max 0.2 max 0.2 max 33 49.9 Unit inch inch inch ohm ohm Differential Routing on a Single PCB L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 2 min to 16 max 1.8 min to 14.4 max Unit inch inch Differential Routing to a PCI Express Connector L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 0.25 to 14 max 0.225 min to 12.6 max Unit inch inch PCI-Express Device Routing L1 L2 L4 RS L1’ L4’ L2’ RS ICS557-06 Output Clock RT L3’ RT L3 PCI-Express Load or Connector Typical PCI-Express (HCSL) Waveform 700 mV 0 tOR 0.52 V 0.175 V 500 ps 500 ps tOF 0.52 V 0.175 V IDT® 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX 5 ICS557-06 REV M 070512 ICS557-06 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX PCIE FAN OUT BUFFER LVDS Compatible Layout Guidelines Vdiff Vp-p 0.45v 0.22v 0.58 0.28 0.80 0.40 0.60 0.3 R1a = R1b = R1 R2a = R2b = R2 Alternative T ermination for LVDS and other Common Differential Signals Vcm R1 R2 R3 R4 Note 1.08 33 150 100 100 0.6 33 78.7 137 100 0.6 33 78.7 none 100 ICS874003i-02 input compatible 1.2 33 174 140 100 Standard LVDS LVDS Device Routing Figure 3 L2 L1 R3 R1a L4 R4 L4' L2' L1' R1b R2a HCSL Output Buffer R2b L3' Down Device REF_CLK Input L3 Typical LVDS Waveform 1325 mV 1000 mV tOR 500 ps 1250 mV 1150 mV 500 ps tOF 1250 mV 1150 mV IDT® 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX 6 ICS557-06 REV M 070512 ICS557-06 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX PCIE FAN OUT BUFFER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS557-06. These ratings are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD, VDDA 5.5 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature (commercial) 0 to +70° C Ambient Operating Temperature (industrial) -40 to +85° C Storage Temperature -65 to +150° C Junction Temperature 125° C Soldering Temperature 260° C ESD Protection (Input) 2000 V min. (HBM) DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C Parameter Symbol Supply Voltage Conditions V Input High Voltage1 Min. Typ. Max. 3.135 3.465 Units VIH OE, SEL, PD 2.0 VDD +0.3 V VIL OE, SEL, PD VSS-0.3 0.8 V Input Leakage Current IIL 0 < Vin < VDD -5 5 μA Operating Supply Current IDD 50Ω, 2pF 55 mA IDDOE OE =Low 20 mA IDDPD No load, PD =Low 400 μA Input Low Voltage 1 2 Input Capacitance CIN Input pin capacitance 7 pF Output pin capacitance 6 pF 5 nH Output Capacitance COUT Pin Inductance LPIN Output Resistance ROUT CLK outputs Pull-up Resistor RPUP SEL, OE, PD 3.0 kΩ 110 kΩ 1. Single edge is monotonic when transitioning through region. 2. Inputs with pull-ups/-downs are not included. IDT® 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX 7 ICS557-06 REV M 070512 ICS557-06 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX PCIE FAN OUT BUFFER AC Electrical Characteristics - CLKOUTA/CLKOUTB Unless stated otherwise, VDD=3.3 V ±5%, Ambient Temperature -40 to +85° C Parameter Symbol Conditions Min. Typ. Max. Units 200 MHz HCSL termination 200 MHz LVDS termination 100 Input Frequency Output Frequency Input High Voltage1,2 VIH HCSL 660 700 Voltage1,2 VIL HCSL -150 0 Differential Input Voltages (VID) LVDS 250 350 450 mV Input Offset Voltage Input Low 850 mV mV (VIS) LVDS 1.125 1.25 1.375 V Output High Voltage1,2 VOH HCSL 660 700 850 mV Output Low Voltage1,2 VOL HCSL -150 0 27 mV Crossing Point Voltage1,2 Absolute 250 350 550 mV Crossing Point Voltage1,2,4 Variation over all edges 140 mV Jitter, Cycle-to-Cycle1,3 Rise Fall Time1,2 Time1,2 60 tOR From 0.175 V to 0.525 V 175 332 tOF From 0.525 V to 0.175 V 175 344 Rise/Fall Time Variation1,2 Skew between Outputs Duty Measured at crossing point Cycle1,3 45 ps 700 ps 700 ps 125 ps 50 ps 55 % Time5 All outputs 10 us Output Disable Time5 All outputs 10 us Input to Output Delay Input differential clock to output differential clock delay measured at mid point of input levels to mid pint of output levels 4.5 ns Output Enable 1 Test setup is RL=50 ohms with 2 pF, Rr = 475Ω (1%). 2 Measurement taken from a single-ended waveform. 3 Measurement taken from a differential waveform. 4 Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal. 5 CLKOUT pins are tri-stated when OE is Low asserted. CLKOUT is driven differential when OE is High unless its PD = low. IDT® 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX 8 ICS557-06 REV M 070512 ICS557-06 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX PCIE FAN OUT BUFFER Thermal Characteristics Parameter Symbol Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Conditions Min. Typ. Max. Units θ JA Still air 93 ° C/W θ JA 1 m/s air flow 78 ° C/W θ JA 3 m/s air flow 65 ° C/W 20 ° C/W θ JC Marking Diagrams (ICS557GI-06LF) (ICS557G-06LF) 20 ICS 11 20 ###### YYWW 557G06LF 1 ICS 10 11 ###### YYWW 557GI06LF 1 10 Notes: 1. ###### is the lot code. 2. YYWW is the last two digits of the year, and the week number that the part was assembled. 3. “LF” denotes Pb free package. 4. “I” denotes industrial temperature. 5. Bottom marking: (origin). Origin = country of origin if not USA. IDT® 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX 9 ICS557-06 REV M 070512 ICS557-06 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX PCIE FAN OUT BUFFER Package Outline and Package Dimensions (20-pin TSSOP, 173 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 20 Symbol E1 A A1 A2 b c D E E1 e L a aaa E INDEX AREA 1 2 D Max 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 6.40 6.60 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° -0.10 Min Max 0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.252 0.260 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0° 8° -0.004 *For reference only. Controlling dimensions in mm. A A2 Min Inches* A1 c -Ce b SEATING PLANE L aaa C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature 557G-06LF See Page 9 Tubes 20-pin TSSOP 0 to +70° C 557G-06LFT Tape and Reel 20-pin TSSOP 0 to +70° C 557GI-06LF Tubes 20-pin TSSOP -40 to +85° C 557GI-06LFT Tape and Reel 20-pin TSSOP -40 to +85° C "LF" suffix to the part number are the Pb-Free configuration, RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT® 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX 10 ICS557-06 REV M 070512 ICS557-06 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX PCIE FAN OUT BUFFER Revision History Rev. Date Originator M 07/05/12 — Description of Change Changed the typical value of the "Input to Output Delay" parameter in the "AC Electrical Characteristics - CLKOUTA/CLKOUTB" table from 3ns to 4.5ns. IDT® 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX 11 ICS557-06 REV M 070512 ICS557-06 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX PCIE FAN OUT BUFFER Innovate with IDT and accelerate your future networks. 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