DATASHEET
IDT5V41129
2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE
Description
Features
The IDT5V41129 is a spread spectrum clock generator that
supports PCI-Express Gen1 and Ethernet requirements.
The device is used for PC or embedded systems to
substantially reduce electromagnetic interference (EMI).
The device provides two differential (HCSL) spread
spectrum outputs. The spread type and amount are
configured via select pin. Using IDT’s patented
Phase-Locked Loop (PLL) techniques, the device takes a
25 MHz crystal input and produces two pairs of differential
outputs at 25 MHz, 100 MHz, 125 MHz or 200 MHz clock
frequencies for HCSL, and 25 MHz or 100 MHz for LVDS.
• Packaged in 16-pin TSSOP
• RoHS 5 (green) or RoHS 6 (green and lead free)
compliant packaging
•
•
•
•
•
•
•
•
Supports HCSL or LVDS output levels
Operating voltage of 3.3 V
Input frequency of 25 MHz
Jitter 60 ps (cycle-to-cycle)
Spread Spectrum capability
Industrial and commercial temperature ranges
For PCIe Gen2 applications, see the 5V41065
For PCIe Gen3 applications, see the 5V41235
Block Diagram
VDD
2
SS1:SS0
2
S1:S0
CLK0
Control
Logic
2
X1/ICLK
25 MHz
crystal or clock X2
Optional tuning crystal
capacitors
IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE
CLK0
Phase Lock Loop
CLK1
Clock
Buffer/
Crystal
Oscillator
CLK1
2
GND
1
Rr(IREF)
OE
IDT5V41129 REV D 02032014
IDT5V41129
2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE
PCIE SSCG
Pin Assignment
Output Select Table 1 (MHz)
S1
S0
CLK(1:0), CLK(1:0)
16
VDDXD
0
0
25M
0
1
100M
S0
1
S1
2
15
CLK0
SS0
3
14
CLK0
1
0
125M
X1/ICLK
4
13
GNDODA
1
1
200M
X2
5
12
VDDODA
OE
6
11
CLK1
GNDXD
7
10
SS1
8
9
Spread Selection Table 2
SS1
SS0
Spread%
CLK1
0
0
No Spread
IREF
0
1
Down -0.5
1
0
Down -0.75
1
1
No Spread
16-pin (173 mil) TSSOP
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
S0
Input
Select pin 0. See Table1. Internal pull-up resistor.
2
S1
Input
Select pin 1. See Table 1. Internal pull-up resistor.
3
SS0
Input
Spread Select pin 0. See Table 2. Internal pull-up resistor.
4
X1/ICLK
Input
Crystal or clock input. Connect to a 25 MHz crystal or single ended clock.
5
X2
6
OE
Input
7
GNDXD
Power
8
SS1
Input
9
IREF
Output Precision resistor attached to this pin is connected to the internal current
reference.
10
CLK1
Output HCSL complimentary clock output 1.
Output HCSL true clock output 1.
Output Crystal connection. Leave unconnected for clock input.
Output enable. Tri-states outputs and device is not shut down. Internal
pull-up resistor.
Connect to ground.
Spread Select pin 1. See Table 2. Internal pull-up resistor.
11
CLK1
12
VDDODA
Power
Connect to voltage supply +3.3 V for output driver and analog circuits
13
GNDODA
Power
Connect to ground.
14
CLK0
Output HCSL complimentary clock output 0.
15
CLK0
Output HCSL true clock output 0.
16
VDDXD
Power
Connect to voltage supply +3.3 V for crystal oscillator and digital circuit.
IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE
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2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE
PCIE SSCG
Applications Information
Output Structures
External Components
A minimum number of external components are required for
proper operation.
IREF
=2.3 mA
6*IREF
Decoupling Capacitors
Decoupling capacitors of 0.01F should be connected
between each VDD pin and the ground plane, as close to
the VDD pin as possible. Do not share ground vias between
components. Route power from power source through the
capacitor pad and then into ICS pin.
Crystal
A 25 MHz fundamental mode parallel resonant crystal
should be used. This crystal must have less than 300 ppm
of error across temperature in order for the IDT5V41129 to
meet PCI Express specifications.
R R 475
See Output Termination
Sections - Pages 3 ~ 5
Crystal Capacitors
General PCB Layout Recommendations
Crystal capacitors are connected from pins X1 to ground
and X2 to ground to optimize the accuracy of the output
frequency.
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1. Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
CL= Crystal’s load capacitance in pF
Crystal Capacitors (pF) = (CL- 8) * 2
2. No vias should be used between decoupling capacitor
and VDD pin.
For example, for a crystal with a 16 pF load cap, each
external crystal cap would be 16 pF. (16-8)*2=16.
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
Current Source (Iref) Reference Resistor - RR
If board target trace impedance (Z) is 50, then RR = 475
(1%), providing IREF of 2.32 mA. The output current (IOH) is
equal to 6*IREF.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the IDT5V41129.This includes signal
traces just underneath the device, or on layers adjacent to
the ground plane layer used by the device.
Output Termination
The PCI-Express differential clock outputs of the
IDT5V41129 are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown in
detail in the PCI-Express Layout Guidelines section.
The IDT5V41129 can also be configured for LVDS
compatible voltage levels. See the LVDS Compatible
Layout Guidelines section.
IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE
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2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE
PCIE SSCG
PCI-Express Layout Guidelines
Common Recommendations for Differential Routing
L1 length, Route as non-coupled 50 ohm trace.
L2 length, Route as non-coupled 50 ohm trace.
L3 length, Route as non-coupled 50 ohm trace.
RS
RT
Dimension or Value
0.5 max
0.2 max
0.2 max
33
49.9
Unit
inch
inch
inch
ohm
ohm
Differential Routing on a Single PCB
L4 length, Route as coupled microstrip 100 ohm differential trace.
L4 length, Route as coupled stripline 100 ohm differential trace.
Dimension or Value
2 min to 16 max
1.8 min to 14.4 max
Unit
inch
inch
Differential Routing to a PCI Express Connector
L4 length, Route as coupled microstrip 100 ohm differential trace.
L4 length, Route as coupled stripline 100 ohm differential trace.
Dimension or Value
0.25 to 14 max
0.225 min to 12.6 max
Unit
inch
inch
PCI-Express Device Routing
L1
L2
L4
RS
L1’
L4’
L2’
RS
IDT5V41129
Output
Clock
RT
L3’
RT
L3
PCI-Express
Load or
Connector
Typical PCI-Express (HCSL) Waveform
700 mV
0
tOR
500 ps
0.525 V
0.175 V
500 ps
tOF
0.525 V
0.175 V
IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE
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2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE
PCIE SSCG
LVDS Compatible Layout Guidelines
LVDS Recommendations for Differential Routing
L1 length, Route as non-coupled 50 ohm trace.
L2 length, Route as non-coupled 50 ohm trace.
RP
RQ
RT
Dimension or Value
0.5 max
0.2 max
100
100
150
Unit
inch
inch
ohm
ohm
ohm
LVDS Device Routing
L1
L3
RQ
L3’
L1’
RT
IDT5V41129
Clock
Output
RP
RT
L2’
LVDS
Device
Load
L2
Typical LVDS Waveform
1325 mV
1000 mV
tOR
500 ps
1250 mV
1150 mV
500 ps
tOF
1250 mV
1150 mV
IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE
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2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE
PCIE SSCG
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT5V41129. These ratings are stress
ratings only. Functional operation of the device at these or any other conditions above those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended
operating temperature range.
Item
Rating
Supply Voltage, VDDXD, VDDODA
7V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature (commercial)
0 to +70C
Ambient Operating Temperature (industrial)
-40 to +85C
Storage Temperature
-65 to +150C
Junction Temperature
125C
Soldering Temperature
260C
ESD Protection (Input)
2000 V min. (HBM)
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±10%, Ambient Temperature -40 to +85C
Parameter
Symbo
l
Supply Voltage
V
Input High Voltage1
Input Low Voltage1
2
Input Leakage Current
Operating Supply Current
Input Capacitance
Output Capacitance
Conditions
Min.
Typ.
2.97
3.3
Max.
Units
3.63
V
VIH
S0, S1, OE, ICLK, SS0, SS1
2.0
VDD +0.3
V
VIL
S0, S1, OE, ICLK, SS0, SS1
VSS-0.3
0.8
V
IIL
0 < Vin < VDD
-5
5
A
IDD
50, 2 pF
78
mA
IDDOE
OE =Low
44
mA
Input pin capacitance
7
pF
Output pin capacitance
6
pF
5
nH
CIN
COUT
Pin Inductance
LPIN
Output Resistance
ROUT
CLK outputs
Pull-up Resistor
RPU
S0, S1, OE, SS0, SS1
3.0
k
100
k
1. Single edge is monotonic when transitioning through region.
2. Inputs with pull-ups/-downs are not included.
IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE
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2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE
PCIE SSCG
AC Electrical Characteristics - CLK0/CLK1, CLK0/CLK1
Unless stated otherwise, VDD=3.3 V ±10%, Ambient Temperature -40 to +85C
Parameter
Symbol
Conditions
Min.
Typ.
Input Frequency
Max.
Units
25
Output Frequency
MHz
HCSL termination
25
200
MHz
LVDS termination
25
100
MHz
Output High
Voltage1,2
VOH
HCSL
660
700
850
mV
Output Low
Voltage1,2
VOL
HCSL
-150
0
27
mV
Absolute
250
350
550
mV
140
mV
100
ps
Crossing Point
Voltage1,2
Crossing Point Voltage1,2,4
Jitter,
Variation over all edges
Cycle-to-Cycle1,3
60
Frequency Synthesis Error
All outputs
Modulation Frequency
Rise Time1,2
Fall
Time1,2
Rise/Fall Time
0
ppm
Spread spectrum
30
31.5
33
kHz
tOR
From 0.175 V to 0.525 V
175
332
700
ps
tOF
From 0.525 V to 0.175 V
175
344
700
ps
125
ps
Variation1,2
Output to Output Skew
Duty Cycle1,3
45
50
ps
55
%
Output Enable
Time5
All outputs
10
12
µs
Output Disable
Time5
All outputs
10
12
µs
Stabilization Time
tSTABLE
From power-up VDD=3.3 V
3.0
3.5
ms
Spread Spectrum Transition
Time
tSPREAD
Stabilization time after spread
spectrum changes
3.0
3.5
ms
Note 1: Test setup is RL=50 ohms with 2 pF, Rr = 475 (1%).
Note 2: Measurement taken from a single-ended waveform.
Note 3: Measurement taken from a differential waveform.
Note 4: Measured at the crossing point where instantaneous voltages of both CLK and CLK are equal.
Note 5: CLK pins are tri-stated when OE is low asserted. CLK is driven differential when OE is high.
Electrical Characteristics - Differential Phase Jitter
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Notes
Jitter, Phase
tjphasePLL
PCIe Gen 1
-
-
86
ps (p-p)
1, 2
Note 1: Guaranteed by design and characterization, not 100% tested in production.
Note 2: See http://www.pcisig.com for complete specs.
IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE
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PCIE SSCG
Thermal Characteristics
Parameter
Symbol
JA
Thermal Resistance Junction to
Ambient
JA
JA
Conditions
Typ.
Still air
1 m/s air flow
3 m/s air flow
JC
Thermal Resistance Junction to Case
Marking Diagram (5V41129PGG)
16
Min.
78
C/W
70
C/W
68
C/W
37
C/W
Marking Diagram (5V41129PGGI)
9
16
IDT5V411
29PGG
YYWW$
9
IDT5V411
29PGGI
YYWW$
LOT xy
LOT xy
1
Max. Units
1
8
8
Notes:
1. Line 1 and 2: IDT part number.
2. Line 3: YYWW – Date code; $ – Assembly location.
3. “G” after the two-letter package code designates RoHS compliant package.
4. “I” at the end of part number indicates industrial temperature range.
IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE
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PCIE SSCG
Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches*
16
Symbol
E1
A
A1
A2
b
C
D
E
E1
e
L
a
aaa
E
INDEX
AREA
1 2
D
A
A2
Min
Max
-1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
4.90
5.1
6.40 BASIC
4.30
4.50
0.65 Basic
0.45
0.75
0
8
-0.10
A1
Min
Max
-0.047
0.002
0.006
0.032
0.041
0.007
0.012
0.0035 0.008
0.193
0.201
0.252 BASIC
0.169
0.177
0.0256 Basic
0.018
0.030
0
8
-0.004
c
-Ce
b
SEATING
PLANE
L
aaa C
Ordering Information
Part / Order Number
Marking
5V41129PGG
see page 8
Shipping Packaging
Package
Temperature
Tubes
16-pin TSSOP
0 to +70 C
5V41129PGG8
Tape and Reel
16-pin TSSOP
0 to +70 C
5V41129PGGI
Tubes
16-pin TSSOP
-40 to +85 C
5V41129PGGI8
Tape and Reel
16-pin TSSOP
-40 to +85 C
“G” after the two-letter package code are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE
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2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE
PCIE SSCG
Revision History
Rev.
Date
Originator
Description of Change
C
10/30/12
D. Chan
Updated device top-side markings per latest ProdBuilder info.
D
02/03/14
RDW
Typo for part number in Termination drawings. Moved to final.
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PCIE SSCG
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