840001BGLF

ICS840001 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS840001 is a Fibre Channel Clock Generator ICS and a member of the HiPerClocksTM family of high HiPerClockS™ performance devices from IDT. The ICS840001 uses a 26.5625MHz cr ystal to synthesize either 106.25MHz or 212.5MHz, using the FREQ_SEL pin. The ICS840001 has excellent phase jitter performance, over the 637kHz – 10MHz integration range. The ICS840001 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. • One LVCMOS/LVTTL output, 7Ω typical output impedence • Crystal oscillator interface designed for 26.5625MHz, 18pF parallel resonant crystal • Selectable 106.25MHz or 212.5MHz output frequency • VCO range: 560MHz to 680MHz • RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal (637kHz - 10MHz): 0.696ps (typical) • RMS phase noise at 106.25MHz (typical) Phase noise: Offset Noise Power 100Hz ............... -94.4 dBc/Hz 1kHz ............. -119.9 dBc/Hz 10kHz ............. -130.2 dBc/Hz 100kHz ............. -131.5 dBc/Hz • 3.3V operating supply • -30°C to 85°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages FUNCTION TABLE Input FREQ_SEL Output Frequencies 0 106.25MHz (Default) 1 212.5MHz Crystal: 26.5625MHz BLOCK DIAGRAM OE FREQ_SEL (Pullup) VDDA OE XTAL_OUT XTAL_IN (Pulldown) XTAL_IN OSC XTAL_OUT PIN ASSIGNMENT Phase Detector VCO 1 ÷3 Q0 637.5MHz w/ 26.5625MHz Ref. 0 ÷6 M = ÷24 (fixed) IDT ™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 1 1 2 3 4 8 7 6 5 VDD Q0 GND FREQ_SEL ICS840001 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View ICS840001BG REV. A JUNE 13, 2007 ICS840001 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name 1 VDDA Power Type 2 OE Input 5 XTAL_OUT, XTAL_IN FREQ_SEL Input 6 GND Power 7 Q0 Output 8 VDD Power 3, 4 Input Description Analog supply pin. Output enable pin. When HIGH, Q0 output is enabled. Pullup When LOW, forces Q0 to Hi-Z state. LVCMOS/LVTTL interface levels. Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. Power supply ground. Single-ended clock output. LVCMOS/LVTTL interface levels. 7Ω typical output impedance. Core supply pin. NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions CPD Power Dissipation Capacitance Minimum VDD, VDDA = 3.465V Typical Maximum Units 4 pF 24 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ ROUT Output Impedance 5 7 12 Ω TABLE 3. CONTROL FUNCTION TABLE Control Inputs Output OE Q0 0 Hi-Z 1 Active IDT ™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 2 ICS840001BG REV. A JUNE 13, 2007 ICS840001 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 101.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -30°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VDD Core Supply Voltage Test Conditions 3.135 3.3 3.465 V 3.135 3.3 VDDA Analog Supply Voltage 3.465 V IDD Power Supply Current 80 mA IDDA Analog Supply Current 10 mA Maximum Units VDD + 0.3 V TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -30°C TO 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage Test Conditions Minimum Typical 2 0.8 V FREQ_SEL VDD = VIN = 3.465V -0.3 150 µA OE VDD = VIN = 3.465V 5 µA IIH Input High Current IIL Input Low Current VOH Output High Voltage; NOTE 1 FREQ_SEL VDD = 3.465V, VIN = 0V -5 µA OE VDD = 3.465V, VIN = 0V -150 µA 2.6 V VOL Output Low Voltage; NOTE 1 NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information Section, "3.3V Output Load Test Circuit". 0.5 V Maximum Units TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Mode of Oscillation Minimum Typical Fundamental Frequency 26.5625 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF IDT ™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 3 ICS840001BG REV. A JUNE 13, 2007 ICS840001 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 6. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -30°C TO 85°C Symbol Parameter fOUT Output Frequency tjit(Ø) RMS Phase Jitter (Random); NOTE 1 t R / tF Output Rise/Fall Time Test Conditions Minimum Typical Maximum Units FREQ_SEL = 1 186.66 212.5 226.66 MHz FREQ_SEL = 0 fOUT = 106.25MHz, (637kHz to 10MHz) fOUT = 212.5MHz, (2.55MHz to 20MHz) 20% to 80% 93.33 106.25 113.33 MHz fOUT = 106.25MHz fOUT = 212.5MHz All parameters are characterized @ 212.5MHz and 106.25MHz. NOTE 1: Please refer to the Phase Noise Plots. odc Output Duty Cycle IDT ™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 4 0.696 ps 0.458 ps 250 600 ps 48 45 52 55 % % ICS840001BG REV. A JUNE 13, 2007 ICS840001 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TYPICAL PHASE NOISE AT 106.25MHZ ➤ 0 -10 Fibre Channel Filter -20 -40 106.25MHz -50 RMS Phase Jitter (Random) 637k to 10MHz = 0.696ps (typical) -60 -70 -80 -90 Raw Phase Noise Data -100 -110 ➤ NOISE POWER dBc Hz -30 -120 -130 -140 -150 ➤ -160 -170 -180 Phase Noise Result by adding Fibre Channel Filter to raw data -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 212.5MHZ ➤ 0 -10 -20 Fibre Channel Filter -40 212.5MHz -50 RMS Phase Jitter (Random) 2.55MHz to 20MHz = 0.458ps -60 -70 -80 -90 Raw Phase Noise Data -100 ➤ NOISE POWER dBc Hz -30 -110 -120 -130 -140 -150 -160 -170 ➤ -180 -190 100 1k Phase Noise Result by adding Fibre Channel Filter to raw data 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) IDT ™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 5 ICS840001BG REV. A JUNE 13, 2007 ICS840001 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 1.65V ± 5% Phase Noise Plot Noise Power SCOPE VDD, VDDA Qx Phase Noise Mask LVCMOS GND Offset Frequency f1 -1.65V ± 5% f2 RMS Jitter = Area Under the Masked Phase Noise Plot 3.3V OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER V DDO 2 Q0 80% t PW t odc = PERIOD t PW Clock Outputs 80% 20% 20% tR tF x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD IDT ™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR OUTPUT RISE/FALL TIME 6 ICS840001BG REV. A JUNE 13, 2007 ICS840001 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS840001 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VDDA pin. 3.3V VDD .01μF 10Ω VDDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING RECOMMENDATIONS FOR UNUSED INPUT PINS INPUTS: LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. IDT ™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 7 ICS840001BG REV. A JUNE 13, 2007 ICS840001 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR CRYSTAL INPUT INTERFACE parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted fordifferent board layouts. The ICS840001 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 26.5625MHz, 18pF XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p FIGURE 2. CRYSTAL INPUt INTERFACE LVCMOS TO XTAL INTERFACE impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VDD VDD R1 Ro .1uf Rs Zo = 50 XTAL_IN R2 Zo = Ro + Rs XTAL_OUT FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE IDT ™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 8 ICS840001BG REV. A JUNE 13, 2007 ICS840001 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR LAYOUT GUIDELINE board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. The output frequency can be set at either 106.25MHz or 212.5MHz. Leaving the R1 un-installed (or install 1kΩ pull-down) will set the output frequency at 106.25MHz. Installing the R1 pull up will set the output frequency at 212.5MHz. Figure 4A shows a schematic example of the ICS840001. An example of LVCMOS termination is shown in this schematic. Additional LVCMOS termination approaches are shown in the LVCMOS Termination Application Note. In this example, an 18 pF parallel resonant 26.5625MHz crystal is used. The C1= 27pF and C2 = 33pF are recommended for frequency accuracy. For different VDD VDDA R2 10 C3 10uF VDD C4 0.1u R1 U1 1K OE C2 33pF 1 2 3 4 VDDA OE XTAL_OUT XTAL_IN VDD Q0 GND FREQ_SEL 8 7 6 5 VDD Q R3 43 Zo = 50 Ohm FRE_SEL X1 C5 0.1u ICS840001 C1 27pF LVCMOS VDD=3.3V FIGURE 4A. ICS840001 SCHEMATIC EXAMPLE PC BOARD LAYOUT EXAMPLE Figure 4B shows an example of P.C. board layout. The crystal X1 footprint in this example allows either surface mount (HC49S) or through hole (HC49) package. C3 is 0805. C1 and C2 are 0402. Other resistors and capacitors are 0603. This layout assumes that the board has clean analog power and ground planes. FIGURE 4B. ICS840001 PC BOARD LAYOUT EXAMPLE IDT ™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 9 ICS840001BG REV. A JUNE 13, 2007 ICS840001 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θ JA by Velocity (Meters Per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W TRANSISTOR COUNT The transistor count for ICS840001 is: 1521 IDT ™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 10 ICS840001BG REV. A JUNE 13, 2007 ICS840001 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 8 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT ™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 11 ICS840001BG REV. A JUNE 13, 2007 ICS840001 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 7. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS840001BG 001B 8 lead TSSOP tube -30°C to 85°C ICS840001BGT 001B 8 lead TSSOP 2500 tape & reel -30°C to 85°C ICS840001BGLF 001BL 8 lead "Lead Free" TSSOP tube -30°C to 85°C ICS840001BGLFT 001BL 8 lead "Lead Free" TSSOP 2500 tape & reel -30°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 12 ICS840001BG REV. A JUNE 13, 2007 ICS840001 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR REVISION HISTORY SHEET Rev Table Page A T9 11 1 7 8 12 A T7 Description of Change Date Ordering Information Table - corrected count from 154 per tube to 100. Features Section - added lead-free bullet. Added Recommendations for Unused Input Pins. Added LVCMOS to XTAL Interface. Ordering Information Table - added lead-free par t number, marking and note. IDT ™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR 13 10/15/04 6/13/07 ICS840001BG REV. A JUNE 13, 2007 ICS840001 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 netcom@idt.com 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA