840N011BGILF

FemtoClock® NG Crystal-to-LVCMOS/ LVTTL Clock Synthesizer ICS840N011I DATASHEET General Description Features The ICS840N011I is an LVCMOS/LVTTL clock synthesizer designed for Fibre Channel applications. The device generates a 106.25MHz clock signal from a 26.5625MHz crystal or a 100MHz clock signal from a 25MHz crystal with excellent phase jitter performance. The device uses IDT’s fourth generation FemtoClock® NG technology for an optimum of high clock frequency, low phase noise performance and low power consumption and high power supply noise rejection.The device supports 2.5V or 3.3V voltage supply and is packaged in a small, lead-free (RoHS 6) 8-lead TSSOP package. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. • • Fourth generation FemtoClock® NG technology • • • One 2.5V or 3.3V LVCMOS/LVTTL clock output • • • • LVCMOS/LVTTL interface level for the output enable input 106.25MHz output clock synthesized from a 26.5625MHz fundamental mode crystal Crystal interface designed for a 12pF parallel resonant crystal RMS phase jitter @ 100MHz, using a 25MHz crystal (637kHz - 10MHz): 0.185ps (maximum) Full 2.5V or 3.3V supply voltage Lead-free (RoHS 6) packaging -40°C to 85°C ambient operating temperature Frequency Table fXTAL (MHz) Output Frequency (MHz) 25 100 26.5625 106.25 30.72 122.88 31.25 125 Function Table Input OE Output Enable 0 Output Q is disabled in high-impedance state 1 (default) Output Q is enabled. NOTE: OE is an asynchronous control. Block Diagram XTAL_IN OSC XTAL_OUT Pin Assignment PFD & LPF FemtoClock® NG VCO 588-765MHz ÷6 Pullup ICS840N011BGI REVISION A AUGUST 16, 2013 1 2 3 4 8 7 6 5 VDD Q GND DNU ICS840N011I 8-lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View ÷24 OE Q VDDA OE XTAL_OUT XTAL_IN 1 ©2013 Integrated Device Technology, Inc. FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER ICS840N011I Data Sheet Pin Descriptions and Characteristics Table 1. Pin Descriptions Number Name Type Description 1 VDDA Power 2 OE Input 3, 4 XTAL_OUT, XTAL_IN Input 5 DNU 6 GND Power Power supply ground. 7 Q Output Single-ended clock output. LVCMOS/LVTTL interface levels. 8 VDD Power Core supply pin. Analog power supply. Pullup Output enable pin. LVCMOS interface levels. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Do not use. Do not connect. NOTE: Pullup refers to an internal input resistor. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance OE 3.5 pF Power Dissipation Capacitance VDD = 3.465V 11 pF CPD VDD = 2.625V 9 pF RPULLUP Input Pullup Resistor 51 k  Output Impedance VDD = 3.3V 15 ROUT VDD =2.5V 19  ICS840N011BGI REVISION A AUGUST 16, 2013 Test Conditions 2 Minimum Typical Maximum Units ©2013 Integrated Device Technology, Inc. FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER ICS840N011I Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 3.63V Inputs, VI XTAL_IN Other Inputs 0V to 2V -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 117°C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 3A. Power Supply DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C Symbol Parameter VDD Core Supply Voltage VDDA Test Conditions Minimum Typical Maximum Units 2.375 3.3 3.465 V Analog Supply Voltage VDD – 0.18 3.3 VDD V VDDA Analog Supply Voltage VDD – 0.18 2.5 VDD V IDDA Analog Supply Current 18 mA IDD Power Supply Current 67 mA Maximum Units Table 3B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum VIH Input High Voltage VDD = 3.3V 2 VDD + 0.3 V VDD = 2.5V 1.7 VDD + 0.3 V VIL Input Low Voltage VDD = 3.3V -0.3 0.8 V VDD = 2.5V -0.3 0.7 V IIH Input High Current OE VDD = VIN = 3.465V or 2.625V 5 µA IIL Input Low Current OE VDD = 3.465V 3.465V or 2.625V, VIN = 0V -150 µA Output High Voltage; NOTE 1 VDD = 3.465V 2.6 V VOH Q VDD = 2.625V 1.8 V VOL Output Low Voltage; NOTE 1 Q VDD = 3.465V or 2.625V Typical 0.5 V NOTE 1: Output terminated with 50 to VDD / 2. See Parameter Measurement Information Section, LVCMOS Output Load Test Circuit Diagrams. ICS840N011BGI REVISION A AUGUST 16, 2013 3 ©2013 Integrated Device Technology, Inc. FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER ICS840N011I Data Sheet Table 4. Crystal Characteristics Parameter Test Conditions Minimum Maximum Units 31.88 MHz Equivalent Series Resistance (ESR) 80  Shunt Capacitance 7 pF Mode of Oscillation Typical Fundamental Frequency 24.50 Capacitive Load (CL) 26.5625 12 pF AC Characteristics Table 5. AC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C Symbol Parameter fOUT Output Frequency tjit(Ø) N RMS Phase Jitter (Random); NOTE 1 Single-Side Band Noise Power tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical Maximum Units 98.00 106.25 127.52 MHz fOUT = 100MHz, 25MHz Crystal, Integration Range: 637kHz – 10MHz 0.140 0.185 ps fOUT = 106.25MHz, 26.5625MHz Crystal, Integration Range: 637kHz – 10MHz 0.139 0.177 ps fOUT = 106.25MHz, Offset: 10Hz -60.4 dBc/Hz fOUT = 106.25MHz, Offset: 100Hz -87.4 dBc/Hz fOUT = 106.25MHz, Offset: 1kHz -117.8 dBc/Hz fOUT = 106.25MHz, Offset: 10kHz -130.7 dBc/Hz fOUT = 106.25MHz, Offset: 100kHz -134.9 dBc/Hz fOUT = 106.25MHz, Offset: 1MHz -145.6 dBc/Hz fOUT = 106.25MHz, Offset: 10MHz -158.9 dBc/Hz 20% to 80% 200 600 ps 48 52 % NOTE: Characterized with 25MHz, 26.5625MHz, 30.72MHz and 31.25MHz crystals. NOTE 1: Please refer to the phase noise plots. ICS840N011BGI REVISION A AUGUST 16, 2013 4 ©2013 Integrated Device Technology, Inc. FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER ICS840N011I Data Sheet Noise Power (dBc/Hz) Typical Phase Noise at 100MHz (637kHz - 10MHz) Offset Frequency (Hz) Noise Power (dBc/Hz) Typical Phase Noise at 106.25MHz (637kHz - 10MHz) Offset Frequency (Hz) ICS840N011BGI REVISION A AUGUST 16, 2013 5 ©2013 Integrated Device Technology, Inc. FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER ICS840N011I Data Sheet Parameter Measurement Information 1.65V ± 5% 1.25V ± 5% 1.65V ± 5% 1.25V ± 5% SCOPE VDD VDDA SCOPE VDD VDDA Qx Qx GND GND -1.25V ± 5% -1.65V ± 5% 2.5V LVCMOS/LVTTL Output Load AC Test Circuit 3.3V LVCMOS/LVTTL Output Load AC Test Circuit 80% 80% 20% 20% Q RMS Phase Jitter tR tF Output Rise/Fall Time V DD 2 Q t PW t odc = PERIOD t PW x 100% t PERIOD Output Duty Cycle/Pulse Width/Period ICS840N011BGI REVISION A AUGUST 16, 2013 6 ©2013 Integrated Device Technology, Inc. FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER ICS840N011I Data Sheet Applications Information Overdriving the XTAL Interface can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and changing R2 to 50. The values of the resistors can be increased to reduce the loading for a slower and weaker LVCMOS driver. Figure 1B shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL termination with one side of the driver feeding the XTAL_IN input. It is recommended that all components in the schematics be placed in the layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. The XTAL_IN input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The XTAL_OUT pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than 0.2V/ns. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. Figure 1A shows an example of the interface diagram for a high speed 3.3V LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface ICS840N011BGI REVISION A AUGUST 16, 2013 7 ©2013 Integrated Device Technology, Inc. FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER ICS840N011I Data Sheet Schematic Layout capacitor on the VDD pin must be placed on the device side with direct return to the ground plane though vias. The remaining filter components can be on the opposite side of the PCB. Figure 2 shows an example ICS840N011I application schematic in which the device is operated at VDD = VDDA = +3.3V. The schematic example focuses on functional connections and is intended as an example only and may not represent the exact user configuration. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. For example OE can be configured from an FPGA instead of set with pull up and pull down resistors as shown. Power supply filter component recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise, so to achieve optimum jitter performance isolation of the VDD pin from power supply is required. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1µF Figure 2. ICS840N011I Application Schematic ICS840N011BGI REVISION A AUGUST 16, 2013 8 ©2013 Integrated Device Technology, Inc. FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER ICS840N011I Data Sheet Power Considerations This section provides information on power dissipation and junction temperature for the ICS840N011I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS840N011I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • Power (core)MAX = VDD_MAX * (IDD + IDDA) = 3.465V *(67mA + 18mA) = 294.53mW • Output Impedance ROUT Current due to Loading 50 to VDD/2 Output Current IOUT = VDD_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 15)] = 26.7mA • Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 15 * (26.7mA)2 = 10.7mW • Total Power (ROUT) = 10.7mW * 1 = 10.7mW Dynamic Power Dissipation at 125MHz Power (125MHz) = CPD * Frequency * (VDD)2 = 11pF * 125MHz * (3.465V)2 = 16.51mW Total Power (125MHz) = 16.51mW * 1 = 16.51mW Total Power Dissipation • Total Power = Power (core)MAX + Power (ROUT) + Power (125MHz) = 294.53mW + 10.7mW + 16.51mW = 321.74mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance qJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 117°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.322W *117°C/W = 122.7°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for 8 Lead TSSOP, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS840N011BGI REVISION A AUGUST 16, 2013 0 117°C/W 9 ©2013 Integrated Device Technology, Inc. FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER ICS840N011I Data Sheet Reliability Information Table 7. JA vs. Air Flow Table for a 8-lead TSSOP JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 117°C/W Transistor Count The transistor count for ICS840N011I is: 24,811 Package Outline and Package Dimensions Package Outline - G Suffix for 8 Lead TSSOP Table 8. Package Dimensions Symbol N A A1 A2 b c D E E1 e L  aaa All Dimensions in Millimeters Minimum Maximum 8 1.20 0.5 0.15 0.80 1.05 0.19 0.30 0.09 0.20 2.90 3.10 6.40 Basic 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS840N011BGI REVISION A AUGUST 16, 2013 10 ©2013 Integrated Device Technology, Inc. FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER ICS840N011I Data Sheet Table 9. Ordering Information Part/Order Number 840N011BGILF 840N011BGILFT Marking 11BIL 11BIL ICS840N011BGI REVISION A AUGUST 16, 2013 Package Lead-Free, 8-lead TSSOP Lead-Free, 8-lead TSSOP 11 Shipping Packaging Tube Tape & Reel Temperature -40C to 85C -40C to 85C ©2013 Integrated Device Technology, Inc. FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER ICS840N011I Data Sheet We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support Sales netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. 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