FemtoClock® Crystal-to-3.3V, 2.5V
LVPECL Frequency Synthesizer
843004I-01
General Description
Features
The 843004I-01 is a 4 output LVPECL synthesizer optimized to
generate Ethernet reference clock frequencies. Using a 25MHz
18pF parallel resonant crystal, the following frequencies can be
generated based on the settings of 2 frequency select pins
(F_SEL[1:0]): 156.25MHz, 125MHz, 62.5MHz. The 843004I-01 uses
IDT’s 3rd generation low phase noise VCO technology and can
achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet
jitter requirements. The 843004I-01 is packaged in a small 24-pin
TSSOP package.
•
•
Four 3.3V differential LVPECL output pairs
•
Supports the following output frequencies: 156.25MHz, 125MHz,
62.5MHz
•
•
VCO range: 560MHz – 680MHz
•
•
•
Full 3.3V or 2.5V supply modes
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended clock input
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 0.54ps (typical)
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) package
Frequency Select Function Table
Inputs
F_SEL1
F_SEL0
M Div. Value
N Div. Value
M/N Div. Value
Output Frequency (MHz)
(25MHz Reference)
0
0
25
4
6.25
156.25
0
1
25
5
5
125
1
0
25
10
2.5
62.5
1
1
25
Not Used
Not Used
Block Diagram
F_SEL[1:0]
Pin Assignment
2
Pulldown
nPLL_SEL Pulldown
F_SEL[1:0]
TEST_CLK Pulldown
1
XTAL_IN
OSC
0
0 0 ÷4
0 1 ÷5
1 0 ÷10
1 1 not used
1
Phase
Detector
XTAL_OUT
VCO
625MHz
(w/25MHz
Reference)
Q0
nQ0
Q1
nQ1
0
Q2
nXTAL_SEL Pulldown
nQ2
M = 25 (fixed)
Q3
nQ3
MR Pulldown
©2016 Integrated Device Technology, Inc
1
nQ1
Q1
VCCO
Q0
nQ0
MR
nPLL_SEL
nc
VCCA
F_SEL0
VCC
F_SEL1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQ2
Q2
VCCO
Q3
nQ3
VEE
VCC
nXTAL_SEL
TEST_CLK
VEE
XTAL_IN
XTAL_OUT
843004I-01
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm
package body
G Package
Top View
January 18, 2016
843004I-01 Data Sheet
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 2
nQ1, Q1
Output
Differential output pair. LVPECL interface levels.
3, 22
VCCO
Power
Output supply pins.
4, 5
Q0, nQ0
Output
Differential output pair. LVPECL interface levels.
6
MR
Input
Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing
the true outputs Qx to go low and the inverted outputs nQx to go high. When logic
LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface
levels.
7
nPLL_SEL
Input
Pulldown
Selects either the PLL or the active input reference to be routed to the output
dividers. When LOW, selects PLL (PLL Enable). When HIGH, selects the reference
clock (PLL Bypass). LVCMOS/LVTTL interface levels.
8
nc
Unused
9
VCCA
Power
10,
12
F_SEL0,
F_SEL1
Input
11, 18
VCC
Power
Core supply pins.
13,
14
XTAL_OUT,
XTAL_IN
Input
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input.
15, 19
VEE
Power
Negative supply pins.
16
TEST_CLK
Input
Pulldown
Single-ended clock input. LVCMOS/LVTTL interface levels.
17
nXTAL_SEL
Input
Pulldown
Selects between the single-ended TEST_CLK or crystal interface as the PLL
reference source. When HIGH, selects TEST_CLK. When LOW, selects XTAL
inputs. LVCMOS/LVTTL interface levels.
20, 21
nQ3, Q3
Output
Differential output pair. LVPECL interface levels.
23, 24
Q2, nQ2
Output
Differential output pair. LVPECL interface levels.
No connect.
Analog supply pin.
Pulldown
Frequency select pins. LVCMOS/LVTTL interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
Test Conditions
RPULLDOWN Input Pulldown Resistor
©2016 Integrated Device Technology, Inc
2
Minimum
Typical
Maximum
Units
4
pF
51
k
January 18, 2016
843004I-01 Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, JA
70C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE =0V, TA = -40°C to 85°C
Symbol
Parameter
VCC
Test Conditions
Minimum
Typical
Maximum
Units
Core Supply Voltage
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
3.135
3.3
3.465
V
VCCO
Output Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
130
mA
ICCA
Analog Supply Current
15
mA
Included in IEE
Table 3B. Power Supply DC Characteristics, VCC = VCCO = 2.5V ± 5%, VEE =0V, TA = -40°C to 85°C
Symbol
Parameter
VCC
Minimum
Typical
Maximum
Units
Core Supply Voltage
2.375
2.5
2.625
V
VCCA
Analog Supply Voltage
2.375
2.5
2.625
V
VCCO
Output Supply Voltage
2.375
2.5
2.625
V
IEE
Power Supply Current
120
mA
ICCA
Analog Supply Current
12
mA
©2016 Integrated Device Technology, Inc
Test Conditions
Included in IEE
3
January 18, 2016
843004I-01 Data Sheet
Table 3C. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = 3.3V ± 5% or 2.5V ± 5%, VEE =0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
VIH
Input High Voltage
VCC = 3.3V ± 5%
VIL
Input
Low Voltage
IIH
Input
High Current
TEST_CLK,
MR, F_SEL[0:1],
nPLL_SEL, nXTAL_SEL
VCC = VIN = 3.465V
IIL
Input
Low Current
TEST_CLK,
MR, F_SEL[0:1],
nPLL_SEL, nXTAL_SEL
VCC = 3.465V, VIN = 0V
Typical
Maximum
Units
2
VCC + 0.3
V
VCC = 2.5V ± 5%
1.7
VCC + 0.3
V
VCC = 3.3V ± 5%
-0.3
0.8
V
VCC = 2.5V ± 5%
-0.3
0.7
V
150
µA
-5
µA
Table 3D. LVPECL DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE =0V, TA = -40°C to 85°C
Symbol
Parameter
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
Typical
Maximum
Units
VCCO – 1.4
VCCO – 0.9
V
VCCO – 2.0
VCCO – 1.7
V
0.6
1.0
V
Maximum
Units
NOTE 1: Outputs termination with 50 to VCCO – 2V.
Table 3E. LVPECL DC Characteristics, VCC = VCCO = 2.5V ± 5%, VEE =0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VOH
Output High Voltage; NOTE 1
VCCO – 1.4
VCCO – 0.9
V
VOL
Output Low Voltage; NOTE 1
VCCO – 2.0
VCCO – 1.5
V
VSWING
Peak-to-Peak Output Voltage Swing
0.4
1.0
V
NOTE 1: Outputs termination with 50 to VCCO – 2V.
Table 4. Crystal Characteristics
Parameter
Test Conditions
Mode of Oscillation
Minimum
Typical
Maximum
Units
Fundamental
Frequency
25
MHz
Equivalent Series Resistance (ESR)
50
Shunt Capacitance
7
pF
NOTE: Characterized using an 18pF parallel resonant crystal.
©2016 Integrated Device Technology, Inc
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January 18, 2016
843004I-01 Data Sheet
AC Electrical Characteristics
Table 5A. AC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE =0V, TA = -40°C to 85°C
Symbol
Parameter
fOUT
Output Frequency Range
tsk(o)
Output Skew; NOTE 1, 2
tjit(Ø)
RMS Phase Jitter, (Random);
NOTE 3
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Test Conditions
Minimum
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10
Typical
Maximum
Units
140
170
MHz
112
136
MHz
56
68
MHz
50
ps
156.25MHz, (1.875MHz – 20MHz)
0.54
ps
125MHz, (1.875MHz – 20MHz)
0.58
ps
62.5MHz, (637kHz – 10MHz)
0.70
ps
20% to 80%
300
600
ps
48
52
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plots.
Table 5B. AC Characteristics, VCC = VCCO = 2.5V ± 5%, VEE =0V, TA = -40°C to 85°C
Symbol
Parameter
fOUT
Output Frequency Range
tsk(o)
Output Skew; NOTE 1, 2
tjit(Ø)
RMS Phase Jitter, (Random);
NOTE 3
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Test Conditions
Minimum
F_SEL[1:0] = 00
Typical
Maximum
Units
140
170
MHz
F_SEL[1:0] = 01
112
136
MHz
F_SEL[1:0] = 10
56
68
MHz
50
ps
156.25MHz, (1.875MHz – 20MHz)
0.54
ps
125MHz, (1.875MHz – 20MHz)
0.58
ps
62.5MHz, (637kHz – 10MHz)
20% to 80%
0.74
ps
300
600
ps
48
52
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plots.
©2016 Integrated Device Technology, Inc
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January 18, 2016
843004I-01 Data Sheet
➝
Typical Phase Noise at 156.25MHz (3.3V)
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.54ps (typical)
Noise Power dBc
10Gb Ethernet Filter
➝
➝
Raw Phase Noise Data
Phase Noise Result by adding a
10Gb Ethernet filter to raw data
Offset Frequency (Hz)
©2016 Integrated Device Technology, Inc
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January 18, 2016
843004I-01 Data Sheet
➝
Typical Phase Noise at 62.5MHz (3.3V)
62.5MHz
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.70ps (typical)
Noise Power dBc
Hz
Fibre Channel Filter
➝
➝
Raw Phase Noise Data
Phase Noise Result by adding a
Fibre Channel filter to raw data
Offset Frequency (Hz)
©2016 Integrated Device Technology, Inc
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January 18, 2016
843004I-01 Data Sheet
Parameter Measurement Information
2V
VCC,
VCCA,
VCCO
2V
Qx
SCOPE
VCC,
VCCA,
VCCO
Qx
nQx
SCOPE
nQx
VEE
VEE
--0.5V ± 0.125V
-1.3V
± 0.165V
2.5V LVPECL Output Load AC Test Circuit
3.3V LVPECL Output Load AC Test Circuit
Phase Noise Plot
Noise Power
nQx
Qx
nQy
Phase Noise Mask
Qy
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS Phase Jitter
Output Skew
nQ0:nQ3
nQ0:nQ3
Q0:Q3
Q0:Q3
Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
©2016 Integrated Device Technology, Inc
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January 18, 2016
843004I-01 Data Sheet
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 843004I-01 provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. VCC, VCCA and VCCO should be individually
connected to the power supply plane through vias, and 0.01µF
bypass capacitors should be used for each pin. Figure 1 illustrates
this for a generic VCC pin and also shows that VCCA requires that an
additional 10 resistor along with a 10F bypass capacitor be
connected to the VCCA pin.
3.3V or 2.5V
VCC
.01µF
10Ω
.01µF
10µF
VCCA
Figure 1. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
Crystal Inputs
LVPECL Outputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied
from XTAL_IN to ground.
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
TEST_CLK Input
For applications not requiring the use of the clock, it can be left
floating. Though not required, but for additional protection, a 1k
resistor can be tied from the TEST_CLK to ground.
LVCMOS Control Pins
All control pins have internal pulldowns; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
Crystal Input Interface
The 843004I-01 has been characterized with 18pF parallel resonant
crystals. The capacitor values shown in Figure 2 below were
determined using a 25MHz, 18pF parallel resonant crystal and were
chosen to minimize the ppm error.
XTAL_IN
C1
33pF
X1
18pF Parallel Crystal
XTAL_OUT
C2
27pF
©2016 Integrated Device Technology, Inc
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January 18, 2016
843004I-01 Data Sheet
Figure 2. Crystal Input Interface
Overdriving the XTAL Interface
The XTAL_IN input can be overdriven by an LVCMOS driver or by
one side of a differential driver through an AC coupling capacitor. The
XTAL_OUT pin can be left floating. The amplitude of the input signal
should be between 500mV and 1.8V and the slew rate should not be
less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be
reduced from full swing to at least half the swing in order to prevent
signal interference with the power rail and to reduce internal noise.
Figure 3A shows an example of the interface diagram for a high
speed 3.3V LVCMOS driver. This configuration requires that the sum
of the output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
VCC
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50 applications,
R1 and R2 can be 100. This can also be accomplished by removing
R1 and changing R2 to 50. The values of the resistors can be
increased to reduce the loading for a slower and weaker LVCMOS
driver. Figure 3B shows an example of the interface diagram for an
LVPECL driver. This is a standard LVPECL termination with one side
of the driver feeding the XTAL_IN input. It is recommended that all
components in the schematics be placed in the layout. Though some
components might not be used, they can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a quartz crystal as the input.
XTAL_OUT
R1
100
Ro
Rs
C1
Zo = 50 ohms
XTAL_IN
R2
100
Zo = Ro + Rs
.1uf
LVCMOS Driver
Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_OUT
C2
Zo = 50 ohms
XTAL_IN
.1uf
Zo = 50 ohms
LVPECL Driver
R1
50
R2
50
R3
50
Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface
©2016 Integrated Device Technology, Inc
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January 18, 2016
843004I-01 Data Sheet
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
R3
125
3.3V
R4
125
3.3V
3.3V
Zo = 50
+
_
Input
Zo = 50
R1
84
Figure 4A. 3.3V LVPECL Output Termination
©2016 Integrated Device Technology, Inc
R2
84
Figure 4B. 3.3V LVPECL Output Termination
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January 18, 2016
843004I-01 Data Sheet
Termination for 2.5V LVPECL Outputs
The R3 in Figure 5B can be eliminated and the termination is shown
in Figure 5C.
Figure 5A and Figure 5B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50
to VCC – 2V. For VCC= 2.5V, the VCC– 2V is very close to ground level.
2.5V
VCC = 2.5V
2.5V
2.5V
VCC = 2.5V
R1
250Ω
50Ω
R3
250Ω
+
50Ω
+
50Ω
–
50Ω
2.5V LVPECL Driver
–
R1
50Ω
2.5V LVPECL Driver
R2
62.5Ω
R2
50Ω
R4
62.5Ω
R3
18Ω
Figure 5A. 2.5V LVPECL Driver Termination Example
Figure 5B. 2.5V LVPECL Driver Termination Example
2.5V
VCC = 2.5V
50Ω
+
50Ω
–
2.5V LVPECL Driver
R1
50Ω
R2
50Ω
Figure 5C. 2.5V LVPECL Driver Termination Example
©2016 Integrated Device Technology, Inc
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January 18, 2016
843004I-01 Data Sheet
Layout Guideline
Figure 6 shows a schematic example of the 843004I-01. An example
of LVEPCL termination is shown in this schematic. Additional
LVPECL termination approaches are shown in the LVPECL
Termination Application Note. In this example, an 18pF parallel
resonant 25MHz crystal is used. The C1= 27pF and
C2 = 33pF are recommended for frequency accuracy. For a different
board layout, the C1 and C2 may be slightly adjusted for optimizing
frequency accuracy.
3.3V
VCC
VCCA
R2
10
R3
133
R5
133
Zo = 50 Ohm
C3
10uF
C4
0.01u
+
VCC
VCCO
C6
0.1u
F_SEL1
VCC
F_SEL0
VCCA
NC
nPLL_SEL
MR
nQ0
Q0
VCCO
Q1
nQ1
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
U1
ICS843004-01
-
R4
82.5
XTAL_OUT
XTAL_IN
VEE
TEST_CLK
nXTAL_SEL
VCC
VEE
nQ3
Q3
VCCO
Q2
nQ2
RU1
1K
Set Logic
Input to
'0'
VDD
VCC=3.3V
R6
82.5
3.3V
VCCO=3.3V
R7
133
13
14
15
16
17
18
19
20
21
22
23
24
Set Logic
Input to
'1'
VDD
Zo = 50 Ohm
C7
0.1u
12
11
10
9
8
7
6
5
4
3
2
1
Logic Control Input Examples
R9
133
Zo = 50 Ohm
X1
25MHz
Zo = 50 Ohm
C1
27pF
C9
0.1u
VCCO
F
p
8
1
C2
33pF
VCC
+
R8
82.5
-
R10
82.5
C8
0.1u
Figure 6. 843004I-01 Schematic Example
©2016 Integrated Device Technology, Inc
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843004I-01 Data Sheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 843004I-01.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the 843004I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 130mA = 450.45mW
•
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power_MAX (3.465V, with all outputs switching) = 450.45mW + 120mW = 570.45mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air
flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.570W * 65°C/W = 122°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance JA for 24 Lead TSSOP, Forced Convection
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
©2016 Integrated Device Technology, Inc
0
1
2.5
70°C/W
65°C/W
62°C/W
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January 18, 2016
843004I-01 Data Sheet
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 7.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
Figure 7. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
VCCO – 2V.
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX – VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V
(VCCO_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V – 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
©2016 Integrated Device Technology, Inc
15
January 18, 2016
Reliability Information
Table 7. JA vs. Air Flow Table for a 24 Lead TSSOP
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
70°C/W
65°C/W
62°C/W
Transistor Count
The transistor count for 843004I-01 is: 3183
Package Outline and Package Dimensions
Package Outline - G Suffix for 24 Lead TSSOP
Table 8. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
24
A
1.20
A1
0.5
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
7.70
7.90
E
6.40 Basic
E1
4.30
4.50
e
0.65 Basic
L
0.45
0.75
0°
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
843004I-01 Data Sheet
Ordering Information
Table 9. Ordering Information
Part/Order Number
843004AGI-01LF
843004AGI-01LFT
Marking
ICS43004AI01L
ICS43004AI01L
©2016 Integrated Device Technology, Inc
Package
“Lead-Free” 24 Lead TSSOP
“Lead-Free” 24 Lead TSSOP
17
Shipping Packaging
Tube
Tape & Reel
Temperature
-40C to 85C
-40C to 85C
January 18, 2016
843004I-01 Data Sheet
Revision History Sheet
Rev
Table
Page
T3E
Added 2.5V LVPECL DC Characteristics Table.
Added LVCMOS to XTAL Interface section.
Ordering Information Table - added Lead-Free marking.
4/22/09
T9
4
10
17
T1
T3D, T3E
2
4
8/11/09
T9
10
14
17
Pin Description Table - revised pin 7 description.
LVPECL Tables - corrected VOH/VOL Parameter rows from current to voltage and
corrected units from µA to V.
LVCMOS to XTAL Interface section - added sentence to end.
Power Considerations, 2. Junction Temperature - reworded sentence.
Ordering Information Table - corrected Temperature column from -30 to -40.
Updated header/footer of datasheet.
6
156.25MHz Phase Noise Plot - corrected filter from Fibre Channel to 10Gb Ethernet and
corrected typo 1.875MHz from 1.875MkHz.
1/26/10
T9
10
17
Updated Overdriving the XTAL Interface application note.
Ordering Information Table - corrected LF marking.
3/24/11
T9
17
Removed leaded orderable parts from the Ordering Information table.
11/14/12
T9
17
Removed ICS from part the part number where needed.
Ordering Information - removed quantity from tape and reel. Deleted LF note below the
table.
Updated header and footer.
1/18/16
B
B
B
B
B
B
Description of Change
©2016 Integrated Device Technology, Inc
Date
18
January 18, 2016
843004I-01 Data Sheet
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