843004AG-01LF

843004-01 Femtoclocks® Crystal-to-3.3V LVPECL Frequency Synthesizer Data Sheet GENERAL DESCRIPTION FEATURES The 843004-01 is a 4 output LVPECL synthesizer optimized to generate Ethernet reference clock frequencies and is a member of the family of high performance clock solutions from IDT. Using a 25MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the settings of 2 frequency select pins (F_SEL[1:0]): 156.25MHz, 125MHz, 62.5MHz. The 843004-01 uses IDT’s 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The 843004-01 is packaged in a small 24-pin TSSOP package. • Four 3.3V LVPECL outputs • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input • Supports the following output frequencies: 156.25MHz, 125MHz and 62.5MHz • VCO range: 560MHz - 680MHz • RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.57ps (typical) • RMS phase noise at 156.25MHz (typical) Phase noise: Offset Noise Power 100Hz ................-95.5 dBc/Hz 1kHz .................-118 dBc/Hz 10kHz .................-126 dBc/Hz 100kHz ..............-126.6 dBc/Hz • Full 3.3V supply mode • -30°C to 85°C ambient operating temperature • Available in lead-free RoHS compliant package FREQUENCY SELECT FUNCTION TABLE Inputs PIN ASSIGNMENT Output Frequency (25MHz Ref.) F_SEL1 F_SEL0 M Divider Value N Divider Value M/N Divider Value 0 0 25 4 6.25 156.25 0 1 25 5 5 125 1 0 25 10 2.5 62.5 1 1 25 not used nQ1 Q1 VCCo Q0 nQ0 MR nPLL_SEL nc VCCA F_SEL0 VCC F_SEL1 not used BLOCK DIAGRAM F_SEL[1:0] Pulldown nPLL_SEL TEST_CLK 2 1 1 25MHz XTAL_IN OSC 0 Phase Detector XTAL_OUT nXTAL_SEL 24 23 22 21 20 19 18 17 16 15 14 13 nQ2 Q2 VCCO Q3 nQ3 VEE VCC nXTAL_SEL TEST_CLK VEE XTAL_IN XTAL_OUT 843004-01 Pulldown Pulldown 1 2 3 4 5 6 7 8 9 10 11 12 VCO 625MHz (w/25MHz Reference) 0 Pulldown F_SEL[1:0] Q0 0 0 ÷4 0 1 ÷5 1 0 ÷10 1 1 not used nQO Q1 24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Top View nQ1 Q2 nQ2 M = 25 (fixed) Q3 nQ3 MR Pulldown ©2016 Integrated Device Technology, Inc 1 Revision B January 18, 2016 843004-01 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type 1, 2 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 3, 22 VCCO Power Output supply pins. 4, 5 Q0, nQ0 Ouput Differential output pair. LVPECL interface levels. 6 MR Input 7 nPLL_SEL Input Description Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Selects between the PLL and TEST_CLK as input to the dividers. When LOW, Pulldown selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. 8 nc Unused 9 VCCA Power No connect. 10, 12 F_SEL0, F_SEL1 Input 11, 18 VCC Power Core supply pin. 13, 14 XTAL_OUT, XTAL_IN Input Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. 15, 19 VEE Power Negative supply pins. 16 TEST_CLK Input Pulldown LVCMOS/LVTTL clock input. 17 nXTAL_SEL Input Selects between crystal or TEST_CLK inputs as the the PLL Reference Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH. LVCMOS/LVTTL interface levels. 20, 21 nQ3, Q3 Output Differential output pair. LVPECL interface levels. 23, 24 Q2, nQ2 Output Differential output pair. LVPECL interface levels. Analog supply pin. Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. NOTE: refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Pulldown TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 kΩ ©2016 Integrated Device Technology, Inc Test Conditions Minimum 2 Typical Maximum Units Revision B January 18, 2016 843004-01 Data Sheet ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 70°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -30°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 135 mA ICCA Analog Supply Current 15 mA Included in IEE TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -30°C TO 85°C Symbol Parameter VIH Input High Voltage nPLL_SEL, nXTAL_SEL, Input F_SEL0, F_SEL1, MR Low Voltage TEST_CLK TEST_CLK, MR, nPLL_ Input SEL, nXTAL_SEL, F_SEL0, High Current F_SEL1 TEST_CLK, MR, nPLL_ Input SEL, nXTAL_SEL, F_SEL0, Low Current F_SEL1 VIL IIH IIL Test Conditions Minimum Maximum Units 2 Typical VCC + 0.3 V -0.3 0.8 V -0.3 1.3 V 150 µA VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V -5 µA TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -30°C TO 85°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCCO - 1.4 Typical VCCO - 0.9 V VOL Output Low Voltage; NOTE 1 VCCO - 2.0 VCCO - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50 to VCCO - 2V. Ω ©2016 Integrated Device Technology, Inc 3 Revision B January 18, 2016 843004-01 Data Sheet TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF NOTE: Characterized using an 18pF parallel resonant crystal. TABLE 5. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -30°C TO 85°C Symbol fOUT tsk(o) tjit(Ø) tR / tF Parameter Output Frequency Test Conditions Minimum Maximum Units F_SEL[1:0] = 00 140 Typical 170 MHz F_SEL[1:0] = 01 112 136 MHz F_SEL[1:0] =10 56 68 MHz 30 ps Output Skew; NOTE 1, 2 RMS Phase Jitter; NOTE 3 Output Rise/Fall Time 156.25MHz (1.875MHz - 20MHz) 0.57 ps 125MHz (1.875MHz - 20MHz) 0.63 ps 62.5MHz (1.875MHz - 20MHz) 0.81 ps 20% to 80% 300 odc Output Duty Cycle 49 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VCCO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Phase jitter is dependent on the input source used. ©2016 Integrated Device Technology, Inc 4 600 ps 51 % Revision B January 18, 2016 843004-01 Data Sheet TYPICAL PHASE NOISE AT 62.5MHZ ➤ 0 -10 -20 -30 10Gb Ethernet Filter -40 62.5MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.81ps (typical) -60 -70 -80 -90 -100 Raw Phase Noise Data -110 ➤ NOISE POWER dBc Hz -50 -120 -130 -140 -150 -160 -170 ➤ -180 -190 100 1k 10k Phase Noise Result by adding 10Gb Ethernet Filter to raw data 100k 1M 10M 100M OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 125MHZ ➤ 0 -10 -20 10Gb Ethernet Filter -30 -40 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.63ps (typical) -60 -70 -80 -90 Raw Phase Noise Data -100 -110 ➤ NOISE POWER dBc Hz -50 -120 -130 -140 -150 -160 ➤ -170 -180 -190 100 1k Phase Noise Result by adding 10Gb Ethernet Filter to raw data 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) ©2016 Integrated Device Technology, Inc 5 Revision B January 18, 2016 843004-01 Data Sheet TYPICAL PHASE NOISE AT 156.25MHZ ➤ 0 -10 -20 10Gb Ethernet Filter -30 -40 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.57ps (typical) -60 -70 -80 -90 -100 Raw Phase Noise Data -110 ➤ NOISE POWER dBc Hz -50 -120 -130 -140 -150 -160 ➤ -170 -180 -190 100 1k 10k Phase Noise Result by adding 10Gb Ethernet Filter to raw data 100k 1M 10M 100M OFFSET FREQUENCY (HZ) ©2016 Integrated Device Technology, Inc 6 Revision B January 18, 2016 843004-01 Data Sheet PARAMETER MEASUREMENT INFORMATION 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW RMS PHASE JITTER OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD ©2016 Integrated Device Technology, Inc 7 Revision B January 18, 2016 843004-01 Data Sheet APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 843004-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC, V CCA, and V CCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01μF bypass capacitor should be connected to each VCCA. 3.3V VCC .01μF 10Ω VCCA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kW resistor can be tied from XTAL_IN to ground. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. TEST_CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the TEST_CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. CRYSTAL INPUT INTERFACE determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The 843004-01 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were Figure 2. CRYSTAL INPUt INTERFACE ©2016 Integrated Device Technology, Inc 8 Revision B January 18, 2016 843004-01 Data Sheet LVCMOS TO XTAL INTERFACE The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure X. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. VDD VDD R1 Ro Rs .1uf Zo = 50 XTAL_IN R2 Zo = Ro + Rs XTAL_OUT FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE TERMINATION FOR 3.3V LVPECL OUTPUT lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission FIGURE 4A. LVPECL OUTPUT TERMINATION ©2016 Integrated Device Technology, Inc FIGURE 4B. LVPECL OUTPUT TERMINATION 9 Revision B January 18, 2016 843004-01 Data Sheet LAYOUT GUIDELINE resonant 25MHz crystal is used. The C1=27pF and C2=33pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. Figure 5 shows a schematic example of the 843004-01. An example of LVEPCL termination is shown in this schematic. Additional LVPECL termination approaches are shown in the LVPECL Termination Application Note. In this example, an 18pF parallel 3.3V VCC VCCA R2 10 C3 10uF Zo = 50 Ohm C4 0.01u VCCO C6 0.1u 12 11 10 9 8 7 6 5 4 3 2 1 F_SEL1 VCC F_SEL0 VCCA NC nPLL_SEL MR nQ0 Q0 VCCO Q1 nQ1 RU2 Not Install To Logic Input pins RD1 Not Install To Logic Input pins RD2 1K Zo = 50 Ohm U1 ICS843004-01 - R4 82.5 XTAL_OUT XTAL_IN VEE TEST_CLK nXTAL_SEL VCC VEE nQ3 Q3 VCCO Q2 nQ2 RU1 1K Set Logic Input to '0' VDD C7 0.1u VCC=3.3V R6 82.5 3.3V VCCO=3.3V 13 14 15 16 17 18 19 20 21 22 23 24 Set Logic Input to '1' VDD R5 133 + VCC Logic Control Input Examples R3 133 Zo = 50 Ohm R7 133 R9 133 X1 25MHz 18pF Zo = 50 Ohm C9 0.1u C1 27pF VCCO C2 33pF VCC + R8 82.5 - R10 82.5 C8 0.1u FIGURE 5. 843004-01 SCHEMATIC EXAMPLE ©2016 Integrated Device Technology, Inc 10 Revision B January 18, 2016 843004-01 Data Sheet POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the 843004-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 843004-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 135mA = 467.8mW • Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30mW = 120mW Total Power_MAX (3.465V, with all outputs switching) = 467.8mW + 120mW = 587.8mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.588W * 65°C/W = 123.2°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 24-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards ©2016 Integrated Device Technology, Inc 11 0 1 2.5 70°C/W 65°C/W 62°C/W Revision B January 18, 2016 843004-01 Data Sheet 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCC- 2V. • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V (VCCO_MAX - VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V (VCCO_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX - 2V))/RL] * (VCC_MAX - VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX))/RL] * (VCC_MAX - VOH_MAX) = [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCC_MAX - 2V))/RL] * (VCC_MAX - VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX))/RL] * (VCC_MAX - VOL_MAX) = [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW ©2016 Integrated Device Technology, Inc 12 Revision B January 18, 2016 843004-01 Data Sheet RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 70°C/W 65°C/W 62°C/W TRANSISTOR COUNT The transistor count for 843004-01 is: 3183 ©2016 Integrated Device Technology, Inc 13 Revision B January 18, 2016 843004-01 Data Sheet PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 24 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 E E1 7.90 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 ©2016 Integrated Device Technology, Inc 14 Revision B January 18, 2016 843004-01 Data Sheet TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 843004AG-01LF ICS43004A01L 24 Lead “Lead-Free” TSSOP tube -30°C to 85°C 843004AG-01LFT ICS43004A01L 24 Lead “Lead-Free” TSSOP tape & reel -30°C to 85°C ©2016 Integrated Device Technology, Inc 15 Revision B January 18, 2016 843004-01 Data Sheet REVISION HISTORY SHEET Rev Table B T5 4 AC Characteristics Table - deleted Propagation Delay row. T9 1 9 15 T9 15 T9 1 15 Features Section - added lead-free bullet. Added - LVCMOS to XTAL Interface and Recommendations for Unused Input and Output Pins sections. Ordering Information Table - added lead-free part number, marking and note. Ordering Information Table - removed leaded devices - PDN CQ-13-02 expired. Updated datasheet format. General Description - Removed Hiperclocks and changed ICS to IDT. Ordering Information - Removed ICS in the Part/Order number and removed LF note below the table. Updated data sheet header and footer. B B B Page Description of Change ©2016 Integrated Device Technology, Inc 16 Date 5/6/05 6/30/06 12/9/14 1/18/16 Revision B January 18, 2016 843004-01 Data Sheet Corporate Headquarters 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. 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