843004AG-125LFT

843004-125 FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer Data Sheet GENERAL DESCRIPTION FEATURES T h e 8 4 3 0 0 4 - 1 2 5 i s a 4 o u t p u t LV P E C L S y n t h e s i z e r o p t i m i z e d t o g e n e r a t e E t h e r n e t r e fe r e n c e clock frequencies and is a member of the family of high performance clock solutions from IDT. The 843004-125 uses IDT’s 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The 843004-125 is packaged in a small 24-pin TSSOP package. • Four 3.3V LVPECL output pairs • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input • Crystal oscillator designed for 25MHz, 18pF parallel resonant crystal • Supports the following output frequency: 125MHz • VCO range: 560MHz - 680MHz • RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.58ps (typical) • Full 3.3V supply mode • 0°C to 70°C ambient operating temperature • Available in lead-free (RoHS 6) package FREQUENCY SELECT FUNCTION TABLE Inputs M Divider Value N Divider Value M/N Divider Value Output Frequency (MHz) (25MHz Ref.) 25 5 5 125 BLOCK DIAGRAM PIN ASSIGNMENT Q0 nPLL_SEL Pulldown nQ0 Q1 REF_CLK Pulldown XTAL_IN 1 25MHz OSC 0 nQ1 1 Phase Detector XTAL_OUT VCO 625MHz (w/25MHz Reference) ÷5 0 Q2 nQ2 nXTAL_SEL Pulldown Q3 nQ3 M = 25 (fixed) MR Pulldown ©2016 Integrated Device Technology, Inc 1 nQ1 Q1 VCCo Q0 nQ0 MR nPLL_SEL nc VCCA nc VCC nc 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 nQ2 Q2 VCCO Q3 nQ3 VEE VCC nXTAL_SEL REF_CLK VEE XTAL_IN XTAL_OUT 843004-125 24-Lead TSSOP 4.40mm x 7.8mm x 0.925mm package body G Package Top View January 18, 2016 843004-125 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type 1, 2 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 3, 22 VCCO Power Output supply pins. 4, 5 Q0, nQ0 Ouput Differential output pair. LVPECL interface levels. 6 MR Input 7 nPLL_SEL Input Description Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx to go high. When logic Pulldown LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Selects between the PLL and REF_CLK as input to the dividers. When LOW, selects Pulldown PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. 8, 10, 12 nc Unused 9 VCCA Power Analog supply pin. No connect. 11, 18 VCC Power Core supply pins. 13, 14 XTAL_OUT, XTAL_IN Input Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. 15, 19 VEE Power Negative supply pins. 16 REF_CLK Input Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels. 17 nXTAL_SEL Input Selects between crystal or REF_CLK inputs as the the PLL Reference source. Selects Pulldown XTAL inputs when LOW. Selects REF_CLK when HIGH. LVCMOS/LVTTL interface levels. 20, 21 nQ3, Q3 Output Differential output pair. LVPECL interface levels. 23, 24 Q2, nQ2 Output Differential output pair. LVPECL interface levels. NOTE: refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Pulldown TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 kΩ ©2016 Integrated Device Technology, Inc Test Conditions 2 Minimum Typical Maximum Units January 18, 2016 843004-125 Data Sheet ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 82.3°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, V = 0V, TA = 0°C TO 70°C EE Symbol Parameter Test Conditions VCC Core Supply Voltage Minimum Typical Maximum Units 3.135 3.3 3.465 V VCCA Analog Supply Voltage VCC – 0.15 3.3 VCC V VCCO Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current ICCA Analog Supply Current Included in IEE 130 mA 15 mA TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, V = 0V, TA = 0°C TO 70°C EE Symbol Parameter Test Conditions Maximum Units VIH Input High Voltage Minimum 2 Typical VCC + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current REF_CLK, MR, nPLL_ SEL, nXTAL_SEL VCC = VIN = 3.465V 150 µA IIL Input Low Current REF_CLK, MR, nPLL_ SEL, nXTAL_SEL VCC = 3.465V, VIN = 0V -5 µA TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, V = 0V, TA = 0°C TO 70°C EE Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 VCCO - 1.4 VCCO - 0.9 V VOL Output Low Voltage; NOTE 1 VCCO - 2.0 VCCO - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. ©2016 Integrated Device Technology, Inc 3 January 18, 2016 843004-125 Data Sheet TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF NOTE: Characterized using an 18pF, parallel resonant crystal. TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, V = 0V, TA = 0°C TO 70°C EE Symbol Parameter fOUT Output Frequency tsk(o) Output Skew; NOTE 1, 2 tjit(Ø) RMS Phase Jitter; NOTE 3 tR / tF Output Rise/Fall Time Test Conditions Minimum Typical Maximum Units 112 125 136 MHz 50 ps 125MHz (1.875MHz - 20MHz) 20% to 80% 0.58 300 ps 600 ps odc Output Duty Cycle 48 52 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditons. NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Phase jitter is dependent on the input source used. ©2016 Integrated Device Technology, Inc 4 January 18, 2016 843004-125 Data Sheet ➤ TYPICAL PHASE NOISE AT 125MHZ NOISE POWER dBc Hz 10Gb Ethernet Filter 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.58ps (typical) Raw Phase Noise Data ➤ ➤ Phase Noise Result by adding 10Gb Ethernet Filter to raw data OFFSET FREQUENCY (HZ) ©2016 Integrated Device Technology, Inc 5 January 18, 2016 843004-125 Data Sheet PARAMETER MEASUREMENT INFORMATION 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW RMS PHASE JITTER OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD ©2016 Integrated Device Technology, Inc 6 January 18, 2016 843004-125 Data Sheet APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 843004-125 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA and V CCO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional10Ω resistor along with a 10µF bypass capacitor be connected to the VCCA pin. 3.3V VCC .01μF 10Ω VCCA .01μF 10 μF FIGURE 1. POWER SUPPLY FILTERING RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: LVPECL OUTPUTS INPUTS: All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. CRYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kW resistor can be tied from XTAL_IN to ground. REF_CLK INPUT For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the REF_CLK to ground. LVCMOS CONTROL PINS All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. CRYSTAL INPUT INTERFACE were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The 843004-125 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below FIGURE 2. CRYSTAL INPUT INTERFACE ©2016 Integrated Device Technology, Inc 7 January 18, 2016 843004-125 Data Sheet LVCMOS TO XTAL INTERFACE The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3 The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. VDD VDD R1 Ro Rs .1uf Zo = 50 XTAL_IN R2 Zo = Ro + Rs XTAL_OUT FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE TERMINATION FOR 3.3V LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission R3 125 3.3V R4 125 3.3V 3.3V Zo = 50 + _ Input Zo = 50 R1 84 FIGURE 4A. LVPECL OUTPUT TERMINATION ©2016 Integrated Device Technology, Inc R2 84 FIGURE 4B. LVPECL OUTPUT TERMINATION 8 January 18, 2016 843004-125 Data Sheet LAYOUT GUIDELINE board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. Two examples of LVPECL terminations are shown in this schematic. Additional termination approaches are shown in the LVPECL Termination Application Note. Figure 5 shows an example of 843004-125 application schematic. In this example, the device is operated at VCC = VCCO = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The C1= 33pF and C2 = 27pF are recommended for frequency accuracy. For different MR nPLL_SEL VCC VCCA R1 10 3.3V C5 10uF C6 0.01u VCCO Logic Control Input Examples + C4 0.1uF C3 0.1uF RU2 Not Install To Logic Input pins - RD2 1K R4 82.5 R5 82.5 VCC=3.3V VCCO=3.3V 13 14 15 16 17 18 19 20 21 22 23 24 RD1 Not Install XTAL_OUT XTAL_IN VEE REF_CLK nXTAL_SEL VCC VEE nQ3 Q3 VCCO Q2 nQ2 To Logic Input pins Zo = 50 Ohm U1 nc VCC nc VCCA nc nPLL_SEL MR nQ0 Q0 VCCO Q1 nQ1 RU1 1K R3 133 VCC Set Logic Input to '0' VDD R2 133 12 11 10 9 8 7 6 5 4 3 2 1 Set Logic Input to '1' VDD Zo = 50 Ohm Zo = 50 Ohm + C1 33pF X1 25MHz 18pF VCC C7 0.1uF Q1 R9 VCCO C2 27pF Ro ~ 7 Ohm Zo = 50 Ohm VCC R6 50 VCCO C8 0.1uF Zo = 50 Ohm Optional Y-Termination R7 50 R8 50 43 Driv er_LVCMOS nXTAL_SEL FIGURE 5. ICS843004-01 SCHEMATIC EXAMPLE ©2016 Integrated Device Technology, Inc 9 January 18, 2016 843004-125 Data Sheet POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the 843004-125. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 843004-125 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 130mA = 450.45mW • Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30mW = 120mW Total Power_MAX (3.465V, with all outputs switching) = 450.45mW + 120mW = 570.45mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 82.3°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.570W * 82.3°C/W = 116.9°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 24-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) 0 Multi-Layer PCB, JEDEC Standard Test Boards ©2016 Integrated Device Technology, Inc 82.3°C/W 10 1 2.5 78.0°C/W 75.9°C/W January 18, 2016 843004-125 Data Sheet 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCC- 2V. • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V (VCCO_MAX - VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V (VCCO_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX - 2V))/RL] * (VCC_MAX - VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX))/RL] * (VCC_MAX - VOH_MAX) = [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCC_MAX - 2V))/RL] * (VCC_MAX - VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX))/RL] * (VCC_MAX - VOL_MAX) = [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW ©2016 Integrated Device Technology, Inc 11 January 18, 2016 843004-125 Data Sheet RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP θJA by Velocity (Meters per Second) 0 Multi-Layer PCB, JEDEC Standard Test Boards 82.3°C/W 1 2.5 78.0°C/W 75.9°C/W TRANSISTOR COUNT The transistor count for 843004-125 is: 2894 PACKAGE OUTLINE AND DIMENSIONS PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 24 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 ©2016 Integrated Device Technology, Inc 12 January 18, 2016 843004-125 Data Sheet TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 843004AG-125LF ICS43004A125L 24 Lead “Lead-Free” TSSOP tube 0°C to 70°C 843004AG-125LFT ICS43004A125L 24 Lead “Lead-Free” TSSOP tape & reel 0°C to 70°C ©2016 Integrated Device Technology, Inc 13 January 18, 2016 843004-125 Data Sheet REVISION HISTORY SHEET Rev A Table T9 Page 1 13 Description of Change Removed ICS from the part number where needed. General Description - Removed ICS Chip and Hiperclocks. Ordering Information - Removed quantity from tape and reel. Deleted LF note below the table. Updated Header and footer. ©2016 Integrated Device Technology, Inc 14 Date 1/18/16 January 18, 2016 843004-125 Data Sheet Corporate Headquarters 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. 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