843004AG-125LF

FemtoClock™ Crystal-to-3.3V LVPECL Frequency Synthesizer ICS843004-125 ADVANCE INFORMATION DATA SHEET GENERAL DESCRIPTION The ICS843004-125 is a 4 output LVPECL SynIC S thesizer optimized to generate Ethernet reference HiPerClockS™ clock frequencies and is a member of the HiPerClocks TM family of high performance clock solutions from IDT. The ICS843004-125 uses IDT’s 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The ICS843004-125 is packaged in a small 24-pin TSSOP package. FEATURES • Four 3.3V LVPECL output pairs • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input • Crystal oscillator designed for 25MHz, 18pF parallel resonant crystal • Supports the following output frequency: 125MHz • VCO range: 560MHz - 680MHz • RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.58ps (typical) • Full 3.3V supply mode • 0°C to 70°C ambient operating temperature • Available in lead-free (RoHS 6) package FREQUENCY SELECT FUNCTION TABLE Inputs M Divider Value 25 N Divider Value 5 M/N Divider Value 5 Output Frequency (MHz) (25MHz Ref.) 125 BLOCK DIAGRAM Q0 nPLL_SEL Pulldown nQ0 Q1 REF_CLK Pulldown 25MHz PIN ASSIGNMENT nQ1 Q1 VCCo Q0 nQ0 MR nPLL_SEL nc VCCA nc VCC nc 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 nQ2 Q2 VCCO Q3 nQ3 VEE VCC nXTAL_SEL REF_CLK VEE XTAL_IN XTAL_OUT 1 1 nQ1 XTAL_IN OSC XTAL_OUT nXTAL_SEL Pulldown 0 Phase Detector VCO 625MHz (w/25MHz Reference) ÷5 0 Q2 nQ2 Q3 M = 25 (fixed) nQ3 ICS843004-125 24-Lead TSSOP 4.40mm x 7.8mm x 0.925mm package body G Package Top View MR Pulldown ICS843004AG-125 REVISION A JUNE 3, 2009 1 ©2009 Integrated Device Technology, Inc. ICS43004-125 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number 1, 2 3, 22 4, 5 6 Name nQ1, Q1 VCCO Q0, nQ0 MR Type Output Power Ouput Input Description Differential output pair. LVPECL interface levels. Output supply pins. Differential output pair. LVPECL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx to go high. When logic Pulldown LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Selects between the PLL and REF_CLK as input to the dividers. When LOW, selects Pulldown PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. No connect. Analog supply pin. Core supply pins. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the input. Negative supply pins. Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels. Selects between cr ystal or REF_CLK inputs as the the PLL Reference source. Pulldown Selects XTAL inputs when LOW. Selects REF_CLK when HIGH. LVCMOS/LVTTL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. 7 8, 10, 12 9 11, 18 13, 14 15, 19 16 17 20, 21 23, 24 nPLL_SEL nc VCCA VCC XTAL_OUT, XTAL_IN VEE REF_CLK nXTAL_SEL nQ3, Q3 Q2, nQ2 Input Unused Power Power Input Power Input Input Output Output NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN RPULLDOWN Parameter Input Capacitance Input Pulldown Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF kΩ ICS843004AG-125 REVISION A JUNE 3, 2009 2 ©2009 Integrated Device Technology, Inc. ICS43004-125 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG 4.6V -0.5V to VCC + 0.5V 50mA 100mA -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 82.3°C/W (0 mps) TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, V = 0V, TA = 0°C TO 70°C EE Symbol VCC VCCA VCCO IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 VCC – 0.15 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 VCC 3.465 130 15 Units V V V mA mA Included in IEE TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, V = 0V, TA = 0°C TO 70°C EE Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current REF_CLK, MR, nPLL_SEL, nXTAL_SEL REF_CLK, MR, nPLL_SEL, nXTAL_SEL Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 150 Units V V µA µA VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V -5 TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, V = 0V, TA = 0°C TO 70°C EE Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1.0 Units V V V NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. ICS843004AG-125 REVISION A JUNE 3, 2009 3 ©2009 Integrated Device Technology, Inc. ICS43004-125 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 4. CRYSTAL CHARACTERISTICS Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance NOTE: Characterized using an 18pF, parallel resonant crystal. Test Conditions Minimum Typical Fundamental 25 50 7 MHz Ω pF Maximum Units TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, V = 0V, TA = 0°C TO 70°C EE Symbol fOUT Parameter Output Frequency Output Skew; NOTE 1, 2 RMS Phase Jitter; NOTE 3 Output Rise/Fall Time Test Conditions Minimum 112 Typical 125 0.58 Maximum 136 50 Units MHz ps ps ps tsk(o) tjit(Ø) tR / tF 125MHz (1.875MHz - 20MHz) 20% to 80% 300 600 odc Output Duty Cycle 48 52 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditons. NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Phase jitter is dependent on the input source used. ICS843004AG-125 REVISION A JUNE 3, 2009 4 ©2009 Integrated Device Technology, Inc. ICS43004-125 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 125MHZ ➤ 10Gb Ethernet Filter NOISE POWER dBc Hz 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.58ps (typical) Raw Phase Noise Data OFFSET FREQUENCY (HZ) ➤ ➤ Phase Noise Result by adding 10Gb Ethernet Filter to raw data ©2009 Integrated Device Technology, Inc. ICS843004AG-125 REVISION A JUNE 3, 2009 5 ICS43004-125 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 2V 2V nQx Qx nQy VCC, VCCO Qx SCOPE VCCA LVPECL nQx VEE Qy t sk(o) -1.3V±0.165V 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW Phase Noise Plot Noise Power nQ0:nQ3 Phase Noise Mask 80% 80% VSW I N G f1 Offset Frequency f2 Q0:Q3 20% tR tF 20% RMS Jitter = Area Under the Masked Phase Noise Plot RMS PHASE JITTER OUTPUT RISE/FALL TIME nQ0:nQ3 Q0:Q3 t PW t PERIOD odc = t PW t PERIOD x 100% OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD ICS843004AG-125 REVISION A JUNE 3, 2009 6 ©2009 Integrated Device Technology, Inc. ICS43004-125 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS843004-125 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA and VCCO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional10Ω resistor along with a 10µF bypass capacitor be connected to the VCCA pin. 3.3V VCC .01μF VCCA .01μF 10 μF 10Ω FIGURE 1. POWER SUPPLY FILTERING RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: CRYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kW resistor can be tied from XTAL_IN to ground. REF_CLK INPUT For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the REF_CLK to ground. LVCMOS CONTROL PINS All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. OUTPUTS: LVPECL OUTPUTS All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. CRYSTAL INPUT INTERFACE The ICS843004-125 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p FIGURE 2. CRYSTAL INPUT INTERFACE ICS843004AG-125 REVISION A JUNE 3, 2009 7 ©2009 Integrated Device Technology, Inc. ICS43004-125 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER LVCMOS TO XTAL INTERFACE The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3 The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VDD impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100 Ω . This can also be accomplished by removing R1 and making R2 50Ω. VDD R1 Ro Rs Zo = 50 .1uf XTAL_IN Zo = Ro + Rs R2 XTAL_OUT FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE TERMINATION FOR 3.3V LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 Ω t ransmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. F igures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. R3 125Ω 3.3V + 3.3V 3.3V 3.3V Zo = 50Ω R4 125Ω 3.3V + Zo = 50Ω _ LVPECL Zo = 50Ω R1 50Ω RTT = 1 * Zo ((VOH + VOL) / (VCC – 2)) – 2 R2 50Ω VCC - 2V RTT Input _ LVPECL Zo = 50Ω R1 84Ω R2 84Ω Input FIGURE 4A. LVPECL OUTPUT TERMINATION FIGURE 4B. LVPECL OUTPUT TERMINATION ICS843004AG-125 REVISION A JUNE 3, 2009 8 ©2009 Integrated Device Technology, Inc. ICS43004-125 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER LAYOUT GUIDELINE Figure 5 s hows an example of ICS843004-125 application schematic. In this example, the device is operated at VCC = VCCO = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The C1= 33pF and C2 = 27pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. Two examples of LVPECL terminations are shown in this schematic. Additional termination approaches are shown in the LVPECL Termination Application Note. MR nPLL_SEL VCC VCCA R1 10 3.3V C5 10uF C6 0.01u VCCO Zo = 50 Ohm R2 133 R3 133 Logic Control Input Examples VDD VCC C4 0.1uF 12 11 10 9 8 7 6 5 4 3 2 1 C3 0.1uF U1 Zo = 50 Ohm + Set Logic Input to '1' RU1 1K VDD Set Logic Input to '0' RU2 Not Install - RD1 Not Install RD2 1K XTAL_OUT XTAL_IN VEE REF_CLK nXTAL_SEL VCC VEE nQ3 Q3 VCCO Q2 nQ2 To Logic Input pins To Logic Input pins nc VCC nc VCCA nc nPLL_SEL MR nQ0 Q0 VCCO Q1 nQ1 R4 82.5 R5 82.5 VCC=3.3V VCCO=3.3V 13 14 15 16 17 18 19 20 21 22 23 24 Zo = 50 Ohm + Zo = 50 Ohm C1 33pF VCC Q1 Ro ~ 7 Ohm R9 43 Driv er_LVCMOS nXTAL_SEL Zo = 50 Ohm X1 25MHz8 p F 1 VCC VCCO VCCO C2 27pF C7 0.1uF C8 0.1uF R6 50 R7 50 - Optional Y-Termination R8 50 FIGURE 5. ICS843004-01 SCHEMATIC EXAMPLE ICS843004AG-125 REVISION A JUNE 3, 2009 9 ©2009 Integrated Device Technology, Inc. ICS43004-125 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS843004-125. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843004-125 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 130mA = 450.45mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30mW = 120mW Total Power_MAX (3.465V, with all outputs switching) = 450.45mW + 120mW = 570.45mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 82.3°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.570W * 82.3°C/W = 116.9°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 24-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) 0 Multi-Layer PCB, JEDEC Standard Test Boards 82.3°C/W 1 78.0°C/W 2.5 75.9°C/W ICS843004AG-125 REVISION A JUNE 3, 2009 10 ©2009 Integrated Device Technology, Inc. ICS43004-125 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V (VCCO_MAX - VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V (VCCO_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX - 2V))/R ] * (VCC_MAX - VOH_MAX) = [(2V - (V L CC_MAX - VOH_MAX))/R ] * (VCC_MAX - VOH_MAX) = L [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCC_MAX - 2V))/R ] * (VCC_MAX - VOL_MAX) = [(2V - (V _MAX - VOL_MAX))/R ] * (VCC_MAX - VOL_MAX) = L CC L [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW ICS843004AG-125 REVISION A JUNE 3, 2009 11 ©2009 Integrated Device Technology, Inc. ICS43004-125 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP θJA by Velocity (Meters per Second) 0 Multi-Layer PCB, JEDEC Standard Test Boards 82.3°C/W 1 78.0°C/W 2.5 75.9°C/W TRANSISTOR COUNT The transistor count for ICS843004-125 is: 2894 PACKAGE OUTLINE PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP AND DIMENSIONS TABLE 8. PACKAGE DIMENSIONS SYMBOL N A A1 A2 b c D E E1 e L α aaa 0.45 0° -4.30 0.65 BASIC 0.75 8° 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 24 1.20 0.15 1.05 0.30 0.20 7.90 Maximum Reference Document: JEDEC Publication 95, MO-153 ICS843004AG-125 REVISION A JUNE 3, 2009 12 ©2009 Integrated Device Technology, Inc. ICS43004-125 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 9. ORDERING INFORMATION Part/Order Number 843004AG-125LF 843004AG-125LFT Marking ICS43004A125L ICS43004A125L Package 24 Lead "Lead-Free" TSSOP 24 Lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel Temperature 0°C to 70°C 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended termperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS843004AG-125 REVISION A JUNE 3, 2009 13 ©2009 Integrated Device Technology, Inc. ICS43004-125 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER www.IDT.com 6024 Silver Creek Valley Road San Jose, CA 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Techical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performace, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved.