844256BGLFT

ICS844256 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS844256 is a Cr ystal-to-LVDS Clock ICS Synthesizer/Fanout Buffer designed for SONET HiPerClockS™ and Gigabit Ether net applications and is a member of the HiperClock S™ family of High Perfor mance Clock Solutions from IDT. The output frequency can be set using the frequency select pins and a 25MHz crystal for Ethernet frequencies, or a 19.44MHz crystal for SONET. The low phase noise characteristics of the ICS844256 make it an ideal clock for these demanding applications. • Six LVDS outputs • Crystal oscillator interface • Output frequency range: 62.5MHz to 622.08MHz • Crystal input frequency range: 15.625MHz to 25.5MHz • RMS phase jitter at 125MHz, using a 25MHz crystal (1.875MHz to 20MHz): 0.48ps (typical) • Full 3.3V or 3.3V core, 2.5V output supply mode • 0°C to 70°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages SELECT FUNCTION TABLE Inputs Function FB_SEL N_SEL1 N_SEL0 M Divide N Divide M/N 0 0 0 25 1 25 0 0 1 25 2 12.5 0 1 0 25 4 6.25 0 1 1 25 5 5 1 0 0 32 1 32 1 0 1 32 2 16 1 1 0 32 4 8 1 1 1 32 8 4 BLOCK DIAGRAM PIN ASSIGNMENT Q0 nQ0 PLL_BYPASS Pullup Q1 1 XTAL_IN OSC PLL 0 Output Divider XTAL_OUT N_SEL1 N_SEL0 Q2 nQ2 Feedback Divider FB_SEL nQ1 VDDO VDDO nQ2 Q2 nQ1 Q1 nQ0 Q0 PLL_BYPASS VDDA VDD FB_SEL 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Q3 nQ3 Q4 nQ4 Q5 nQ5 N_SEL1 GND GND N_SEL0 XTAL_OUT XTAL_IN Q3 ICS844256 nQ3 24-Lead TSSOP, E-Pad 4.40mm x 7.8mm x 0.90mm body package G Package Top View Pulldown Q4 Pullup nQ4 Pullup Q5 nQ5 IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER 1 ICS844256BG REV. A NOVEMBER 7, 2008 ICS844256 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 VDDO 3, 4 5, 6 Type Description Power Output supply pins. nQ2, Q2 Output Differential output pair. LVDS interface levels. nQ1, Q1 Output Differential output pair. LVDS interface levels. 7, 8 nQ0, Q0 Output 9 PLL_BYPASS Input 10 VDDA Power Differential output pair. LVDS interface levels. Selects between the PLL and crystal inputs as the input to the dividers. When LOW, selects PLL. When HIGH, selects XTAL_IN, XTAL_OUT. LVCMOS / LVTTL interface levels. Analog supply pin. 11 VDD Power Core supply pin. 12 13, 14 15, 18 16, 17 FB_SEL XTAL_IN, XTAL_OUT N_SEL0 N_SEL1 GND Input 19, 20 nQ5, Q5 Output Differential output pair. LVDS interface levels. 21, 22 nQ4, Q4 Output Differential output pair. LVDS interface levels. 23, 24 nQ3, Q3 Output Differential output pair. LVDS interface levels. Input Input Pullup Pulldown Feedback frequency select pin. LVCMOS/LVTTL interface levels. Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Pullup Output frequency select pin. LVCMOS/LVTTL interface levels. Power supply ground. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER 2 Minimum Typical Maximum Units ICS844256BG REV. A NOVEMBER 7, 2008 ICS844256 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER CRYSTAL FUNCTION TABLE Inputs XTAL (MHz) FB_SEL Function N_SEL1 N_SEL0 M VCO (MHz) N Output (MHz) 20 0 0 0 25 500 1 500 20 0 0 1 25 500 2 250 20 0 1 0 25 500 4 125 20 0 1 1 25 500 5 100 21.25 0 1 1 25 531.25 5 106.25 24 0 0 0 25 600 1 600 24 0 0 1 25 600 2 300 24 0 1 0 25 60 0 4 150 24 0 1 1 25 60 0 5 12 0 25 0 0 0 25 625 1 625 25 0 0 1 25 625 2 312.5 25 0 1 0 25 625 4 156.25 25 0 1 1 25 625 5 12 5 25.5 0 1 0 25 637.5 4 159.375 15.625 1 1 1 32 500 8 62.5 18.5625 1 1 1 32 594 8 74.25 18.75 1 0 0 32 600 1 600 18.75 1 0 1 32 600 2 300 18.75 1 1 0 32 600 4 150 18.75 1 1 1 32 600 8 75 19.44 1 0 0 32 622.08 1 622.08 19.44 1 0 1 32 622.08 2 311.04 19.44 1 1 0 32 622.08 4 155.52 19.44 1 1 1 32 622.08 8 77.76 19.53125 1 0 0 32 625 1 625 19.53125 1 0 1 32 625 2 312.5 19.53125 1 1 0 32 625 4 156.25 19.53125 1 1 1 32 62 5 8 78.125 20 1 1 1 32 640 8 80 IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER 3 ICS844256BG REV. A NOVEMBER 7, 2008 ICS844256 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 24 Lead TSSOP, EPad 32.1°C/W (0 mps) -65°C to 150°C Storage Temperature, TSTG TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD – 0.20 3.3 VDD V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 160 mA IDDA Analog Supply Current 20 mA IDDO Output Supply Current 160 mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage VDDA Analog Supply Voltage 3.135 3. 3 3.465 V VDD – 0.20 3.3 VDD V VDDO Output Supply Voltage 2.375 IDD Power Supply Current 2.5 2.625 V 160 mA IDDA Analog Supply Current 20 mA IDDO Output Supply Current 150 mA TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 3.3V±5% Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions OR Minimum 2 -0.3 FB_SEL PLL_BYPASS, N_SEL0, N_SEL1 FB_SEL PLL_BYPASS, N_SEL0, N_SEL1 2.5V±5%, TA = 0°C Typical TO 70°C Maximum Units VDD + 0.3 V 0.8 V VDD = VIN = 3.465V 150 µA VDD = VIN = 3.465V 5 µA VDD = 3.465V, VIN = 0V -5 µA VDD = 3.465V, VIN = 0V -150 µA IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER 4 ICS844256BG REV. A NOVEMBER 7, 2008 ICS844256 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDO = 3.3V±5% TA = 0°C TO 70°C Symbol Parameter VOD Differential Output Voltage Δ VOD VOD Magnitude Change VOS Offset Voltage Δ VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 275 350 475 mV 50 mV 1.15 1.25 1.50 V 50 mV Units NOTE: Please refer to Parameter Measurement Information for output information. TABLE 4E. LVDS DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter VOD Differential Output Voltage Δ VOD VOD Magnitude Change VOS Offset Voltage Δ VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum 250 350 450 mV 50 mV 1.15 1.25 1.50 V 50 mV TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental 25.5 MHz Equivalent Series Resistance (ESR) Frequency 15.625 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW NOTE: Characterized using an 18pF parallel resonant cr ystal. IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER 5 ICS844256BG REV. A NOVEMBER 7, 2008 ICS844256 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER TABLE 6A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter FOUT Output Frequency tjit(Ø) RMS Phase Jitter (Random) tsk(o) Output Skew; NOTE 1, 2 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical 62.5 125MHz, Integration Range: 1.875MHz - 20MHz Maximum Units 625 MHz 0.48 ps 65 ps ps 20% to 80% 200 550 fOUT ≤ 312.5MHz 47 53 % fOUT > 312.5MHz 42 58 % PLL Lock Time 1 ms tLOCK NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditons.“ See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. TABLE 6B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter FOUT Output Frequency tjit(Ø) RMS Phase Jitter (Random) tsk(o) Output Skew; NOTE 1, 2 tR / tF Output Rise/Fall Time odc Test Conditions Output Duty Cycle Minimum Typical 62.5 125MHz, Integration Range: 1.875MHz - 20MHz Maximum Units 625 MHz 0.44 ps 65 ps 20% to 80% 135 600 ps fOUT ≤ 312.5MHz 46 54 % fOUT > 312.5MHz 40 60 % PLL Lock Time 1 ms tLOCK NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditons.“ See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER 6 ICS844256BG REV. A NOVEMBER 7, 2008 ICS844256 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER ➤ TYPICAL PHASE NOISE AT 125MHZ @ 3.3V Gb Ethernet Filter NOISE POWER dBc Hz 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.48ps (typical) Raw Phase Noise Data ➤ ➤ Phase Noise Result by adding Gb Ethernet Filter to raw data OFFSET FREQUENCY (HZ) ➤ TYPICAL PHASE NOISE AT 125MHZ @ 3.3V/2.5V Gb Ethernet Filter Raw Phase Noise Data ➤ ➤ NOISE POWER dBc Hz 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.44ps (typical) Phase Noise Result by adding Gb Ethernet Filter to raw data OFFSET FREQUENCY (HZ) IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER 7 ICS844256BG REV. A NOVEMBER 7, 2008 ICS844256 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION VDD SCOPE 3.3V±5% POWER SUPPLY + Float GND – Qx VDD, VDDO V DDA Qx VDDA SCOPE + + VDDO LVDS LVDS nQx nQx 3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT nQx nQ0:nQ5 Qx Q0:Q5 t PW t nQy Qy odc = tsk(o) PERIOD t PW x 100% t PERIOD OUTPUT SKEW OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD VDD out nQ0:nQ5 80% DC Input VOD 20% 20% Q0:Q5 LVDS ➤ 80% tR out tF ➤ VOS/Δ VOS ➤ OFFSET VOLTAGE SETUP OUTPUT RISE/FALL TIME VDD LVDS 100 ➤ VOD/Δ VOD out ➤ DC Input ➤ out DIFFERENTIAL OUTPUT VOLTAGE SETUP IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER 8 ICS844256BG REV. A NOVEMBER 7, 2008 Reference Document: JEDEC Publication 95, MO-153 – POWER SUPPLY Float GND ICS844256 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS844256 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VDDA requires that an additional10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. 3.3V VDD .01μF 10Ω VDDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. LVDS Outputs All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, we recommend that there is no trace attached. CRYSTAL INPUT INTERFACE below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error. The ICS844256 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 XTAL_IN C1 18p X1 18pF Parallel Crystal XTAL_OUT C2 22p FIGURE 2. CRYSTAL INPUt INTERFACE IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER 9 ICS844256BG REV. A NOVEMBER 7, 2008 ICS844256 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER LVCMOS TO XTAL INTERFACE resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. The XTAL_IN input can accept a single-ended LVCMOS signal through an AC couple capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series VDD VCC VDD VCC R1 Ro .1uf Rs Zo = 50 XTAL_IN R2 Zo = Ro + Rs XTAL_OUT FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE 3.3V, 2.5V LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 4. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. 2.5V or 3.3V VDD LVDS_Driv er + R1 100 - 100 Ohm Differential Transmission Line FIGURE 4. TYPICAL LVDS DRIVER TERMINATION IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER 10 ICS844256BG REV. A NOVEMBER 7, 2008 Reference Document: JEDEC Publication 95, MO-153 ICS844256 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER EPAD THERMAL RELEASE PATH In order to maximize both the removal of heat from the package and the electrical perfor mance, a land patter n must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 5. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadfame Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) SOLDER PIN PIN PAD EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER SOLDER PIN LAND PATTERN (GROUND PAD) PIN PAD FIGURE 5. ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE) IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER 11 ICS844256BG REV. A NOVEMBER 7, 2008 ICS844256 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER SCHEMATIC LAYOUT Figure 6 shows an example of ICS844256 application schematic. In this example, the device is operated at VDD = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The C1 = 27pF and C2 = 27pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. One example of HCSL and one example of LVCMOS terminations are shown in this schematic. The decoupling capacitors should be located as close as possible to the power pin. FIGURE 6. ICS844256 SCHEMATIC LAYOUT IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER 12 ICS844256BG REV. A NOVEMBER 7, 2008 ICS844256 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS844256. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS844256 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (160mA + 20mA) = 623.7mW Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 160mA = 554.5mW Total Power_MAX = 623.7mW + 554.5mW = 1178.1mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 32.1°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 1.178W * 32.1°C/W = 107.8°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (multi-layer). TABLE 7. THERMAL RESISTANCE θJA FOR 24-LEAD TSSOP, E-PAD, FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER 13 0 1 2.5 32.1°C/W 25.5°C/W 24.0°C/W ICS844256BG REV. A NOVEMBER 7, 2008 ICS844256 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP, E-PAD θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 32.1°C/W 25.5°C/W 24.0°C/W TRANSISTOR COUNT The transistor count for ICS844256 is: 3887 IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER 14 ICS844256BG REV. A NOVEMBER 7, 2008 ICS844256 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP, E-PAD TABLE 9. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Nominal Maximum 24 A -- 1.10 A1 0.05 0.15 A2 0.85 b 0.19 b1 0.19 c 0.09 c1 0.09 D 7. 7 0 E E1 0.95 0.30 0.22 0.25 0.20 0.127 0.16 7.80 7.90 6.40 BASIC 4.30 e L 0.90 4.40 4.50 0.65 BASIC 0.50 0.60 0.70 P 5. 5 P1 3.2 α 0° 8° aaa 0.076 bbb 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER 15 ICS844256BG REV. A NOVEMBER 7, 2008 ICS844256 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 844256BG ICS844256BG 24 Lead TSSOP, E-Pad tube 0°C to 70°C 844256BGT ICS844256BG 24 Lead TSSOP, E-Pad 2500 tape & reel 0°C to 70°C 844256BGLF ICS844256BGLF 24 Lead "Lead-Free" TSSOP, E-Pad tube 0°C to 70°C 844256BGLFT ICS844256BGLF 24 Lead "Lead-Free" TSSOP, E-Pad 2500 tape & reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER 16 ICS844256BG REV. A NOVEMBER 7, 2008 ICS844256 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support Corporate Headquarters 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT netcom@idt.com +480-763-2056 Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA