844441DGILFT

844441 FemtoClock® SAS/ SATA Clock Generator Datasheet General Description Features The 844441 is a low jitter, high performance clock generator and a member of the FemtoClock® family of silicon timing products. The 844441 is designed for use in applications using the SAS and SATA interconnect. The 844441 uses an external, 25MHz, parallel resonant crystal to generate four selectable output frequencies: 75MHz, 100MHz, 150MHz, and 300MHz. This silicon based approach provides excellent frequency stability and reliability. The 844441 features down and center spread spectrum (SSC) clocking techniques. • • • • • • Designed for use in SAS, SAS-2, and SATA systems • External fundamental crystal frequency ensures high reliability and low aging • Selectable output frequencies: 75MHz, 100MHz, 150MHz, 300MHz • • Output frequency is tunable with external capacitors • • • 2.5V operating supply Applications • • • • • • • SAS/SATA Host Bus Adapters SATA Port Multipliers SAS I/O Controllers TapeDrive and HDD Array Controllers SAS Edge and Fanout Expanders HDDs and TapeDrives Disk Storage Enterprise Center (±0.17%) Spread Spectrum Clocking (SSC) Down (-0.23% or -0.5%) SSC Better frequency stability than SAW oscillators One differential 2.5V LVDS output Crystal oscillator interface designed for 25MHz (CL = 12pF) frequency RMS phase jitter @ 100MHz, using a 25MHz crystal (12kHz – 20MHz): 1.1936ps (typical) -40°C to 85°C ambient operating temperature Lead-free (RoHS 6) packaging Pin Assignment Block Diagrams XTAL_OUT XTAL_IN SSC_SEL0 SSC_SEL1 XTAL_IN 25MHz XTAL OSC FemtoClock™ PLL XTAL_OUT SSC_SEL(1:0) 00 = SSC Off 01 = 0.5% Down-spread 10 = 0.23% Down-spread 11 = 0.5% Center-spread 1 2 3 4 8 7 6 5 GND nQ Q VDD 844441 8-Lead SOIC, 3.90mm x 4.90mm Package Q nQ SSC Output Control Logic Pulldown:Pulldown 8-Lead SOIC nPLL_SEL Pulldown GND XTAL_IN 25MHz XTAL OSC FemtoClock™ PLL XTAL_OUT F_SEL(1:0) SSC_SEL(1:0) 0 1 00 = 75MHz 01 = 100MHz 10 = 150MHz (default) 11 = 300MHz Q nQ nc nc SSC_SEL1 Pullup:Pulldown Pulldown:Pulldown Clock Output Control Logic 16-Lead TSSOP ©2016 Integrated Device Technology, Inc. XTAL_OUT XTAL_IN SSC_SEL0 nc 1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 F_SEL1 GND nPLL_SEL nQ Q VDD F_SEL0 VDD 844441 16-Lead TSSOP, 4.4mm x 5.0mm Package Revison E, November 2, 2016 844441 Datasheet Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Name Type Description XTAL_OUT, XTAL_IN Input SSC_SEL0, SSC_SEL1 Input Pulldown SSC select pins. See Table 3A. LVCMOS/LVTTL interface levels. F_SEL0 Input Pulldown Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels. F_SEL1 Input Pullup Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels. nPLL_SEL Input Pulldown Q, nQ Output Differential clock outputs. LVDS interface levels. GND Power Power supply ground. VDD Power Power supply pin. nc Unused Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. PLL Bypass pin. LVCMOS/LVTTL interface levels. No connect. NOTE: Pullup/Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance RPULLDOWN RPULLUP Test Conditions Minimum nPLL_SEL, F_SEL[1:0], SSC_SEL[1:0] Typical Maximum Units 4 pF Input Pulldown Resistor 51 k Input Pullup Resistor 51 k Function Tables Table 3A. SSC_SEL[1:0] Function Table Table 3B. F_SEL[1:0] Function Table Inputs Inputs SSC_SEL1 SSC_SEL0 Mode F_SEL1 F_SEL0 Output Frequency (MHz) 0 (default) 0 (default) SSC Off 0 0 75 0 1 0.5% Down-spread 0 1 100 1 0 0.23% Down-spread 1 (default) 0 (default) 150 1 1 0.34% Center-spread 1 1 300 ©2016 Integrated Device Technology, Inc. 2 Revison E, November 2, 2016 844441 Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, JA 16 Lead TSSOP 8 Lead SOIC 81.2°C/W (0 mps) 96.0°C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions VDD Power Supply Voltage IDD Power Supply Current Minimum Typical Maximum Units 2.375 2.5 2.625 V 73 mA Maximum Units Table 4B. LVCMOS/LVTTL DC Characteristics,VDD = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical VIH Input High Voltage 1.7 VDD + 0.3 V VIL Input Low Voltage -0.3 0.7 V IIH Input High Current IIL Input Low Current F_SEL1 VDD = VIN = 2.5V 5 µA SSC_SEL[0:1], F_SEL0, nPLL_SEL VDD = VIN = 2.5V 150 µA F_SEL1 VDD = 2.5V, VIN = 0V -150 µA SSC_SEL[0:1], F_SEL0, nPLL_SEL VDD = 2.5V, VIN = 0V -5 µA Table 4C. LVDS DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change ©2016 Integrated Device Technology, Inc. Test Conditions Minimum 200 1 3 Typical Maximum Units 454 mV 50 mV 1.375 V 50 mV Revison E, November 2, 2016 844441 Datasheet Table 4D. Crystal Characteristics Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 50 Ohm Shunt Capacitance 7 pF Load Capacitance (CL) 12 pF AC Electrical Characteristics Table 5. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Symbol fOUT tjit(Ø) Parameter Test Conditions Minimum Typical Maximum Units F_SEL(1:0) = 00 75 MHz F_SEL(1:0) = 01 100 MHz F_SEL(1:0) = 10 150 MHz F_SEL(1:0) = 11 300 MHz 75MHz, Integration Range: 12kHz – 20MHz 1.19602 ps 100MHz, Integration Range: 12kHz – 20MHz 1.1936 ps 150MHz, Integration Range: 12kHz – 20MHz 1.22743 ps 300MHz, Integration Range: 12kHz – 20MHz 1.15011 ps Output Frequency RMS Phase Jitter (Random); NOTE 1 t R / tF Output Rise/Fall Time odc Output Duty Cycle 20% to 80% 100 400 ps 45 55 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Characterized using a 25MHz, 12pF quartz crystal. NOTE 1: Please refer to the Phase Noise plot. ©2016 Integrated Device Technology, Inc. 4 Revison E, November 2, 2016 844441 Datasheet Noise Power (dBc / Hz) Typical Phase Noise at 100MHz Offset Frequency (Hz) ©2016 Integrated Device Technology, Inc. 5 Revison E, November 2, 2016 844441 Datasheet Parameter Measurement Information VDD RMS Phase Jitter 2.5V LVDS Output Load Test Circuit nQ nQ 80% Q 80% VOD Q 20% 20% tR tF Output Rise/Fall Time Output Duty Cycle/Pulse Width/Period Offset Voltage Setup Differential Output Voltage Setup ©2016 Integrated Device Technology, Inc. 6 Revison E, November 2, 2016 844441 Datasheet Application Information Overdriving the XTAL Interface The XTAL_IN input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The XTAL_OUT pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than 0.2V/ns. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. Figure 1A shows an example of the interface diagram for a high speed 3.3V LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This VCC can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and changing R2 to 50. The values of the resistors can be increased to reduce the loading for a slower and weaker LVCMOS driver. Figure 1B shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL termination with one side of the driver feeding the XTAL_IN input. It is recommended that all components in the schematics be placed in the layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. XTAL_OUT R1 100 Ro Rs C1 Zo = 50 ohms XTAL_IN R2 100 Zo = Ro + Rs .1uf LVCMOS Driver Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface XTAL_OUT C2 Zo = 50 ohms XTAL_IN .1uf Zo = 50 ohms LVPECL Driver R1 50 R2 50 R3 50 Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface ©2016 Integrated Device Technology, Inc. 7 Revison E, November 2, 2016 844441 Datasheet Recommendations for Unused Input Pins Inputs: LVCMOS Control Pins All control pins have internal pull-ups; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVDS Driver Termination For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90 and 132. The actual value should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100 parallel resistor at the receiver and a 100 differential transmission-line environment. In order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The LVDS Driver standard termination schematic as shown in Figure 2A can be used with either type of output structure. Figure 2B, which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is recommended to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the output. ZO  ZT ZT LVDS Receiver Figure 2A. Standard Termination LVDS Driver ZO  ZT C ZT 2 LVDS ZT Receiver 2 Figure 2B. Optional Termination LVDS Termination ©2016 Integrated Device Technology, Inc. 8 Revison E, November 2, 2016 844441 Datasheet Schematic Example Figures 3A and 3B are example 844441 application schematics for either the 8 pin M package or the 16 pin G package. The schematic examples focus on functional connections and are not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set. In order to achieve the best possible filtering, it is recommended that the placement of the power filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1µF capacitor in each power pin filter should be placed on the device side. The other components can be on the opposite side of the PCB. In this example, the device is operated at VDD = 2.5V. A 12pF parallel resonant 25MHz crystal is used with tuning capacitors C1 = C2 =14pF, which are recommended for frequency accuracy. Depending on the variation of the parasitic stray capacity of the printed circuit board traces between the crystal and the Xtal_In and Xtal_Out pins, the values of C1 and C2 might require a slight adjustment to optimize the frequency accuracy. Crystals with other load capacitance specifications can be used, but this will require adjusting C1 and C2. In circuit board design, return the capacitors to ground through a single point contact close to the package. Two examples of terminations for LVDS receivers without built-in termination are shown in this schematic. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. FOX 603-25-173 crystal ,'7&U\VWDO R 20 0 XTA L_OU T 2 5MH z( 12p f) 4 1 X1 3 2 C1 14pF Zo = 50 O hm U1 1 2 3 4 XT AL_ IN S SC _S EL0 S SC _S EL1 XTA L_OU T XTA L_I N SS C _SE L0 SS C _SE L1 G ND nQ Q V DD 8 7 6 5 nQ Q R1 100 - Zo = 50 O hm C2 14pF + C3 0. 1uF 2. 5V 1 F B1 Pl ace th e 0.1 uF by pas s c ap di rec tly a dja cen t to the V DD pin . 2 VD D B LM18 BB 221S N 1 C5 0. 1u F C6 10uF Q Z o = 50 O hm Logic Input Pin Examples Set Logic Input to '1' V DD RU 1 1K R3 50 Set Logic Input to '0' V DD C9 0. 1u F R4 50 RU2 N ot I ns t all To Logic Input pins RD 1 N ot I ns t all + To Logic Input pins nQ RD2 1K - Z o = 50 O hm Alternate LVDS Termination Figure 3A. 844441 Schematic Example ©2016 Integrated Device Technology, Inc. 9 Revison E, November 2, 2016 844441 Datasheet P l ac e o n e o f t h e 0 . 1u F by p as s ca p s d i re c tl y ad j ac e n t t o o n e o f t h e V D D p in s . 4 8 SSC_SEL0 SSC_SEL1 F_SEL0 F_SEL1 10 16 nPLL_SEL 14 0 F_SEL0 F_SEL1 Zo = 50 Ohm nPLL_SEL Q XTAL_IN 3 XTAL_IN nQ 25 M H z( 1 2 pf ) 4 2 X1 1 3 12 Q + R2 100 13 nQ - Zo = 50 Ohm XTAL_OUT XTAL_OUT nc nc nc GND 1 15 C2 14pF 5 6 7 GND 2 C1 14pF C10 0.1uF SSC_SEL0 SSC_SEL1 FOX 603-25-173 crystal ,'7&U\VWDO R19 BLM18BB221SN1 11 VDD U7 2.5V 1 C4 C11 0.1uF 10uF VDD 9 C13 0.1uF FB2 2 VDD Q Zo = 50 Ohm Logi c Input P in Examples Set Logic Input to '1' VDD RU3 1K R5 50 Set Logic Input to '0' VDD C12 0.1uF R6 50 RU4 Not Install To Logic Inpu t pins RD4 Not Ins tall + To Logic In put pins nQ RD3 1K - Zo = 50 Ohm Alternate LVDS Termination Figure 3B. 844441 Schematic Example ©2016 Integrated Device Technology, Inc. 10 Revison E, November 2, 2016 844441 Datasheet Power Considerations This section provides information on power dissipation and junction temperature for the 844441. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 844441 is the sum of the core power plus the power dissipated due to loading. The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results. Total Power MAX = VDD_MAX * IDD_MAX = 2.625V * 73mA = 191.7mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 96°C/W per Table 6B below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.192W * 96°C/W = 103.4°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the supply voltage, air flow and the type of board (multi-layer). Table 6A. Thermal Resistance JA for 16 Lead TSSOP, Forced Convection JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 81.2°C/W 73.9°C/W 70.2°C/W 0 200 500 96°C/W 87°C/W 82°C/W Table 6B. Thermal Resistance JA for 8 Lead SOIC, Forced Convection JA vs. Air Flow Linear Feet per Second Multi-Layer PCB, JEDEC Standard Test Boards ©2016 Integrated Device Technology, Inc. 11 Revison E, November 2, 2016 844441 Datasheet Reliability Information Table 7A. JA vs. Air Flow Table for a 16 Lead TSSOP JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 81.2°C/W 73.9°C/W 70.2°C/W 0 200 500 96°C/W 87°C/W 82°C/W Table 7B. JA vs. Air Flow Table for a 8 Lead SOIC JA vs. Air Flow Linear Feet per Second Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for 844441 is: 3374 ©2016 Integrated Device Technology, Inc. 12 Revison E, November 2, 2016 844441 Datasheet Package Outline and Package Dimensions Package Outline - G Suffix for 16-Lead TSSOP Package Outline - M Suffix for 8 Lead SOIC aaa C 9 A ccc C 8 S 0.08 C NX L2 NX b2 7 C A B 6.25 bbb Table 8B. Package Dimensions for 8 Lead SOIC Table 8A. Package Dimensions for 16 Lead TSSOP All Dimensions in Millimeters Symbol Minimum Maximum N 8 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 Basic H 5.80 6.20 h 0.25 0.50 L 0.40 1.27  0° 8° All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75  0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MS-012 Reference Document: JEDEC Publication 95, MO-153 ©2016 Integrated Device Technology, Inc. 13 Revison E, November 2, 2016 844441 Datasheet Ordering Information Table 9. Ordering Information Part/Order Number Marking Output Frequency (MHz) Package Shipping Packaging Temperature 844441DGILF 44441DIL 75, 100, 150, 300 16 Lead TSSOP, Lead-Free Tube -40C to 85C 844441DGILFT 44441DIL 75, 100, 150, 300 16 Lead TSSOP, Lead-Free Tape & Reel -40C to 85C 844441DMI-75LF 441DI75L 75 8 Lead SOIC, Lead-Free Tube -40C to 85C 844441DMI-75LFT 441DI75L 75 8 Lead SOIC, Lead-Free Tape & Reel -40C to 85C 844441DMI-100LF 41DI100L 100 8 Lead SOIC, Lead-Free Tube -40C to 85C 844441DMI-100LFT 41DI100L 100 8 Lead SOIC, Lead-Free Tape & Reel -40C to 85C 844441DMI-150LF 41DI150L 150 8 Lead SOIC, Lead-Free Tube -40C to 85C 844441DMI-150LFT 41DI150L 150 8 Lead SOIC, Lead-Free Tape & Reel -40C to 85C 844441DMI-300LF 41DI300L 300 8 Lead SOIC, Lead-Free Tube -40C to 85C 844441DMI-300LFT 41DI300L 300 8 Lead SOIC, Lead-Free Tape & Reel -40C to 85C Revision History Sheet Rev B C D E Table Page Description of Change T4D T5 1 4 4 9 - 10 Features Section, Crystal Oscillator bullet, added additional crystal recommendation. Crystal Characteristics Table - added crystal recommendation note. AC Characteristics Table - added additional crystal recommendation to 2nd note. Application Schematics - in schematics, added additional crystal recommendation. Deleted part number prefix/suffix throughout the datasheet. Updated datasheet header/footer. 5/5/15 9 - 10 Updated Application Schematics. 7/31/15 PDN #CQ-15-04 Product Discontinuance Notice – Last Time buy Expires on August 14, 2016. 08/21/15 1 9 - 10 Date The 844441 datasheet is obsolete per PDN #CQ-15-04. Application Schematic, IDT crystal part number was replaced by FOX part number. ©2016 Integrated Device Technology, Inc. 14 11/2/16 Revison E, November 2, 2016 844441 Datasheet Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales www.IDT.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. 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