8741004AGLFT

Differential-to-LVDS/0.7V Differential PCI Express™ Jitter Attenuator 8741004 DATA SHEET General Description Features The 8741004 is a high performance Differential-to-LVDS/0.7V Differential Jitter Attenuator designed for use in PCI Express™ systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The 8741004 has 3 PLL bandwidth modes: 200kHz, 600kHz and 2MHz. The 200kHz mode will provide maximum jitter attenuation, but with higher PLL tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. The 600kHz provides an intermediate bandwidth that can easily track triangular spread profiles, while providing good jitter attenuation. The 2MHz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter attenuation will not be as good as the lower bandwidth modes. Because some 2.5Gb serdes have x20 multipliers while others have x25 multipliers, the 8741004 can be set for 1:1 mode or 5/4 multiplication mode (i.e. 100MHz input/125MHz output) using the F_SEL pins. • Two LVDS and two 0.7V differential output pairs Bank A has two LVDS output pairs and Bank B has two 0.7V differential output pairs • • One differential clock input pair • • • • • • Output frequency range: 98MHz - 160MHz • • 0°C to 70°C ambient operating temperature The 8741004 uses IDT’s 3rd Generation FemtoClock™ PLL technology to achieve the lowest possible phase noise. The device is packaged in a 24 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. CLK, CLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL Input frequency range: 98MHz - 128MHz VCO range: 490MHz - 640MHz Cycle-to-cycle jitter: 35ps (maximum) Full 3.3V operating supply Three bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs Available in lead-free (RoHS 6) package Pin Assignment nQA1 QA1 VDDO QA0 nQA0 MR BW_SEL nc VDDA F_SELA VDD OEA PLL Bandwidth BW_SEL 0 = PLL Bandwidth: ~200kHz Float = PLL Bandwidth: ~600kHz (default) 1 = PLL Bandwidth: ~2MHz 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 nQB1 QB1 VDDO QB0 nQB0 IREF F_SELB OEB GND GND nCLK CLK 8741004 24-Lead TSSOP 4.4mm x 7.8mm x 0.925mm package body G Package Top View 8741004 Rev A 7/20/15 1 ©2015 Integrated Device Technology, Inc. 8741004 DATA SHEET Block Diagram OEA Pullup F_SELA Pulldown QA0 BW_SEL Float F_SELA 0 ÷5 (default) 1 ÷4 0 = ~200kHz Float = ~400kHz 1 = ~800kHz nQA0 QA1 CLK Pulldown nCLK Pullup Phase Detector VCO nQA1 490 - 640 MHz QB0 F_SELB 0 ÷5 (default) 1 ÷4 M = ÷5 (fixed) nQB0 QB1 nQB1 F_SELB Pulldown MR Pulldown IREF OEB Pullup DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR 2 Rev A 7/20/15 8741004 DATA SHEET Table 1. Pin Descriptions Number Name Type Description 1, 2 QA1, QA1 Output Differential output pair. LVDS interface levels. 3, 22 VDDO Power Output supply pins. 4, 5 QA0, QA0 Output Differential output pair. LVDS interface levels. 6 MR Input Pulldown Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Q[Ax:Bx] to go LOW and the inverted outputs Q[Ax:Bx] to go HIGH. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 7 BW_SEL Input Pullup/ Pulldown PLL Bandwidth input. LVCMOS/LVTTL interface levels. See Table 3B. 8 nc Unused 9 VDDA Power 10 F_SELA Input 11 VDD Power 12 OEA Input Pullup 13 CLK Input Pulldown 14 CLK Input Pullup 15, 16 GND Power 17 OEB Input Pullup 18 F_SELB Input Pulldown 19 IREF Input 20, 21 QB0, QB0 Output Differential output pair. HCSL interface levels. 23, 24 QB1, QB1 Output Differential output pair. HCSL interface levels. No connect. Analog supply pin. Pulldown Frequency select pins for QAx/QAx outputs. LVCMOS/LVTTL interface levels. See Table 3C. Core supply pin. Output enable for QAx pins. When HIGH, QAx/QAx outputs are enabled. When LOW, the QAx/QAx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. See Table 3A. Non-inverting differential clock input. Inverting differential clock input. Power supply ground. Output enable for QBx pins. When HIGH, QBx/QBx outputs are enabled. When LOW, the QBx/QBx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. See Table 3A. Frequency select pins for QBx/QBx outputs. LVCMOS/LVTTL interface levels. See Table 3C. A fixed precision resistor (RREF = 475) from this pin to ground provides a reference current used for differential current-mode QB0/nQB0 clock outputs. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR 3 Minimum Typical Maximum Units Rev A 7/20/15 8741004 DATA SHEET Function Tables Table 3A. Output Enable Function Table Inputs Table 3B. PLL Bandwidth Function Table Outputs Input OEA OEB QA[0:1]/QA[0:1] QB[0:1]/QB[0:1] BW_SEL 0 0 Hi-Z Hi-Z 0 1 1 Enabled Enabled Float PLL Bandwidth ~200kHz ~600kHz (default) 1 ~2MHz Table 3C. Frequency Select Table Inputs F_SEL[A, B] Divider 0 ÷5 (default) 1 ÷4 Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 82.3C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VDD Core Supply Voltage VDDA Minimum Typical Maximum Units 3.135 3.3 3.465 V Analog Supply Voltage VDD – 0.12 3.3 VDD V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 45 mA IDDA Analog Supply Current 12 mA IDDO Output Supply Current 80 mA Rev A 7/20/15 Test Conditions 4 DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR 8741004 DATA SHEET Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol VIH Parameter Input High Voltage Test Conditions Maximum Units 2 VDD + 0.3 V VDD – 0.3 VDD + 0.3 V OEA, OEB, MR, F_SELA, F_SELB -0.3 0.8 V BW_SEL -0.3 +0.3 V VDD/2 – 0.1 VDD/2 + 0.1 V OEA, OEB, MR, F_SELA, F_SELB BW_SEL VIL Input Low Voltage Minimum Typical VIM Input Mid Voltage BW_SEL VDD = VIN = 3.465V µA Input High Current F_SELA, F_SELB, MR, BW_SEL 150 IIH OEA, OEB VDD = VIN = 3.465V 5 µA IIL Input Low Current MR, F_SELA, F_SELB, VDD = 3.465V, VIN = 0V -5 µA OEA, OEB, BW_SEL VDD = 3.465V, VIN = 0V -150 µA Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter IIH Input High Current IIL Test Conditions Minimum Typical Maximum Units CLK VDD = VIN = 3.465V 150 µA CLK VDD = VIN = 3.465V 5 µA CLK VDD = 3.465V, VIN = 0V -5 µA CLK VDD = 3.465V, VIN = 0V -150 µA Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 0.15 1.3 V GND + 0.5 VDD – 0.85 V NOTE 1: VIL should not be less than -0.3V NOTE 2: Common mode input voltage is defined as VIH. Table 4D. LVDS DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change Test Conditions DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR Minimum Typical Maximum Units 290 390 490 mV 50 mV 1.5 V 50 mV 1.2 5 1.35 Rev A 7/20/15 8741004 DATA SHEET AC Electrical Characteristics Table 5. 0.7V Differential AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Parameter Symbol fMAX Output Frequency Test Conditions Minimum Typical 98 Maximum Units 160 MHz tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 35 ps tsk(b) Bank Skew, NOTE 2 30 ps VHIGH Output Voltage High QBx/QBx 530 870 mV VLOW Output Voltage Low QBx/QBx -150 VOVS Max. Voltage, Overshoot QBx/QBx VUDS Min. Voltage, Undershoot QBx/QBx Vrb Ringback Voltage QBx/QBx VCROSS Absolute Crossing Voltage QBx/QBx @ 0.7V Swing VCROSS Total Variation of VCROSS over all edges QBx/QBx @ 0.7V Swing tR / tF Output Rise/Fall Time QBx/QBx measured between 0.175V to 0.525V QAx/QAx 20% to 80% tR / tF Rise/Fall Time Variation QBx/QBx tRFM Rise/Fall Matching QBx/QBx odc Output Duty Cycle mV VHIGH + 0.35 -0.3 V V 0.2 V 550 mV 140 mV 175 700 ps 250 600 ps 125 ps 20 % 52 % 250 48 NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Defined as skew within a bank of outputs at the same voltage and with equal load conditions. Rev A 7/20/15 6 DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR 8741004 DATA SHEET Parameter Measurement Information 3.3V ±5% VDD, VDDO VDDA 3.3V HCSL Output Load AC Test Circuit 3.3V LVDS Output Load AC Test Circuit VDD QX0 QX0 CLK V Cross Points OD QX1 CLK QX1 V tsk(b) OS GND Where X is either Bank A or Bank B Differential Input Level Bank Skew QA[0:1], QB[0:1] QA[0:1], QB[0:1] QA[0:1], QB[0:1] QA[0:1], QB[0:1] tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles Cycle-to-Cycle Jitter DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR Output Duty Cycle/Pulse Width/Period 7 Rev A 7/20/15 8741004 DATA SHEET Parameter Measurement Information, continued 80% 80% VOD Clock Outputs 20% 20% tF tR LVDS Output Rise/Fall Time Differential Measurement Points for Duty Cycle/Period TSTABLE VRB +150mV VRB = +100mV 0.0V VRB = -100mV -150mV Q - nQ VRB TSTABLE SE Measurement Points for Delta Cross Point Differential Measurement Points for Ringback Rise Edge Rate Fall Edge Rate +150mV 0.0V -150mV Q - nQ Differential Measurement Points for Rise/Fall Time SE Measurement Points for Absolute Cross Point/Swing Rev A 7/20/15 8 DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR 8741004 DATA SHEET Parameter Measurement Information, continued Rise Edge Rate Fall Edge Rate +150mV 0.0V -150mV Q - nQ Differential Measurement Points for Rise/Fall Time Offset Voltage Setup Differential Output Voltage Setup nQ nQ tFALL tRISE VCROSS_MEDIAN +75mV VCROSS_MEDIAN VCROSS_MEDIAN VCROSS_MEDIAN -75mV Q Q SE Measurement Points for Rise/Fall Time Matching DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR 9 Rev A 7/20/15 8741004 DATA SHEET Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 8741004 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin. 3.3V VDD .01µF 10Ω .01µF 10µF VDDA Figure 1. Power Supply Filtering Wiring the Differential Input to Accept Single Ended Levels Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K Figure 2. Single-Ended Signal Driving Differential Input Rev A 7/20/15 10 DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR 8741004 DATA SHEET Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 1.8V Zo = 50Ω CLK Zo = 50Ω nCLK Differential Input LVHSTL IDT LVHSTL Driver R1 50Ω R2 50Ω Figure 3A. HiPerClockS CLK/nCLK Input Driven by an IDT Open Emitter HiPerClockS LVHSTL Driver Figure 3B. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3C. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3D. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVDS Driver 3.3V 2.5V 3.3V 3.3V 2.5V R3 120Ω *R3 R4 120Ω Zo = 60Ω CLK CLK Zo = 60Ω nCLK nCLK HCSL *R4 Differential Input SSTL R1 120Ω Differential Input Figure 3F. HiPerClockS CLK/nCLK Input Driven by a 2.5V SSTL Driver Figure 3E. HiPerClockS CLK/nCLK Input Driven by a 3.3V HCSL Driver DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR R2 120Ω 11 Rev A 7/20/15 8741004 DATA SHEET Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins Differential Outputs All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVDS Outputs All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, we recommend that there is no trace attached. LVDS Driver Termination A general LVDS interface is shown in Figure 4. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 50Ω 3.3V LVDS Driver + R1 100Ω – 50Ω 100Ω Differential Transmission Line Figure 4. Typical LVDS Driver Termination Rev A 7/20/15 12 DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR 8741004 DATA SHEET Recommended Termination Figure 5A is the recommended termination for applications which require the receiver and driver to be on a separate PCB. All traces should be 50Ω impedance. Figure 5A. Recommended Termination Figure 5B is the recommended termination for applications which require a point to point connection and contain the driver and receiver on the same PCB. All traces should all be 50Ω impedance. Figure 5B. Recommended Termination DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR 13 Rev A 7/20/15 8741004 DATA SHEET Power Considerations This section provides information on power dissipation and junction temperature for the 8741004. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS741004 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (45mA + 12mA) = 197.5mW • Power (LVDS_output)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 80mA = 277.2mW • Power (HCSL_output)MAX = 44.5mW * 2 = 89mW Total Power_MAX = (3.465V, with all outputs switching) = 197.5mW + 277.2mW + 89mW = 563.7mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 82.3°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.564W * 82.3°C/W = 116.4°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 6. Thermal Resistance JA for 24 Lead TSSOP, Forced Convection JA Vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards Rev A 7/20/15 0 1 2.5 82.3°C/W 78.0°C/W 75.9°C/W 14 DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR 8741004 DATA SHEET 3. Calculations and Equations. The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 6. VDD IOUT = 17mA VOUT RREF = 475 ± 1% RL 50 IC Figure 6. HCSL Driver Circuit and Termination HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation, use the following equations which assume a 50 load to ground. The highest power dissipation occurs when VDD_MAX. Power = (VDD_MAX – VOUT) * IOUT, since VOUT = IOUT * RL = (VDD_MAX – IOUT * RL) * IOUT = (3.465V – 17mA * 50) * 17mA Total Power Dissipation per output pair = 44.5mW DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR 15 Rev A 7/20/15 8741004 DATA SHEET Reliability Information Table 7. JA vs. Air Flow Table for a 24 Lead TSSOP JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 82.3°C/W 78.0°C/W 75.9°C/W Transistor Count The transistor count for 8741004 is: 1318 Package Outline and Package Dimensions Package Outline - G Suffix for 24 Lead TSSOP Table 8. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 24 A 1.20 A1 0.5 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75  0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 4 40 Rev A 7/20/15 B d 0 65 Pit h TSSOP 16 DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR 8741004 DATA SHEET Ordering Information Table 9. Ordering Information Part/Order Number 8741004AGLF 8741004AGLFT Marking ICS8741004AGL ICS8741004AGL Package “Lead-Free” 24 Lead TSSOP “Lead-Free” 24 Lead TSSOP Shipping Packaging Tray 2500 Tape & Reel Temperature 0C to 70C 0C to 70C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR 17 Rev A 7/20/15 8741004 DATA SHEET Revision History Sheet Rev A Table Page Description of Change T4C T5 5 6 8&9 11 Differential DC Characteristics Table - added NOTE. AC Characteristics Table - corrected VHIGH/VLOW units from ps to mV. Added HCSL Parameter Measurement Information. Updated Differential Clock Input Interface section. 10/31/07 T3C 4 14 & 15 Added F_SEL Function Table. Power Considerations - updated Power Dissipation section to coincide with updates to the Calculations & Equations section on page 15. 5/29/08 Ordering Information - removed leaded devices. Updated data sheet format. 7/20/15 A A T9 17 DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR Date 18 Rev A 7/20/15 Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. 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