8741004BGILFT

8741004I Differential-to-LVDS/0.7V Differential PCI Express™ Jitter Attenuator Data Sheet General Description Features The 8741004I is a high performance Differential-to-LVDS/0.7V Differential Jitter Attenuator designed for use in PCI Express™ systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The 8741004I has 3 PLL bandwidth modes: 200kHz, 600kHz and 2MHz. The 200kHz mode will provide maximum jitter attenuation, but with higher PLL tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. The 600kHz provides an intermediate bandwidth that can easily track triangular spread profiles, while providing good jitter attenuation. The 2MHz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter attenuation will not be as good as the lower bandwidth modes. Because some 2.5Gb serdes have x20 multipliers while others have x25 multipliers, the 8741004I can be set for 1:1 mode or 5/4 multiplication mode (i.e. 100MHz input/125MHz output) using the F_SEL pins. • Two LVDS and two 0.7V differential output pairs Bank A has two LVDS output pairs and Bank B has two 0.7V differential output pairs • • One differential clock input pair • • • • • • Output frequency range: 98MHz - 160MHz • • -40°C to 85°C ambient operating temperature The 8741004I uses IDT’s 3rd Generation FemtoClock™ PLL technology to achieve the lowest possible phase noise. The device is packaged in a 24 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL Input frequency range: 98MHz - 128MHz VCO range: 490MHz - 640MHz Cycle-to-cycle jitter: 35ps (maximum) Full 3.3V operating supply Three bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs Available in lead-free packages Pin Assignment nQA1 QA1 VDDO QA0 nQA0 MR BW_SEL nc VDDA F_SELA VDD OEA PLL Bandwidth BW_SEL 0 = PLL Bandwidth: ~200kHz Float = PLL Bandwidth: ~600kHz (default) 1 = PLL Bandwidth: ~2MHz 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 nQB1 QB1 VDDO QB0 nQB0 IREF F_SELB OEB GND GND nCLK CLK 24-Lead TSSOP, E-Pad 4.40mm x 7.8mm x 0.925mm package body G Package Top View ©2016 Integrated Device Technology, Inc 1 Revision A January 27, 2016 8741004I Data Sheet Block Diagram OEA Pullup F_SELA Pulldown QA0 BW_SEL Float F_SELA 0 ÷5 (default) 1 ÷4 0 = ~200kHz Float = ~400kHz 1 = ~800kHz nQA0 QA1 CLK Pulldown nCLK Pullup Phase Detector VCO nQA1 490 - 640 MHz QB0 F_SELB 0 ÷5 (default) 1 ÷4 M = ÷5 (fixed) nQB0 QB1 nQB1 F_SELB Pulldown MR Pulldown IREF OEB Pullup ©2016 Integrated Device Technology, Inc 2 Revision A January 27, 2016 8741004I Data Sheet Table 1. Pin Descriptions Number Name Type Description 1, 2 nQA1, QA1 Output Differential output pair. LVDS interface levels. 3, 22 VDDO Power Output supply pins. 4, 5 QA0, nQA0 Output Differential output pair. LVDS interface levels. 6 MR Input Pulldown Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Q[Ax:Bx] to go LOW and the inverted outputs nQ[Ax:Bx] to go HIGH. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 7 BW_SEL Input Pullup/ Pulldown PLL Bandwidth input. LVCMOS/LVTTL interface levels. See Table 3B. 8 nc Unused 9 VDDA Power 10 F_SELA Input 11 VDD Power 12 OEA Input Pullup 13 CLK Input Pulldown 14 nCLK Input Pullup Inverting differential clock input. 15, 16 GND Power Power supply ground. Output enable for QBx pins. When HIGH, QBx/nQBx outputs are enabled. When LOW, the QBx/nQBx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. See Table 3A. No connect. Analog supply pin. Pulldown Frequency select pins for QAx/nQAx outputs. LVCMOS/LVTTL interface levels. See Table 3C. Core supply pin. Output enable for QAx pins. When HIGH, QAx/nQAx outputs are enabled. When LOW, the QAx/nQAx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. See Table 3A. Non-inverting differential clock input. 17 OEB Input Pullup 18 F_SELB Input Pulldown 19 IREF Input 20, 21 nQB0, QB0 Output Differential output pair. HCSL interface levels. 23, 24 QB1, nQB1 Output Differential output pair. HCSL interface levels. Frequency select pins for QBx/nQBx outputs. LVCMOS/LVTTL interface levels. See Table 3C. A fixed precision resistor (RREF = 475) from this pin to ground provides a reference current used for differential current-mode QB0/nQB0 clock outputs. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k ©2016 Integrated Device Technology, Inc Test Conditions 3 Minimum Typical Maximum Units Revision A January 27, 2016 8741004I Data Sheet Function Tables Table 3A. Output Enable Function Table Inputs Table 3B. PLL Bandwidth Function Table Outputs Input OEA OEB QA[0:1]/nQA[0:1] QB[0:1]/nQB[0:1] BW_SEL 0 0 Hi-Z Hi-Z 0 1 1 Enabled Enabled Float PLL Bandwidth ~200kHz ~600kHz (default) 1 ~2MHz Table 3C. Frequency Select Table Inputs F_SEL[A, B] Divider 0 ÷5 (default) 1 ÷4 Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 32.1C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VDD Minimum Typical Maximum Units Positive Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD – 0.12 3.3 VDD V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 45 mA IDDA Analog Supply Current 12 mA IDDO Output Supply Current 80 mA ©2016 Integrated Device Technology, Inc Test Conditions 4 Revision A January 27, 2016 8741004I Data Sheet Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol VIH Parameter Maximum Units 2 VDD + 0.3 V VDD – 0.3 VDD + 0.3 V OEA, OEB, MR, F_SELA, F_SELB -0.3 0.8 V BW_SEL -0.3 +0.3 V Input Mid Voltage BW_SEL VDD/2 – 0.1 VDD/2 + 0.1 V VDD = VIN = 3.465V 150 µA Input High Current F_SELA, F_SELB, MR, BW_SEL OEA, OEB VDD = VIN = 3.465V 5 µA Input High Voltage Test Conditions OEA, OEB, MR, F_SELA, F_SELB BW_SEL VIL VIM IIH IIL Input Low Voltage Input Low Current Minimum Typical MR, F_SELA, F_SELB, VDD = 3.465V, VIN = 0V -5 µA OEA, OEB, BW_SEL VDD = 3.465V, VIN = 0V -150 µA Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter IIH Input High Current IIL Test Conditions Minimum Typical Maximum Units CLK VDD = VIN = 3.465V 150 µA nCLK VDD = VIN = 3.465V 5 µA CLK VDD = 3.465V, VIN = 0V -5 µA nCLK VDD = 3.465V, VIN = 0V -150 µA Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, NOTE 2 0.15 1.3 V GND + 0.5 VDD – 0.85 V NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 4D. LVDS DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change ©2016 Integrated Device Technology, Inc Test Conditions Minimum Typical Maximum Units 290 390 490 mV 50 mV 1.5 V 50 mV 1.2 5 1.35 Revision A January 27, 2016 8741004I Data Sheet AC Electrical Characteristics Table 5. 0.7V Differential AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Parameter Symbol Test Conditions Minimum fMAX Output Frequency tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 tsk(b) Bank Skew, NOTE 2 VHIGH Output Voltage High QBx/nQBx 530 VLOW Output Voltage Low QBx/nQBx -150 VOVS Max. Voltage, Overshoot QBx/nQBx VUDS Min. Voltage, Undershoot QBx/nQBx Vrb Ringback Voltage QBx/nQBx VCROSS Absolute Crossing Voltage QBx/nQBx @ 0.7V Swing VCROSS Total Variation of VCROSS over all edges QBx/nQBx @ 0.7V Swing tR / tF Output Rise/Fall Time QBx/nQBx measured between 0.175V to 0.525V QAx/nQAx 20% to 80% Typical 98 Maximum Units 160 MHz 35 ps 30 ps 870 mV mV VHIGH + 0.35 -0.3 V V 0.2 V 550 mV 140 mV 175 700 ps 250 600 ps 250 tR / tF Rise/Fall Time Variation QBx/nQBx 125 ps tRFM Rise/Fall Matching QBx/nQBx 20 % odc Output Duty Cycle 52 % 48 NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Defined as skew within a bank of outputs at the same voltage and with equal load conditions. ©2016 Integrated Device Technology, Inc 6 Revision A January 27, 2016 8741004I Data Sheet Parameter Measurement Information 3.3V±5% 3.3V±5% Measurement Point VDD, VDDO VDDA 3.3V ±5% 2pF VDD, VDDO VDDA Measurement Point IREF GND 2pF 0V 0V 3.3V HCSL Output Load AC Test Circuit 3.3V LVDS Output Load AC Test Circuit VDD nQX0 QX0 nCLK V Cross Points OD nQX1 CLK QX1 V tsk(b) OS GND Where X is either Bank A or Bank B Differential Input Level Bank Skew nQA[0:1], nQB[0:1] nQA[0:1], nQB[0:1] QA[0:1], QB[0:1] QA[0:1], QB[0:1] tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles Cycle-to-Cycle Jitter ©2016 Integrated Device Technology, Inc LVDS Output Duty Cycle/Pulse Width/Period 7 Revision A January 27, 2016 8741004I Data Sheet Parameter Measurement Information, continued 80% 80% VOD Clock Outputs 20% 20% tR tF LVDS Output Rise/Fall Time Offset Voltage Setup TSTABLE VRB +150mV VRB = +100mV 0.0V VRB = -100mV -150mV Q - nQ VRB TSTABLE Differential Measurement Points for Ringback Differential Output Voltage Setup Rise Edge Rate Fall Edge Rate +150mV 0.0V -150mV SRCC - SRCT HCSL Differential Measurement Points for Rise/Fall Time Differential Measurement Points for Duty Cycle/Period ©2016 Integrated Device Technology, Inc 8 Revision A January 27, 2016 8741004I Data Sheet Parameter Measurement Information, continued Differential Measurement Points for Duty Cycle/Period Single-ended Measurement Points for Delta Cross Point nQ nQ tFALL tRISE VCROSS_MEDIAN +75mV VCROSS_MEDIAN VCROSS_MEDIAN VCROSS_MEDIAN -75mV Q Q Differential Measurement Points for Rise/Fall Matching ©2016 Integrated Device Technology, Inc 9 Revision A January 27, 2016 8741004I Data Sheet Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 8741004I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin. 3.3V VDD .01µF 10Ω .01µF 10µF VDDA Figure 1. Power Supply Filtering Wiring the Differential Input to Accept Single Ended Levels Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K Figure 2. Single-Ended Signal Driving Differential Input ©2016 Integrated Device Technology, Inc 10 Revision A January 27, 2016 8741004I Data Sheet Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 1.8V Zo = 50Ω CLK Zo = 50Ω nCLK Differential Input LVHSTL IDT LVHSTL Driver R1 50Ω R2 50Ω Figure 3A. HiPerClockS CLK/nCLK Input Driven by an IDT Open Emitter HiPerClockS LVHSTL Driver Figure 3B. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3C. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3D. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVDS Driver 3.3V 2.5V 3.3V 3.3V 2.5V R3 120Ω *R3 R4 120Ω Zo = 60Ω CLK CLK Zo = 60Ω nCLK nCLK HCSL *R4 Differential Input SSTL R1 120Ω Differential Input Figure 3F. HiPerClockS CLK/nCLK Input Driven by a 2.5V SSTL Driver Figure 3E. HiPerClockS CLK/nCLK Input Driven by a 3.3V HCSL Driver ©2016 Integrated Device Technology, Inc R2 120Ω 11 Revision A January 27, 2016 8741004I Data Sheet Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins Differential Outputs All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVDS Outputs All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, we recommend that there is no trace attached. LVDS Driver Termination A general LVDS interface is shown in Figure 4. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 50Ω 3.3V LVDS Driver + R1 100Ω – 50Ω 100Ω Differential Transmission Line Figure 4. Typical LVDS Driver Termination ©2016 Integrated Device Technology, Inc 12 Revision A January 27, 2016 8741004I Data Sheet Recommended Termination Figure 5A is the recommended termination for applications which require the receiver and driver to be on a separate PCB. All traces should be 50Ù impedance. Figure 5A. Recommended Termination Figure 5B is the recommended termination for applications which require a point to point connection and contain the driver and receiver on the same PCB. All traces should all be 50Ù impedance. Figure 5B. Recommended Termination ©2016 Integrated Device Technology, Inc 13 Revision A January 27, 2016 8741004I Data Sheet EPAD Thermal Release Path dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/Electrically Enhance Leadfame Base Package, Amkor Technology. In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 6. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific and dependent upon the package power SOLDER PIN PIN PAD EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER SOLDER PIN LAND PATTERN (GROUND PAD) PIN PAD Figure 6. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale) ©2016 Integrated Device Technology, Inc 14 Revision A January 27, 2016 8741004I Data Sheet Schematic Example Figure 7 shows an example of 8741004I application schematic. In this example, the device is operated at VDD = VDDO = 3.3V. Two examples of LVDS terminations and two examples of HCSL terminations are shown in this schematic. The input is driven by a 3.3V LVPECL driver. The decoupling capacitors should be located as close as possible to the power pin. Zo = 50 Ohm /QA1 Logic Control Input Examples Set Logic Input to '1' VDD VDD RU1 1K R1 100 Set Logic Input to '0' + Zo = 50 Ohm QA1 RU2 Not Install To Logic Input pins RD1 Not Install To Logic Input pins RD2 1K Alternate LVDS Termination Zo = 50 Ohm QA0 R2 50 + VDD = 3.3V /QA0 C1 0.1uF R3 50 U1 Zo = 50 Ohm VDDO R4 10 C2 10uF QA0 /QA0 MR BW_SEL C3 0.01u F_SELA OEA 1 2 3 4 5 6 7 8 9 10 11 12 /QA1 QA1 VDDO QA0 /QA0 MR BW_SEL nc VDDA F_SELA VDD OEA /QB1 QB1 VDDO QB0 /QB0 IREF F_SELB OEB GND GND /CLK CLK 24 23 22 21 20 19 18 17 16 15 14 13 - /QB1 QB1 VDDO QB0 /QB0 F_SELB OEB VDD=3.3V R5 475 VDDO=3.3V C4 0.1u ICS8741004I R6 33 Zo = 50 - TL4 Zo = 50 Ohm R7 33 CLK Zo = 50 + TL6 Zo = 50 Ohm nCLK LVPECL Driv er R10 50 R8 50 R9 50 Recommended for PCI Express Add-In Card R11 50 HCSL Termination R12 50 (U1:3)VDDO (U1:22) Zo = 50 + QB0 TL8 C5 .1uf /QB0 C6 .1uf Zo = 50 - TL9 R13 50 R14 50 Recommended for PCI Express Point-to-Point Connection Figure 7. 8741004I Schematic Example ©2016 Integrated Device Technology, Inc 15 Revision A January 27, 2016 8741004I Data Sheet Power Considerations This section provides information on power dissipation and junction temperature for the 8741004I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 741004I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (45mA + 12mA) = 197.5mW • Power (LVDS_output)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 80mA = 277.2mW • Power (HCSL_output)MAX = 44.5mW * 2 = 89mW Total Power_MAX = (3.465V, with all outputs switching) = 197.5mW + 277.2mW + 89mW = 563.7mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 32.1°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.564W * 32.1°C/W = 103.1°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 6. Thermal Resistance JA for 24 Lead TSSOP, E-Pad, Forced Convection JA Vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 32.1°C/W 25.5°C/W 24.0°C/W 3. Calculations and Equations. ©2016 Integrated Device Technology, Inc 16 Revision A January 27, 2016 8741004I Data Sheet The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 8. VDD IOUT = 17mA VOUT RREF = 475 ± 1% RL 50 IC Figure 8. HCSL Driver Circuit and Termination HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation, use the following equations which assume a 50 load to ground. The highest power dissipation occurs when VDD_MAX. Power = (VDD_MAX – VOUT) * IOUT, since VOUT – IOUT * RL = (VDD_MAX – IOUT * RL) * IOUT = (3.465V – 17mA * 50) * 17mA Total Power Dissipation per output pair = 44.5mW ©2016 Integrated Device Technology, Inc 17 Revision A January 27, 2016 8741004I Data Sheet Reliability Information Table 7. JA vs. Air Flow Table for a 24 Lead TSSOP, E-Pad JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 32.1°C/W 25.5°C/W 24.0°C/W Transistor Count The transistor count for 8741004I is: 1318 ©2016 Integrated Device Technology, Inc 18 Revision A January 27, 2016 8741004I Data Sheet Package Outline and Package Dimension Package Outline - G Suffix for 24 Lead TSSOP, E-Pad Table 8. Package Dimensions Symbol N A A1 A2 b b1 c c1 D E E1 e L P P1   bbb ©2016 Integrated Device Technology, Inc 19 All Dimensions in Millimeters Minimum Nominal Maximum 24 1.10 0.05 0.15 0.85 0.90 0.95 0.19 0.30 0.19 0.22 0.25 0.09 0.20 0.09 0.127 0.16 7.70 7.90 6.40 Basic 4.30 4.40 4.50 0.65 Basic 0.50 0.60 0.70 5.0 5.5 3.0 3.2 0° 8° 0.076 0.10 Revision A January 27, 2016 8741004I Data Sheet Ordering Information Table 9. Ordering Information Part/Order Number 8741004BGILF 8741004BGILFT Marking ICS8741004BIL ICS8741004BIL ©2016 Integrated Device Technology, Inc Package “Lead-Free” 24 Lead TSSOP, E-Pad “Lead-Free” 24 Lead TSSOP, E-Pad 20 Shipping Packaging Tray Tape & Reel Temperature -40C to 85C -40C to 85C Revision A January 27, 2016 8741004I Data Sheet Revision History Sheet Rev Table Page T3C 4 16 & 17 A A A T9 20 T9 1 11 Description of Change Date Added F_SEL Function Table. Power Considerations - updated Power Dissipation section to coincide with updates to the Calculations & Equations section on page 17. 5/29/08 Removed leaded parts from Ordering Information table 11/15/12 Removed ICS from part numbers where needed. General Description - Deleted ICS chip. Ordering Information - Deleted quantity from tape and reel. Deleted LF note below table. Updated header and footer. 1/27/16 ©2016 Integrated Device Technology, Inc 21 Revision A January 27, 2016 8741004I Data Sheet Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. 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