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TLV705, TLV705P
SBVS151F – DECEMBER 2010 – REVISED APRIL 2017
TLV705 200-mA, Low IQ, Low-Noise, Low-Dropout Regulator in Ultra-Small,
0.77-mm × 0.77-mm DSBGA and PicoStar™
1 Features
3 Description
•
The TLV705 series of low-dropout (LDO) linear
regulators are low quiescent current devices with
excellent line and load transient performance. These
devices
are
designed
for
power-sensitive
applications, with a precision band gap. An error
amplifier provides typical accuracy of 0.5%. Low
output noise, very high power-supply rejection ratio
(PSRR), and low dropout voltage make this series of
LDOs ideal for a wide selection of battery-operated
handheld equipment. All devices have a thermal
shutdown and current limit for safety.
1
•
•
•
•
•
•
•
•
Very Low Dropout:
– 105 mV at IOUT = 150 mA
– 145 mV at IOUT = 200 mA
Accuracy: 0.5% Typical
Low IQ: 35 μA
Available in Fixed-Output Voltages From
0.7 V to 4.8 V
VIN Range: 2 V to 5.5 V
High PSRR: 70 dB at 1 kHz
Stable With Effective Capacitance of 0.1 μF
Thermal Shutdown and Overcurrent Protection
Available in an Ultra-Low Profile (0.15-mm
Maximum Height) PicoStar Package Option
Furthermore, the TLV705 series is stable with an
effective output capacitance of only 0.1 μF. This
feature enables the use of cost-effective capacitors
that have higher bias voltage and temperature
derating. The devices regulate to the specified
accuracy with zero output load. The TLV705P series
also provides an active pulldown circuit to quickly
discharge output.
2 Applications
•
•
•
•
•
•
Wireless Handsets
Smart Phones
Zigbee® Networks
Bluetooth® Devices
Other Li-Ion Operated Handheld Products
WLAN and Other PC Add-On Cards
The TLV705 and TLV705P series are both available
in 0.77-mm × 0.77-mm DSBGA and PicoStar
packages with three height options that are optimal
for handheld applications.
Device Information(1)
PART NUMBER
TLV705
PACKAGE
BODY SIZE (NOM)
DSGBA (4)
0.77 mm × 0.77 mm
PicoStar (4)
0.77 mm × 0.77 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit (Fixed-Voltage Versions)
VOUT
VIN
Input
CIN
COUT
Output
1 mF
Ceramic
TLV705
On
Off
EN
GND
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV705, TLV705P
SBVS151F – DECEMBER 2010 – REVISED APRIL 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
1
1
1
2
4
5
9 Power Supply Recommendations...................... 16
10 Layout................................................................... 17
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
5
6
7
11 Device and Documentation Support ................. 19
Absolute Maximum Ratings .....................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1
7.2
7.3
7.4
8
8.2 Typical Application .................................................. 15
8.3 Do's and Don'ts ....................................................... 16
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
12
12
13
14
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
10.1
10.2
10.3
10.4
10.5
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Layout Guidelines ................................................. 17
Layout Example .................................................... 17
Power Dissipation ................................................. 17
Power Dissipation and Junction Temperature ...... 17
Estimating Junction Temperature ......................... 18
Device Support ....................................................
Documentation Support .......................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
20
20
20
20
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
12.1 Package Mounting ................................................ 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (May 2015) to Revision F
Page
•
Deleted "x" from TLV705 device in document title ................................................................................................................ 1
•
Changed package dimensions in document title from "0.8-mm × 0.8-mm" to "0.77-mm × 0.77-mm" .................................. 1
•
Changed ultra-low profile maximum height from 0.2-mm to 0.15-mm in Applications section ............................................. 1
•
Changed package dimensions in Description section from 0.8-mm to 0.77-mm. .................................................................. 1
•
Changed DSBGA package dimensions from "0.80 mm × 0.80 mm" to "0.77 mm × 0.77 mm" in the Device
Information table .................................................................................................................................................................... 1
•
Added copyright statement to the Typical Application Circuit ............................................................................................... 1
•
Changed formatting of Thermal Information table note ......................................................................................................... 5
•
Deleted "x" from device number in Thermal Information table .............................................................................................. 5
•
Added copyright statement to functional block diagrams in Functional Block Diagrams section ........................................ 12
•
Added copyright statement to Typical Application Circuit (Fixed-Voltage Versions) in the Typical Application section ..... 15
•
Changed formatting of document reference in Related Documentation section ................................................................. 19
•
Changed table header title from "Sample & Buy" to "Order Now" in the Related Links table ............................................ 19
Changes from Revision D (April 2015) to Revision E
Page
•
Added new package (YFM) to document .............................................................................................................................. 1
•
Added PicoStar to title ........................................................................................................................................................... 1
•
Changed last Features bullet ................................................................................................................................................. 1
•
Changed last sentence of Description section ...................................................................................................................... 1
•
Added second row to Device Information table ..................................................................................................................... 1
•
Added YFM pin out drawing ................................................................................................................................................... 4
•
Added YFM package to Thermal Information table ............................................................................................................... 5
•
Changed VO parameter units in Electrical Characteristics table: % for first row, mV for second row.................................... 6
2
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SBVS151F – DECEMBER 2010 – REVISED APRIL 2017
•
Changed first sentence of Overview section: removed new ............................................................................................... 12
•
Changed fifth sentence of Internal Current Limit section to clarify description of the shutdown circuit functionality .......... 13
•
Changed Vµs to V/µs in second paragraph of Start-Up Current section ............................................................................ 13
•
Changed it to the start-up current in third paragraph of Start-Up Current section .............................................................. 13
•
Changed INPUT to VIN in Power Supply Recommendations section .................................................................................. 16
•
Added Related Links section ............................................................................................................................................... 19
•
Added YFM package to Package Mounting section ........................................................................................................... 20
Changes from Revision C (October 2012) to Revision D
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Added Features bullet for VIN range ...................................................................................................................................... 1
•
Changed Applications list items ............................................................................................................................................. 1
•
Deleted Power Dissipation Ratings table .............................................................................................................................. 5
•
Changed y-axis unit measurement from ILIM to ICL for Figure 11............................................................................................ 7
•
Changed Figure 31 and deleted layout silkscreen images; replaced with image of PCB layout drawing. .......................... 17
•
Changed title for Figure 31 .................................................................................................................................................. 17
•
Changed title of Thermal Protection section ....................................................................................................................... 17
Changes from Revision B (December 2011) to Revision C
•
Page
Deleted last Features bullet.................................................................................................................................................... 1
Changes from Revision A (August 2011) to Revision B
Page
•
Added last Features bullet...................................................................................................................................................... 1
•
Changed last sentence of Description section ....................................................................................................................... 1
•
Added Mechanical Packages section (removed June 2013; packages are now automatically appended)........................... 1
•
Added YFP to title of pin out drawing ..................................................................................................................................... 4
•
Added YFP package to Thermal Information table ................................................................................................................ 5
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3
TLV705, TLV705P
SBVS151F – DECEMBER 2010 – REVISED APRIL 2017
www.ti.com
5 Pin Configuration and Functions
YFF, YFP Packages
4-Pin DSBGA
Top View
EN
YFM Package
4-Pin PicoStar
Top View
VIN
2
EN
VIN
GND
VOUT
A
B
2
GND
VOUT
1
1
A
B
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
GND
A1
—
EN
A2
I
Enable pin.
Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V places the regulator into
shutdown mode, which reduces the operating current to 1 μA (nominal).
VOUT
B1
O
Regulated output voltage pin.
Placing a small 1-μF ceramic capacitor is required from this pin to ground to ensure stability.
See Input and Output Capacitor Requirements for more details.
VIN
B2
I
Input pin.
TI recommends placing a small 1-µF capacitor from this pin to ground for good transient performance.
See Input and Output Capacitor Requirements for more details.
4
Ground pin.
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SBVS151F – DECEMBER 2010 – REVISED APRIL 2017
6 Specifications
6.1 Absolute Maximum Ratings
specified at TJ = –40°C to +125°C, unless otherwise noted. All voltages are with respect to GND. (1)
Voltage
(2)
Maximum output current
MIN
MAX
UNIT
VIN
–0.3
6
V
VEN
–0.3
6
V
VOUT
–0.3
6
V
IOUT
Internally limited
Output short-circuit duration
Indefinite
Temperature
(1)
(2)
Operating junction, TJ
–55
150
°C
Storage, Tstg
–55
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
All voltages are with respect to network ground pin.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
VIN
Input voltage
VOUT
Output voltage
IOUT
Output current
TJ
Junction temperature
NOM
MAX
UNIT
2
5.5
V
0.7
4.8
V
0
200
mA
–40
125
°C
6.4 Thermal Information
TLV705
THERMAL METRIC (1)
YFF, YFP
(DSBGA)
YFM
(PicoStar)
UNIT
4 PINS
4 PINS
RθJA
Junction-to-ambient thermal resistance
160
191.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
80
3.1
°C/W
RθJB
Junction-to-board thermal resistance
90
36.5
°C/W
ψJT
Junction-to-top characterization parameter
0.5
2.8
°C/W
ψJB
Junction-to-board characterization parameter
78
26.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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TLV705, TLV705P
SBVS151F – DECEMBER 2010 – REVISED APRIL 2017
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6.5 Electrical Characteristics
at TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 2 V (whichever is greater), IOUT = 10 mA, VEN = 0.9 V, and
COUT = 1 μF, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
VIN
Input voltage range
VOUT
Output voltage range
0.7
0 mA ≤ IOUT ≤ 200 mA, VOUT ≥ 1 V
DC output accuracy
–40°C ≤ TJ ≤ 125°C
ΔVOUT(ΔVIN)
Line regulation
VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V
ΔVOUT(ΔIOUT)
Load regulation
0 mA ≤ IOUT ≤ 200 mA
VDO
Dropout voltage (1)
VIN = 0.98 × VOUT(nom), IOUT = 200 mA
ICL
Output current limit
VOUT = 0.9 × VOUT(nom), TJ = 25°C
IGND
Ground pin current
ISHUTDOWN
Shutdown ground pin
current
PSRR
Power-supply
rejection ratio
0 mA ≤ IOUT ≤ 200 mA, VOUT < 1 V
–2% ±0.5%
–20
MAX
260
IOUT = 200 mA
V
4.8
V
2%
±5
20
mV
0.05
5
mV
mV
145
250
mV
400
550
mA
35
55
μA
315
VEN ≤ 0.4 V, 2 V ≤ VIN ≤ 4.5 V
UNIT
5.5
1
IOUT = 0 mA
1
μA
1.8
μA
VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA,
f = 10 kHz
80
dB
VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA,
f = 1 MHz
55
dB
BW = 100 Hz to
100 kHz, IOUT = 10 mA
Output noise voltage
BW = 10 Hz to 100 kHz,
IOUT = 10 mA
(2)
TYP
2
VO
Vn
MIN
VIN = 2.3 V, VOUT = 1.8 V
26.6
μVRMS
VIN = 3.3 V, VOUT = 2.8 V
26.7
μVRMS
VIN = 3.8 V, VOUT = 3.3 V
28.2
μVRMS
VIN = 2.3 V, VOUT = 1.8 V
30.7
μVRMS
VIN = 3.3 V, VOUT = 2.8 V
31.3
μVRMS
VIN = 3.8 V, VOUT = 3.3 V
34.1
μVRMS
tSTR
Start-up time
VHI
Enable high (enabled)
0.9
VIN
V
VLO
Enable low (disabled)
0
0.4
V
IEN
EN pin current
VEN = 5.5 V
UVLO
Undervoltage lockout
VIN rising
1.9
V
tSD
Thermal shutdown
temperature
Shutdown, temperature increasing
160
°C
Reset, temperature decreasing
140
°C
TJ
Operating junction
temperature
(1)
(2)
6
COUT = 1 μF, IOUT = 200 mA
100
μs
0.01
–40
μA
125
°C
VDO is measured for devices with VOUT(nom) = 2.35 V so that VIN = 2.3 V.
Start-up time = time from EN assertion to 0.98 × VOUT(nom).
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SBVS151F – DECEMBER 2010 – REVISED APRIL 2017
6.6 Typical Characteristics
over operating temperature range (TJ = –40°C to +125°C), IOUT = 10 mA, VEN = 0.9 V, COUT = 1 μF, and VIN = VOUT(nom) +
0.5 V or 2 V, whichever is greater, unless otherwise noted. Typical values are at TJ = 25°C.
1.90
1.90
VOUT = 1.8 V
IOUT = 10 mA
1.88
1.86
1.84
1.84
1.82
1.82
VOUT (V)
VOUT (V)
1.86
1.80
1.78
1.76
1.72
1.80
1.78
1.76
+125°C
+85°C
+25°C
-40°C
1.74
VOUT = 1.8 V
IOUT = 200 mA
1.88
+125°C
+85°C
+25°C
-40°C
1.74
1.72
1.70
1.70
2.1
2.6
3.1
3.6
4.1
VIN (V)
4.6
5.1
2.1
5.6
2.6
Figure 1. Line Regulation
1.90
3.6
4.1
VIN (V)
4.6
5.1
5.6
Figure 2. Line Regulation
250
VOUT = 1.8 V
1.88
3.1
IOUT = 200 mA
200
1.86
1.82
VDO (mV)
VOUT (V)
1.84
1.80
1.78
1.76
+125°C
+85°C
+25°C
-40°C
1.74
1.72
150
100
+125°C
+85°C
+25°C
-40°C
50
0
1.70
0
50
100
150
2
200
2.25 2.5 2.75
IOUT (mA)
3
3.25 3.5 3.75
4
4.25 4.5 4.75
VIN (V)
Figure 3. Load Regulation ( 0 mA ≤ IOUT ≤ 200 mA)
Figure 4. Dropout Voltage vs Input Voltage
140
1.90
VOUT = 4.8 V
VOUT = 1.8 V
1.88
120
1.84
80
1.82
VOUT (V)
VDO (mV)
1.86
100
60
40
+125°C
+85°C
+25°C
-40°C
20
0
1.80
1.78
1.76
10mA
150mA
200mA
1.74
1.72
1.70
0
50
100
IOUT (mA)
150
Figure 5. Dropout Voltage vs Output Current
200
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 6. Output Voltage vs Temperature
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Typical Characteristics (continued)
over operating temperature range (TJ = –40°C to +125°C), IOUT = 10 mA, VEN = 0.9 V, COUT = 1 μF, and VIN = VOUT(nom) +
0.5 V or 2 V, whichever is greater, unless otherwise noted. Typical values are at TJ = 25°C.
50
400
VOUT = 1.8 V
IOUT = 0 mA
45
40
300
35
30
IGND (mA)
IGND (mA)
VOUT = 1.8 V
350
25
20
15
+125°C
+85°C
+25°C
-40°C
10
5
250
200
150
+125°C
+85°C
+25°C
-40°C
100
50
0
0
2.3
2.7
3.1
3.5
3.9
VIN (V)
4.3
4.7
5.1
0
5.5
Figure 7. Ground Pin Current vs Input Voltage
50
100
IOUT (mA)
150
200
Figure 8. Ground Pin Current vs Output Current
2.5
VOUT = 1.8 V
IOUT = 0 mA
45
50
VOUT = 1.8 V
2
40
ISHDN (mA)
IGND (mA)
35
30
25
20
1.5
1
15
+125°C
+85°C
+25°C
-40°C
0.5
10
5
0
0
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
2.3
110 125
Figure 9. Ground Pin Current vs Temperature
2.7
3.1
3.5
3.9
VIN (V)
4.3
4.7
5.1
5.5
Figure 10. Shutdown Pin Current vs Input Voltage
500
100
VOUT = 1.8 V
VIN = 2.3 V
VOUT = 1.8 V
90
470
80
PSRR (dB)
ICL (mA)
70
440
+25°C
410
60
50
40
30
380
20
IOUT = 10 mA
IOUT = 150 mA
10
350
0
2.5
3
3.5
4
VIN (V)
4.5
5
Figure 11. Current Limit vs Input Voltage
8
5.5
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
Figure 12. Power-Supply Rejection Ratio vs Frequency
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Typical Characteristics (continued)
100
Output Spectral Noise Density (mV/ÖHz)
over operating temperature range (TJ = –40°C to +125°C), IOUT = 10 mA, VEN = 0.9 V, COUT = 1 μF, and VIN = VOUT(nom) +
0.5 V or 2 V, whichever is greater, unless otherwise noted. Typical values are at TJ = 25°C.
VOUT = 1.8 V
90
80
PSRR (dB)
70
60
50
40
30
1 kHz
10 kHz
100 kHz
20
10
0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
10
VOUT = 1.8 V
1
0.1
0.01
0
10
100
1k
Input Voltage (V)
Figure 13. Power-Supply Rejection Ratio vs Input Voltage
10 k
100 k
Frequency (Hz)
10 M
Figure 14. Output Spectral Noise Density vs Frequency
45
tR = tF = 1 ms
40
Integrated Noise (mVRMS)
1M
35
VOUT
30
(20 mV/div)
25
20
200 mA
15
(100 mA/div)
10
IOUT
Bandwidth: 100 Hz to 100 kHz
Bandwidth: 10 Hz to 100 kHz
5
0 mA
0
0.8
1.2
1.6
2
2.4
2.8
3.2
3.6
4
4.4
4.8
Time (200 ms/div)
VOUT (V)
Figure 15. Integrated Noise vs Output Voltage
Figure 16. Load Transient 0
tR = tF = 1 ms
tR = tF = 1 ms
(20 mV/div)
VOUT
VOUT
(20 mV/div)
200 mA
(50 mA/div)
(100 mA/div)
IOUT
IOUT
100 mA
1 mA
1 mA
Time (200 ms/div)
Time (200 ms/div)
Figure 17. Load Transient 1
Figure 18. Load Transient 3
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Typical Characteristics (continued)
over operating temperature range (TJ = –40°C to +125°C), IOUT = 10 mA, VEN = 0.9 V, COUT = 1 μF, and VIN = VOUT(nom) +
0.5 V or 2 V, whichever is greater, unless otherwise noted. Typical values are at TJ = 25°C.
Slew Rate = 1 V/ms
2.9 V
2.9 V
VIN
Slew Rate = 1 V/ms
VIN
(200 mV/div)
(200 mV/div)
2.3 V
(5 mV/div)
VOUT
2.3 V
(5 mV/div)
VOUT
Time (100 ms/div)
Time (100 ms/div)
Figure 19. Small-Step Line Transient (10 mA)
Figure 20. Small-Step Line Transient (200 mA)
IOUT = 0 mA
IOUT = 200 mA
C2
(1 V/div)
C2
(1 V/div)
C1
(1 V/div)
C1
(1 V/div)
C4
(100 mA/div)
C4
(100 mA/div)
Time (50 ms/div)
Time (10 ms/div)
Figure 21. VIN Inrush Current
Figure 22. VIN Inrush Current
Slew Rate = 1 V/ms
5.5 V
5.5 V
(2 V/div)
(5 mV/div)
(2 V/div)
VIN
VIN
2.3 V
VOUT
(5 mV/div)
2.3 V
VOUT
Slew Rate = 1 V/ms
Time (100 ms/div)
Time (100 ms/div)
Figure 23. Line Transient (10 mA)
10
Figure 24. Line Transient (200 mA)
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Typical Characteristics (continued)
over operating temperature range (TJ = –40°C to +125°C), IOUT = 10 mA, VEN = 0.9 V, COUT = 1 μF, and VIN = VOUT(nom) +
0.5 V or 2 V, whichever is greater, unless otherwise noted. Typical values are at TJ = 25°C.
VIN
(1 V/div)
VOUT
Time (100ms/div)
Figure 25. Power-Up and Power-Down
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7 Detailed Description
7.1 Overview
The TLV705 and TLV705P series of devices belong to a family of next-generation value low-dropout (LDO)
voltage regulators. These devices consume low quiescent current and deliver excellent line and load transient
performance. This performance, combined with low noise, very good PSRR with little (VIN – VOUT) headroom,
makes these devices ideal for RF portable applications. This family of regulators offers sub-band-gap output
voltages down to 0.7 V, current limit, and thermal protection, and are specified from –40°C to +125°C. The
TLV705P provides an active pulldown circuit to quickly discharge the outputs.
7.2 Functional Block Diagrams
VOUT
VIN
Current
Limit
Thermal
Shutdown
UVLO
EN
Bandgap
LOGIC
TLV705 Series
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 26. TLV705 Series
TLV705P Series
VOUT
VIN
Current
Limit
Thermal
Shutdown
120 Ω
UVLO
EN
Bandgap
LOGIC
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 27. TLV705P Series
12
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7.3 Feature Description
7.3.1 Internal Current Limit
The internal current limits of the TLV705 series help protect the regulator during fault conditions. During current
limit, the output sources a fixed amount of current that is largely independent of output voltage. In such a case,
the output voltage is not regulated, and can be measured as VOUT = ILIMIT × RLOAD. The PMOS pass transistor
dissipates [(VIN – VOUT) × ILIMIT] until a thermal shutdown is triggered and the device turns off. When the device
cools down, the internal thermal shutdown circuit turns the device back on. If the fault condition continues, the
device cycles between current limit and thermal shutdown; see Power Dissipation and Junction Temperature for
more details.
The PMOS pass element in the TLV705 has a built-in body diode that conducts current when the voltage at VOUT
exceeds the voltage at VIN. This current is not limited, so if extended reverse voltage operation is anticipated, TI
recommends external limiting to 5% of the rated output current.
7.3.2 Undervoltage Lockout (UVLO)
The TLV705 uses an UVLO circuit to keep the output shut off until the internal circuitry is operating properly.
7.3.3 Start-Up Current
The TLV705 uses a unique start-up architecture that creates a constant start-up time regardless of the output
capacitor. The start-up current is given by Equation 1. Equation 1 shows that start-up current is directly
proportional to COUT.
ISTARTUP = COUT (μF) × 0.06 (Vμs) + ILOAD (mA)
(1)
The output voltage ramp rate is independent of COUT and the load current, and has a typical value of 0.06 V/μs.
The TLV705 automatically adjusts the soft-start current to supply both the load current and the current to charge
COUT. For example, if ILOAD = 0 mA upon enabling the LDO, then ISTARTUP = 1 μF × 0.06 Vμs + 0 mA = 60 mA,
which is the current that charges the output capacitor.
However, if ILOAD = 200 mA, then ISTARTUP = 1 μF × 0.06 V / μs + 200 mA = 260 mA, which is the required current
to charge the output capacitor and supply the load current.
If the output capacitor and load increase such that the start-up current exceeds the output current limit, the startup current is clamped at the typical current limit of 400 mA. For example, if COUT = 10 μF and
IOUT = 200 mA, then 10 μF × 0.06 V / μs + 200 mA = 800 mA is not supplied and is instead clamped at 400 mA.
7.3.4 Dropout Voltage
The TLV705 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout
voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the
RDS(on) of the PMOS pass element. VDO approximately scales with the output current because the PMOS device
functions as a resistor in dropout.
As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout.
This effect is shown in Figure 13 in the Typical Characteristics.
7.3.5 Shutdown
The enable pin (EN) is active high. The device is enabled when the EN pin goes above 0.9 V. This relatively
lower value of voltage required to turn the LDO on can power the device with the GPIO of recent processors with
a GPIO voltage lower than traditional microcontrollers. The device is turned off when the EN pin is held at less
than 0.4 V. When shutdown capability is not required, EN can be connected to the VIN pin. The TLV705P version
has internal active pulldown circuitry that discharges the output with a time constant of:
τ = (120 × RL) / (120 + RL) × COUT
where
•
•
RL = load resistance
COUT = output capacitor
(2)
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7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
•
•
•
The input voltage is greater than the nominal output voltage added to the dropout voltage.
The output current is less than the current limit.
The input voltage is greater than the UVLO voltage.
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this condition, the output
voltage is the same the input voltage minus the dropout voltage. The transient performance of the device is
significantly degraded because the pass device is in a triode state and no longer regulates the output voltage of
the LDO. Line or load transients in dropout can result in large output voltage deviations.
Table 1 lists the conditions that lead to the different modes of operation.
Table 1. Device Functional Mode Comparison
OPERATING MODE
14
PARAMETER
VIN
IOUT
Normal mode
VIN > VOUT (nom) + VDO
IOUT < ICL
Dropout mode
VIN < VOUT (nom) + VDO
IOUT < ICL
Current limit
VIN > UVLO
IOUT > ICL
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV705 is a LDO that offers very low dropout voltages in a tiny package. The operating junction temperature
of this device is –40°C to +125°C.
8.2 Typical Application
VOUT
VIN
Input
CIN
COUT
Output
1 mF
Ceramic
TLV705
On
Off
EN
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 28. Typical Application Circuit (Fixed-Voltage Versions)
8.2.1 Design Requirements
Table 2 lists the design parameters.
Table 2. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
2.5 V to 3.3 V
Output voltage
1.8 V
Output current
100 mA
8.2.2 Detailed Design Procedure
Select the desired device based on the output voltage.
Provide an input supply with adequate headroom to account for dropout. The input supply must also provide
adequate current to account for the GND pin current and load current.
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8.2.2.1 Input and Output Capacitor Requirements
TI recommends using 1-μF X5R- and X7R-type ceramic capacitors because these components have minimal
variation in value and equivalent series resistance (ESR) over temperature. However, the TLV705 series is
designed to be stable with an effective capacitance of 0.1 μF or larger at the output. As a result, the device is
stable with capacitors of other dielectrics as long as the effective capacitance under the operating bias voltage
and temperature is greater than 0.1 μF. This effective capacitance refers to the capacitance that the LDO detects
under operating bias voltage and temperature conditions (that is, the capacitance after taking the bias voltage
and temperature derating into consideration). In addition to allowing the use of lower cost dielectrics, the effective
capacitance enables using smaller footprint capacitors that have higher derating in space-constrained
applications.
Using a 0.1-μF rating capacitor at the output of the LDO does not ensure stability because the effective
capacitance under operating conditions is less than 0.1 μF. Maximum ESR must be less than 200 mΩ.
Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1-μF to
1-μF low ESR capacitor across the VIN and GND pins of the regulator. This capacitor counteracts reactive input
sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor can be
necessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the power
source. If source impedance is more than 2 Ω, a 0.1-μF input capacitor may be necessary to ensure stability.
8.2.2.2 Transient Response
As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude,
but increases the duration of the transient response.
8.2.3 Application Curves
100
VIN = 2.3 V
VOUT = 1.8 V
90
80
VIN
PSRR (dB)
70
60
50
(1 V/div)
40
VOUT
30
20
IOUT = 10 mA
IOUT = 150 mA
10
0
10
100
1k
10k
100k
Frequency (Hz)
1M
Time (100ms/div)
10M
Figure 29. Power-Supply Rejection Ratio vs Frequency
Figure 30. Power-Up and Power-Down
8.3 Do's and Don'ts
Place input and output capacitors as close as possible to the device.
Do not exceed the device absolute maximum ratings.
9 Power Supply Recommendations
Connect a low output impedance power supply directly to the VIN pin of the TLV705. Inductive impedances
between the input supply and the VIN pin can create significant voltage excursions at the VIN pin during start-up
or load transient events.
16
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10 Layout
10.1 Layout Guidelines
Place input and output capacitors as close to the device pins as possible. To improve ac performance (such as
PSRR, output noise, and transient response), TI recommends designing the board with the input and output
capacitors on opposite sides of the device. In addition, connect the ground connection for the output capacitor
directly to the GND pin of the device. High ESR capacitors can degrade PSRR.
10.2 Layout Example
VOUT
VIN
COUT
EN
CIN
GND
Represents via used for
application-specific connections
Figure 31. Example PCB Layout
10.3 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the printed-circuit-board (PCB) layout. The PCB area around the device that is free of other components moves
the heat from the device to the ambient air. Performance data for JEDEC low and high-K boards are given in
Thermal Information. Using heavier copper increases the effectiveness in removing heat from the device. The
addition of plated through-holes to heat-dissipating layers also improves the thermal dissipation.
See for thermal performance on the TLV705 evaluation module (EVM). The EVM is a 2-layer board with two
ounces of copper per side.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of
the output current and the voltage drop across the output pass element, as shown in Equation 3:
PD = (VIN – VOUT) × IOUT
(3)
10.4 Power Dissipation and Junction Temperature
Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is enabled
again. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit can cycle on and off. This cycling limits the dissipation of the regulator, which protects the regulator from
damage as a result of overheating.
For reliable operation, limit junction temperature to 125°C (maximum). To estimate the margin of safety in a
complete design, increase the ambient temperature until the thermal protection is triggered; use worst-case loads
and signal conditions. For good reliability, trigger thermal protection at least 35°C above the maximum expected
ambient condition of the particular application. This configuration produces a worst-case junction temperature of
125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TLV705 is designed to protect against overload conditions. Continuously
running the TLV705 into thermal shutdown degrades device reliability.
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10.5 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly discussing thermal
resistances; rather, these metrics offer practical and relative means of estimating junction temperatures. These
psi metrics are determined to be significantly independent of the copper-spreading area. The key thermal metrics
(ΨJT and ΨJB) are given in Thermal Information and are used in accordance with Equation 4.
YJT: TJ = TT + YJT ´ PD
YJB: TJ = TB + YJB ´ PD
where:
•
•
•
18
PD is the power dissipated, as explained in Thermal Information.
TT is the temperature at the center-top of the device package, and
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge.
(4)
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TLV705.
The TLV70533EVM-596 evaluation module (and related user's guide) can be requested at the TI website through
the product folders or purchased directly from the TI eStore.
11.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TLV705 is available through the product folders under Tools
& Software.
11.1.2 Device Nomenclature
Table 3. Available Options (1)
(1)
PRODUCT
VOUT
TLV705xx(x)Pyyyz
xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits
are used in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 475
= 4.75 V).
P is optional; devices with P have an LDO regulator with an active output discharge.
yyy is package designator.
z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
11.2 Documentation Support
11.2.1 Related Documentation
•
TLV70533EVM-596 Evaluation Module User's Guide (SLVU439)
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TLV705
Click here
Click here
Click here
Click here
Click here
TLV705P
Click here
Click here
Click here
Click here
Click here
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11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
PicoStar is a trademark of Texas Instruments, Inc.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
Zigbee is a registered trademark of ZigBee Alliance.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12.1 Package Mounting
Solder pad footprint recommendations for the TLV705 are available from the Packaging Information page on TI's
website through the TLV705 series product folders. The recommended land patterns for the YFF, YFP, and YFM
packages are appended to this data sheet.
20
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV705075YFPR
ACTIVE
DSBGA
YFP
4
3000
RoHS & Green
SAC396
Level-1-260C-UNLIM
-40 to 125
3V
TLV705075YFPT
ACTIVE
DSBGA
YFP
4
250
RoHS & Green
SAC396
Level-1-260C-UNLIM
-40 to 125
3V
TLV70509YFPR
ACTIVE
DSBGA
YFP
4
3000
RoHS & Green
SAC396
Level-1-260C-UNLIM
-40 to 125
3W
TLV70509YFPT
ACTIVE
DSBGA
YFP
4
250
RoHS & Green
SAC396
Level-1-260C-UNLIM
-40 to 125
3W
TLV70512YFPR
ACTIVE
DSBGA
YFP
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
BU
TLV70512YFPT
ACTIVE
DSBGA
YFP
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
BU
TLV70515YFPR
ACTIVE
DSBGA
YFP
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
BV
TLV70515YFPT
ACTIVE
DSBGA
YFP
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
BV
TLV705165YFPR
ACTIVE
DSBGA
YFP
4
3000
RoHS & Green
SAC396
Level-1-260C-UNLIM
-40 to 125
CN
TLV705165YFPT
ACTIVE
DSBGA
YFP
4
250
RoHS & Green
SAC396
Level-1-260C-UNLIM
-40 to 125
CN
TLV705185YFPR
ACTIVE
DSBGA
YFP
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
YS
TLV705185YFPT
ACTIVE
DSBGA
YFP
4
250
RoHS & Green
SAC396
Level-1-260C-UNLIM
-40 to 125
YS
TLV70518PYFPR
ACTIVE
DSBGA
YFP
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
EV
TLV70518PYFPT
ACTIVE
DSBGA
YFP
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
EV
TLV70518YFMR
ACTIVE
DSLGA
YFM
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TLV70518YFMT
ACTIVE
DSLGA
YFM
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TLV70518YFPR
ACTIVE
DSBGA
YFP
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
WT
TLV70518YFPT
ACTIVE
DSBGA
YFP
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
WT
TLV70525PYFPR
ACTIVE
DSBGA
YFP
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
EK
TLV70525PYFPT
ACTIVE
DSBGA
YFP
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
EK
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Dec-2020
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV70525YFPR
ACTIVE
DSBGA
YFP
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
YB
TLV70525YFPT
ACTIVE
DSBGA
YFP
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
YB
TLV705285YFPR
ACTIVE
DSBGA
YFP
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
BW
TLV705285YFPT
ACTIVE
DSBGA
YFP
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
BW
TLV70528PYFPR
ACTIVE
DSBGA
YFP
4
3000
RoHS & Green
SAC396
Level-1-260C-UNLIM
-40 to 125
4E
TLV70528PYFPT
ACTIVE
DSBGA
YFP
4
250
RoHS & Green
SAC396
Level-1-260C-UNLIM
-40 to 125
4E
TLV70528YFPR
ACTIVE
DSBGA
YFP
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
WU
TLV70528YFPT
ACTIVE
DSBGA
YFP
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
WU
TLV70530YFMR
ACTIVE
DSLGA
YFM
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TLV70530YFMT
ACTIVE
DSLGA
YFM
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TLV70530YFPR
ACTIVE
DSBGA
YFP
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
XA
TLV70530YFPT
ACTIVE
DSBGA
YFP
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
XA
TLV70533PYFPR
ACTIVE
DSBGA
YFP
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
5L
TLV70533PYFPT
ACTIVE
DSBGA
YFP
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
5L
TLV70533YFFR
ACTIVE
DSBGA
YFF
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
US
TLV70533YFFT
ACTIVE
DSBGA
YFF
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
US
TLV70533YFMR
ACTIVE
DSLGA
YFM
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TLV70533YFMT
ACTIVE
DSLGA
YFM
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TLV70533YFPR
ACTIVE
DSBGA
YFP
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
VV
TLV70533YFPT
ACTIVE
DSBGA
YFP
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
VV
TLV70534YFPR
ACTIVE
DSBGA
YFP
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
B4
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Dec-2020
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV70534YFPT
ACTIVE
DSBGA
YFP
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
B4
TLV70536YFMR
ACTIVE
DSLGA
YFM
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TLV70536YFMT
ACTIVE
DSLGA
YFM
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TLV70536YFPR
ACTIVE
DSBGA
YFP
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
BX
TLV70536YFPT
ACTIVE
DSBGA
YFP
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
BX
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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