Programmable FemtoClock® NG LVPECL/LVDS
Dual 4-Output Fractional Clock Generator
IDT8T49N524I
DATA SHEET
General Description
Features
The IDT8T49N524I is an eight output programmable any-rate dual
clock generator with selectable LVDS or LVPECL outputs. Both clock
generators use Fractional Output Dividers to be able to generate output frequencies that are independent of each other and independent
of the input frequency. Output frequencies for both clock generators
are generated from a single crystal or reference clock.
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•
•
•
•
Fourth Generation FemtoClock® NG PLL technology
•
•
•
•
Input frequencies from 5MHz up to 800MHz
•
•
RMS phase jitter at 125MHz (12kHz - 20MHz): 0.282ps (typical)
•
•
•
•
•
Full 2.5V or 3.3V power supply
Clock Generator A supports three different factory-programmed
default frequencies that can be selected from using only the FSEL
control pins. Alternatively any desired output frequency can be
programmed over the I2C serial port. The chosen output frequency is
then driven out the QA0 to QA3 outputs.
Clock Generator B supports a single factory-programmed default
frequency. It can also be programmed for any output frequency via
the serial port. The output frequency is driven out the QB0 to QB3
outputs.
Some examples of frequency configurations that can be achieved
are shown in Table 5A. Please consult IDT for programming software
that can be used to determine the required settings for any desired
configuration.
Excellent phase noise performance is achieved with IDT’s fourth
Generation FemtoClock® NG PLL technology, which delivers
sub-0.5ps RMS phase jitter in the integer divide mode.
Eight outputs selectable as LVPECL or LVDS
Input selectable: fundamental mode crystal or clock reference
Supports fundamental mode crystals from 10MHz - 40MHz
CLK, nCLK input pair can accept the following differential input
levels: LVPECL, LVDS, HCSL
Two independent output frequencies can be generated
Output frequencies independent of each other and of input
Output frequencies from 15.234MHz - 645MHz, and
975MHz - 1290MHz, (See Table 5D for details)
RMS phase jitter at 156.25MHz (12kHz - 20MHz):
0.278ps (typical)
I2C programming interface
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
VCC / VCCA / VCCO
3.3V / 3.3V / 3.3V
3.3V / 3.3V / 2.5V (LVPECL only)
2.5V / 2.5V / 2.5V
VEE_B
QB3
nQB3
nQB2
QB2
nQB1
31
30 29 28 27 26 25 24 23 22 21
20
SCLK
32
19
VCC
SDATA
33
18
VEE
VEE
34
VCCA
35
LOCK
36
VEE
VCC
37
CLK_SEL
VEE_A
IDT8T49N524I
40 Lead VFQFN
17
6mm x 6mm x 0.925mm 16
4.65mm x 4.65mm EPad 15
NL Package
14
38
FSEL1
ADDR_SEL
FSEL0
nCLK
CLK
VEE
39
13
12
40
11
XTAL_IN
8
9 10
nQA3
XTAL_OUT
VEE_A
7
QA3
QA2
5 6
VCCO_A
nQA1
QA1
nQA0
3 4
nQA2
Top View
QA0
1
VCCO_B
VEE_B
1 2
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
QB1
nQB0
QB0
Pin Assignment
©2014 Integrated Device Technology, Inc.
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
IDT8T49N524I Data Sheet
Block Diagram
LOCK
QA0
nQA0
÷NINT_1[5:0]
Pulldown
CLK SEL
÷2
0
÷NFRAC_1[15:0]
nQA1
QA2
XTAL_IN
÷2
Xtal
Osc
XTAL_OUT
CLK
nCLK
QA1
0
1
x2
Pulldown
PU/PD
÷P[1:0]
1
1
Phase
Detector
+
Charge
Pump
nQA2
QA3
nQA3
FemtoClock® NG
0
VCO
QB0
÷2
1
nQB0
QB1
÷NINT_2[5:0]
÷MINT [8:1]
÷2
÷ NFRAC_2[15:0]
0
nQB1
QB2
nQB2
FSEL0
FSEL1
SCLK
SDATA
ADDR_SEL
Pulldown
Pulldown
Pullup
Pullup
Pulldown
Divider,
Output Type
&
Output
Enable
Selection
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
QB3
OUTPUT ENABLE
OUTPUT STYLE
2
8
nQB3
©2014 Integrated Device Technology, Inc.
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
IDT8T49N524I Data Sheet
Pin Description & Characteristics
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 2
QA0, nQA0
Output
Clock generator A differential output pair. LVPECL or LVDS interface levels.
3, 4
QA1, nQA1
Output
Clock generator A differential output pair. LVPECL or LVDS interface levels.
5
VCCO_A
Power
Clock generator A output supply pin.
6, 7
QA2, nQA2
Output
Clock generator A differential output pair. LVPECL or LVDS interface levels.
8, 9
QA3, nQA3
Output
Clock generator A differential output pair. LVPECL or LVDS interface levels.
10, 13, 18,
21, 31, 34,
37, 40
VEE
Power
Negative supply pins.
11,
12
XTAL_IN
XTAL_OUT
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
14
CLK
Input
Pulldown
Non-inverting differential clock input.
15
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input. Internal resistor bias to VCC/2.
16,
20
FSEL0,
FSEL1
Input
Pulldown
Frequency select pins. See Table 4A for frequency selection.
LVCMOS/LVTTL interface levels.
17
ADDR_SEL
Input
Pulldown
I2C Address select pin. LVCMOS/LVTTL interface levels.
19, 38
VCC
Power
Core supply pins.
22, 23
nQB3, QB3
Output
Clock generator B differential output pair. LVPECL or LVDS interface levels.
24, 25
nQB2, QB2
Output
Clock generator B differential output pair. LVPECL or LVDS interface levels.
26
VCCO_B
Power
Clock generator B output supply pin.
27, 28
nQB1, QB1
Output
Clock generator B differential output pair. LVPECL or LVDS interface levels.
29, 30
nQB0, QB0
Output
Clock generator B differential output pair. LVPECL or LVDS interface levels.
32
SCLK
Input
Pullup
I2C Clock Input. LVCMOS/LVTTL interface levels.
33
SDATA
Input/Output
Pullup
I2C Data Input. Input: LVCMOS/LVTTL interface levels. Output: Open
Drain.
35
VCCA
Power
Analog supply pin.
36
LOCK
Output
PLL Lock Indicator.
39
CLK_SEL
Input
Pulldown
Input source control pin. LVCMOS/LVTTL interface levels.
0 = Crystal is input source (default)
1 = CLK, nCLK input reference clock is input source
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
3.5
pF
RPULLDOWN
Input Pulldown Resistor
51
k
RPULLUP
Input Pullup Resistor
51
k
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
Test Conditions
3
Minimum
Typical
Maximum
Units
©2014 Integrated Device Technology, Inc.
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
IDT8T49N524I Data Sheet
Register Map
Table 3. I2C Register Map
Binary
Register
Register Address
Register Bit
D7
D6
D5
D4
D3
D2
D1
D0
0
00000
MINT0[7]
MINT0[6]
MINT0[5]
MINT0[4]
MINT0[3]
MINT0[2]
MINT0[1]
MINT0[0]
1
00001
MINT1[7]
MINT1[6]
MINT1[5]
MINT1[4]
MINT1[3]
MINT1[2]
MINT1[1]
MINT1[0]
2
00010
MINT2[7]
MINT2[6]
MINT2[5]
MINT2[4]
MINT2[3]
MINT2[2]
MINT2[1]
MINT2[0]
3
00011
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
4
00100
unused
unused
NINTB[5]
NINTB[4]
NINTB[3]
NINTB[2]
NINTB[1]
NINTB[0]
5
00101
unused
unused
unused
unused
unused
unused
DIVB_BYPASS
DIVB_INT
6
00110
NFRACB[7]
NFRACB[6]
NFRACB[5]
NFRACB[4]
NFRACB[3]
NFRACB[2]
NFRACB[1]
NFRACB[0]
7
00111
NFRACB[15]
NFRACB[14]
NFRACB[13]
NFRACB[12]
NFRACB[11]
NFRACB[10]
NFRACB[9]
NFRACB[8]
8
01000
NINTA_0[5]
NINTA_0[4]
NINTA_0[3]
NINTA_0[2]
NINTA_0[1]
NINTA_0[0]
CP0[1]
CP0[0]
9
01001
NINTA_1[5]
NINTA_1[4]
NINTA_1[3]
NINTA_1[2]
NINTA_1[1]
NINTA_1[0]
CP1[1]
CP1[0]
10
01010
NINTA_2[5]
NINTA_2[4]
NINTA_2[3]
NINTA_2[2]
NINTA_2[1]
NINTA_2[0]
CP2[1]
CP2[0]
11
01011
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
12
01100
OE_QB3
OE_QB2
OE_QB1
OE_QB0
OE_QA3
OE_QA2
OE_QA1
OE_QA0
13
01101
unused
unused
unused
unused
LVDS_SEL
PLL_BYPASS
P[1]
P[0]
14
01110
1
1
DOUBLER_
ENABLE
unused
unused
unused
DIVA_BYPASS
DIVA_INT
15
01111
unused
1
1
1
16
10000
NFRACA_0[15] NFRACA_0[14] NFRACA_0[13] NFRACA_0[12] NFRACA_0[11] NFRACA_0[10]
NFRACA_0[9]
NFRACA_0[8]
17
10001
NFRACA_1[15] NFRACA_1[14] NFRACA_1[13] NFRACA_1[12] NFRACA_1[11] NFRACA_1[10]
NFRACA_1[9]
NFRACA_1[8]
18
10010
NFRACA_2[15] NFRACA_2[14] NFRACA_2[13] NFRACA_2[12] NFRACA_2[11] NFRACA_2[10]
NFRACA_2[9]
NFRACA_2[8]
19
10011
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
20
10100
NFRACA_0[7]
NFRACA_0[6]
NFRACA_0[5]
NFRACA_0[4]
NFRACA_0[3]
NFRACA_0[2]
NFRACA_0[1]
NFRACA_0[0]
21
10101
NFRACA_1[7]
NFRACA_1[6]
NFRACA_1[5]
NFRACA_1[4]
NFRACA_1[3]
NFRACA_1[2]
NFRACA_1[1]
NFRACA_1[0]
22
10110
NFRACA_2[7]
NFRACA_2[6]
NFRACA_2[5]
NFRACA_2[4]
NFRACA_2[3]
NFRACA_2[2]
NFRACA_2[1]
NFRACA_2[0]
23
10111
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
unused
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
1
1
4
1
©2014 Integrated Device Technology, Inc.
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
IDT8T49N524I Data Sheet
Function Tables
Table 4A. Frequency Select Table
FSEL1
FSEL0
Pre-scaler
Ratio
Feedback
Divider Ratio
0 (default)
0 (default)
P
MINT0
NINTA_0
NFRACA_0
NINTB
NFRACB
0
1
P
MINT1
NINTA_1
NFRACA_1
NINTB
NFRACB
1
0
P
MINT2
NINTA_2
NFRACA_2
NINTB
NFRACB
1
1
QAn Operation
QBn Operation
Reserved
Table 4B. I2C Register Function Descriptions
Bits
Name
MINTn[7:0]
Integer Feedback Divider Register n
(n = 0...2)
Sets the integer feedback divider value. See Table 5B for the feedback
divider coding.
P[1:0]
Input Divider Register
Sets the PLL input divider. The divider value has the range of 1, 2, 4 and
8. See Table 5C for the divider coding.
NINTA_n[5:0]
Output Divider A - Integer Portion n
(n = 0...2)
Sets the integer portion of the output divider A. See Table 5D for the
output divider coding.
NFRACA_n[15:0]
Output Divider A - Fractional Portion
(n = 0...2)
Sets the fractional portion of the output divider A. See Table 5D for the
output divider coding.
NINTB[5:0]
Output Divider B - Integer Portion
NFRACB[15:0]
Output Divider B - Fractional Portion
CPn[1:0]
PLL Bandwidth n (n = 0...2)
OE_Qxx
Output Enable
LVDS_SEL
Output Style
Selects differential output style
0 = LVPECL (default)
1 = LVDS
PLL_BYPASS
PLL Bypass
Bypasses PLL. Input to phase detector is routed through output dividers
A and B to the output fanout buffers. Dividers should be programmed for
integer divide operation (DIVA_INT = DIVB_INT = 0) for proper operation.
DOUBLER_
ENABLE
Input Doubler
DIVA_BYPASS
Bypass Output Divider A
Bypasses output divider A. QAn output frequency is VCO/2.
DIVB_BYPASS
Bypass Output Divider B
Bypasses output divider B. QBn output frequency is VCO/2.
DIVA_INT
Divider A Integer Mode
Disables fractional portion of divider A. Setting this bit will provide better
phase noise performance in cases where the fractional portion is 0.
DIVB_INT
Divider B Integer Mode
Disables fractional portion of divider B. Setting this bit will provide better
phase noise performance in cases where the fractional portion is 0.
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
Function
Sets the integer portion of the output divider B. See Table 5D for the
output divider coding.
Sets the fractional portion of the output divider B. See Table 5D for the
output divider coding.
Sets the FemtoClock® NG PLL Charge Pump current to support the
selected operating frequency. See Table 5E.
Sets the desired output to Active or High impedance.
0 = Output is high-impedance (default)
1 = Output is active.
Enables the input frequency doubler.
0 = Input frequency presented directly to PLL
1 = Input frequency doubled before PLL (default)
5
©2014 Integrated Device Technology, Inc.
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
IDT8T49N524I Data Sheet
Frequency Configuration
The IDT8T49N524I is capable of being loaded with up to three
different frequency configurations. Use of the FSEL[1:0] inputs allows
a user to select from any of those three configurations at any time.
The three frequency configurations may be pre-loaded at the factory
or can be setup at any time over the I2C serial port. Table 5A shows
a number of example configurations.
It is recommended to use the IDT8T49N524I Configuration SW to
generate the desired configurations for the device.
Table 5A. Frequency Configuration Examples
Output Frequencies
(MHz)
Input or Crystal
Frequency (MHz)
Input Divider
P
Effective Feedback
Divider Ratio M
VCO Frequency
(MHz) fVCO
Effective Output
Divider Ratio N
62.5
25
1
100
2500
40
78.125
25
1
100
2500
32
100
25
1
96
2400
24
106.25
25
1
102
2550
24
125
25
1
100
2500
20
133.333
25
1
96
2400
18
150
25
1
96
2400
16
156.25
25
1
100
2500
16
166.666
25
1
80
2000
12
187.5
25
1
90
2250
12
200
25
1
96
2400
12
212.5
25
1
102
2550
12
250
25
1
100
2500
10
300
25
1
96
2400
8
312.5
25
1
100
2500
8
375
25
1
90
2250
6
400
25
1
96
2400
6
625
25
1
100
2500
4
1250
25
1
100
2500
2
30.72
25
1
88
2200
71.6145833333
61.44
25
1
88
2200
35.8072916667
76.8
25
1
88
2200
28.6458333333
122.88
25
1
88
2200
17.9153094463
148.5
25
1
88
2200
14.8148148148
153.6
25
1
88
2200
14.3229166667
155.52
25
1
88
2200
14.1460905350
159.375
25
1
88
2200
13.8039215686
160
25
1
88
2200
13.75
161.1328125
25
1
88
2200
13.6533333333
164.355
25
1
88
2200
13.3856590916
166.6285
25
1
88
2200
13.2030234924
184.32
25
1
88
2200
11.9357638889
311.04
25
1
88
2200
7.0730452675
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
6
©2014 Integrated Device Technology, Inc.
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
IDT8T49N524I Data Sheet
Table 5B. Feedback Divider MINTn Coding
Table 5C. Input Pre-scaler (P) Coding
Register Bit
Register Bit
MINTn[7:0]
Feedback Divide Ratio M
P1
P0
Input Pre-scaler Divide Ratio P
000000xx
Do Not Use
0
0
1
0000100
8
0
1
2
0000101
10
1
0
4
0000110
12
1
1
8
0000111
14
00001000 thru 11111111
16 thru 510
Table 5D. Output Divider NINTx and NFRACx Coding
Output Frequency
Frequency Divider N
fMIN (MHz)
Register Bit
fMAX (MHz)
NINTx[5:0]
Do Not Use
00000x
2
975
1290
xxxxxx (NOTE 2)
4
487.5
645
000010
6
325
430
000011
8 – 9.99999999 (NOTE 1)
195
322.5
000100
N – N +1.99999999
1950/ (N + 1.99999999)
2580 / N
...
126 - 127.99999999
15.234
20.476
111111
NOTE: When operating in Integer-mode, set NFRACx = 0, DIVA_INT = 1, and NINTx to desired output frequency configurations.
NOTE 1: When operating in fractional-mode, output frequency is limited to 322.5MHz. NFRACx must be set to 0 if NINTx = 000010 or 000011.
NOTE 2: The output divider is bypassed to generate frequencies in this range on the output. Set DIVx_INT and DIVx_BYPASS bits for the
desired output divider (A or B) for a ÷2 operation on that output bank.
Table 5E. Charge Pump CPn[1:0] Settings
Feedback Divider
(M) Value Range
Register Bit
CPn[1]
CPn[0]
Minimum
Maximum
0
0
16
48
0
1
49
100
1
0
101
192
1
1
193
510
NOTE: FemtoClock® NG PLL stability is only guaranteed over the feedback divider ranges listed in Table 5B.
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
7
©2014 Integrated Device Technology, Inc.
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
IDT8T49N524I Data Sheet
Power-up Default Configuration Description
The IDT8T49N524I supports a variety of options such as different
output styles, number of programmed default frequencies, output enable and operating temperature range. The device options and default frequencies must be specified at the time of order and are
programmed by IDT prior to shipment. The document, Programmable FemtoClock® NG Product Ordering Guide specifies the available
order codes.
Other order codes with respective programmed frequencies are
available from IDT upon request. After power-up changes to the
output frequencies, and state of outputs, active or high impedance,
are controlled by FSEL[1:0] or the I2C interface.
Serial Interface Configuration Description
The IDT8T49N524I has an I2C-compatible configuration interface to
access any of the internal registers (Table 3) for frequency and PLL
parameter programming. The IDT8T49N524I acts as a slave device
on the I2C bus and has the address 0b110111x, where x is set by the
value on ADDR_SEL input. (See Tables 6A & 6B). The interface
accepts byte-oriented block write and block read operations. An
address byte (P) specifies the register address (Table 3) as the byte
position of the first register to write or read. Data bytes (registers) are
accessed in sequential order from the lowest to the highest byte
(most significant bit first, see Table 6C, 6D). Read and write block
transfers can be stopped after any complete byte transfer. It is
recommended to terminate the I2C read or write transfer after
accessing byte #23 by sending a stop command.
For full electrical I2C compliance, it is recommended to use external
pull-up resistors for SDATA and SCLK. The internal pull-up resistors
have a size of 50K typical.
Table 6A. I2C Device Slave Address ADDR_SEL = 0 (default)
1
1
0
1
1
1
0
R/W
Table 6B. I2C Device Slave Address ADDR_SEL = 1
1
1
0
1
1
1
1
R/W
Table 6C. Block Write Operation
Bit
1
2:8
9
10
11:18
19
20:27
28
29-36
37
...
...
...
Description
START
Slave Address
W (0)
ACK
Address Byte P
ACK
Data
Byte (P)
ACK
Data
Byte
(P+1)
ACK
Data
Byte
...
ACK
STOP
Length (bits)
1
7
1
1
8
1
8
1
8
1
8
1
1
Table 6D. Block Read Operation
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39-46
47
...
...
...
Description
START
Slave
Address
W
(0)
A
C
K
Address
byte P
A
C
K
Repeated
START
Slave
address
R
(1)
A
C
K
Data Byte
(P)
A
C
K
Data Byte
(P+1)
A
C
K
Data Byte
...
A
C
K
STOP
Length (bits)
1
7
1
1
8
1
1
7
1
1
8
1
8
1
8
1
1
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
8
©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Rating
Supply Voltages, VCC, VCCA, VCCO_A, VCCO_B
3.6V
Inputs, VI
XTAL_IN
Other Input
0V to 2V
-0.5V to VCC + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Outputs, IO (LVDS)
Continuous Current
Surge Current
10mA
15mA
Outputs, IO (LVCMOS)
Continuous Current (LOCK)
Continuous Current (SDATA)
Surge Current (all)
12mA
10mA
22mA
Package Thermal Impedance, JA
32.4C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 7A. LVPECL Power Supply DC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VCC
Core Supply Voltage
VCCA
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
Analog Supply Voltage
VCC – 0.18
3.3
VCC
V
VCCO_A, VCCO_B
Output Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
264
300
mA
ICCA
Analog Supply Current
15
18
mA
Table 7B. LVPECL Power Supply DC Characteristics, VCC = VCCO_A = VCCO_B = 2.5V±5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VCC
Core Supply Voltage
VCCA
Minimum
Typical
Maximum
Units
2.375
2.5
2.625
V
Analog Supply Voltage
VCC – 0.17
2.5
VCC
V
VCCO_A, VCCO_B
Output Supply Voltage
2.375
2.5
2.625
V
IEE
Power Supply Current
256
290
mA
ICCA
Analog Supply Current
14
17
mA
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
Test Conditions
9
©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Table 7C. LVPECL Power Supply DC Characteristics,
VCC = 3.3V±5%, VCCO_A = VCCO_B = 2.5V±5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VCC
Core Supply Voltage
VCCA
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
Analog Supply Voltage
VCC – 0.18
3.3
VCC
V
VCCO_A, VCCO_B
Output Supply Voltage
2.375
2.5
2.625
V
IEE
Power Supply Current
264
300
mA
ICCA
Analog Supply Current
15
18
mA
Table 7D. LVDS Power Supply DC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V±5%, TA = -40°C to 85°C
Symbol
Parameter
VCC
Core Supply Voltage
VCCA
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
Analog Supply Voltage
VCC – 0.18
3.3
VCC
V
VCCO_A, VCCO_B
Output Supply Voltage
3.135
3.3
3.465
V
ICC
Power Supply Current
188
212
mA
ICCA
Analog Supply Current
15
18
mA
ICCO_A + ICCO_B
Output Supply Current
148
167
mA
Table 7E. LVDS Power Supply DC Characteristics, VCC = VCCO_A = VCCO_B = 2.5V±5%, TA = -40°C to 85°C
Symbol
Parameter
VCC
Core Supply Voltage
VCCA
Minimum
Typical
Maximum
Units
2.375
2.5
2.625
V
Analog Supply Voltage
VCC – 0.17
2.5
VCC
V
VCCO_A, VCCO_B
Output Supply Voltage
2.375
2.5
2.625
V
ICC
Power Supply Current
177
200
mA
ICCA
Analog Supply Current
14
17
mA
ICCO_A + ICCO_B
Output Supply Current
147
166
mA
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
Test Conditions
10
©2014 Integrated Device Technology, Inc.
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
IDT8T49N524I Data Sheet
Table 7F. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
IIL
Input
High Current
Input
Low Current
Test Conditions
Minimum
VCC = 3.3V
Typical
Maximum
Units
2
VCC + 0.3
V
VCC = 2.5V
1.7
VCC + 0.3
V
VCC = 3.3V
-0.3
0.8
V
VCC = 2.5V
-0.3
0.7
V
SCLK,
SDATA
VCC = VIN = 3.465V or 2.625V
5
µA
FSEL[1:0],
CLK_SEL,
ADDR_SEL
VCC = VIN = 3.465V or 2.625V
150
µA
SCLK,
SDATA
VCC = 3.465V or 2.625V, VIN = 0V
-150
µA
FSEL[1:0],
CLK_SEL,
ADDR_SEL
VCC = 3.465V or 2.625V, VIN = 0V
-5
µA
Table 7G. Differential DC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
IIH
Input
High Current
IIL
Input
Low Current
VPP
Peak-to-Peak Voltage:
NOTE 1
VCMR
Common Mode Input
Voltage; NOTE 1, NOTE 2
CLK, nCLK
Minimum
Typical
VCC = VIN = 3.465V or 2.625V
Maximum
Units
150
µA
nCLK
VCC = 3.465V or 2.625V, VIN = 0V
-150
µA
CLK
VCC = 3.465V or 2.625V, VIN = 0V
-5
µA
0.15
1.3
V
VEE + 0.5
VDD – 0.85
V
NOTE 1: VIL should not be less then -0.3V.
NOTE 2: Common mode input voltage is at the crosspoint.
Table 7H. LVPECL DC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VOH
Output High Voltage; NOTE 1
VOL
VSWING
Test Conditions
Minimum
Typical
Maximum
Units
VCCO_X – 1.1
VCCO_X – 0.75
V
Output Low Voltage; NOTE 1
VCCO_X – 2.0
VCCO_X – 1.6
V
Peak-to-Peak Output Voltage
Swing
0.6
1.0
V
NOTE: VCCO_X denotes VCCO_A and VCCO_B.
NOTE 1: Outputs terminated with 50 to VCCO_X – 2V.
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
11
©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Table 7I. LVPECL DC Characteristics, VCC = VCCO_A = VCCO_B = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VOH
Output High Voltage; NOTE 1
VOL
VSWING
Test Conditions
Minimum
Typical
Maximum
Units
VCCO_X – 1.2
VCCO_X – 0.75
V
Output Low Voltage; NOTE 1
VCCO_X – 2.0
VCCO_X – 1.6
V
Peak-to-Peak Output Voltage
Swing
0.5
1.0
V
NOTE: VCCO_X denotes VCCO_A and VCCO_B
NOTE 1: Outputs terminated with 50 to VCCO_X – 2V.
Table 7J. LVPECL DC Characteristics, VCC = 3.3V±5%, VCCO_A = VCCO_B = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VOH
Output High Voltage; NOTE 1
VOL
VSWING
Test Conditions
Minimum
Typical
Maximum
Units
VCCO_X – 1.2
VCCO_X – 0.75
V
Output Low Voltage; NOTE 1
VCCO_X – 2.0
VCCO_X – 1.5
V
Peak-to-Peak Output Voltage
Swing
0.5
1.0
V
Maximum
Units
454
mV
50
mV
1.375
V
50
mV
Maximum
Units
454
mV
50
mV
1.375
V
50
mV
Maximum
Units
40
MHz
50
18
pF
NOTE: VCCO_X denotes VCCO_A and VCCO_B
NOTE 1: Outputs termination with 50 to VCCO_X – 2V.
Table 7K. LVDS DC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VOD
Differential Output Voltage
VOD
VOD Magnitude Change
VOS
Output Low Voltage;
VOS
VOS Magnitude Change
Test Conditions
Minimum
Typical
247
1.15
Table 7L. LVDS DC Characteristics, VCC = VCCO_A = VCCO_B = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VOD
Differential Output Voltage
VOD
VOD Magnitude Change
VOS
Output Low Voltage;
VOS
VOS Magnitude Change
Test Conditions
Minimum
Typical
247
1.15
Table 8. Crystal Characteristics
Parameter
Test Conditions
Minimum
Mode of Oscillation
Fundamental
Frequency
10
Equivalent Series Resistance (ESR)
Load Capacitance (CL)
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
Typical
12
12
©2014 Integrated Device Technology, Inc.
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
IDT8T49N524I Data Sheet
AC Electrical Characteristics
Table 9. AC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V ± 5% or 2.5V ± 5% VEE = 0V, TA = -40°C to 85°
Symbol
Parameter
fDIFF_IN
Differential Input Frequency
fPFD
Phase / Frequency Detector
Frequency
fVCO
VCO Frequency
tjit(Ø)
tsk(b)
Test Conditions
RMS Phase Jitter, Random;
NOTE 1
Bank Skew;
NOTE 2, 3
5
800
MHz
5
100
MHz
1950
2580
MHz
ps
125MHz, Integration Range:
12kHz – 20MHz
0.282
0.383
ps
156.25MHz, Integration Range:
12kHz – 20MHz
0.278
0.371
ps
212.5MHz, Integration Range:
12kHz – 20MHz
0.341
0.734
ps
40
ps
25
ms
LVDS_SEL = 1
LVPECL Outputs
Output
Rise/Fall Time LVDS Outputs
Units
0.405
LVDS Outputs
tR / tF
Maximum
0.303
LVDS_SEL = 0
PLL Lock Time; NOTE 4
Typical
100MHz, Integration Range:
12kHz – 20MHz
LVPECL Outputs
tLOCK
Minimum
20% - 80%, LVDS_SEL = 0
100
400
ps
20% - 80%, LVDS_SEL = 1
100
400
ps
N
45
55
%
N>3
40
60
%
LVPECL
odc
Output Duty
Cycle
LVDS
LVPECL
LVDS
tS
Setup Time
SDATA to SCLK
5
ns
tH
Hold Time
SDATA from
SCLK
5
ns
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All Integer mode characterizations done using 25MHz, 12pf resonant Crystal.
NOTE: Output dividers using even integer divide ratios.
NOTE 1: Please refer to Phase Noise Plots.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: Refer to fLOCK in Parameter Measurement Information.
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
13
©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Typical Phase Noise at 125MHz
Noise Power (dBc / Hz)
125MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.282ps (typical)
Offset Frequency (Hz)
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
14
©2014 Integrated Device Technology, Inc.
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
IDT8T49N524I Data Sheet
Parameter Measurement Information
2V
2V
2V
2V
VCC,
VCCO_X
VCC,
VCCO_X
VCCA
VCCA
-1.3V+0.165V
-0.5V±0.125V
2.5V Core/2.5V LVPECL Output Load Test Circuit
3.3V Core/3.3V LVPECL Output Load Test Circuit
2.8V±0.04V
2V
2.8V±0.04V
VCC
Qx
VCCO_X
SCOPE
3.3V ±5%
VCCA
VCC,
V
VCCO_XCCA
nQx
VEE
-0.5V±0.125V
3.3V Core/3.3V LVDS Output Load Test Circuit
3.3V Core/2.5V LVPECL Output Load Test Circuit
VCC
SCOPE
VCC,
2.5V±5%
POWER SUPPLY
+ Float GND –
Qx
nCLK
VCCA
VCCO_X
CLK
nQx
VEE
Differential Input Levels
2.5V Core/2.5V LVDS Output Load Test Circuit
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
15
©2014 Integrated Device Technology, Inc.
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
IDT8T49N524I Data Sheet
Parameter Measurement Information, continued
PLL Lock Time
RMS Phase Jitter
nQx
nQx
80%
80%
VOD
Qx
20%
20%
tR
Qx
tF
LVPECL Output Rise/Fall Time
LVDS Output Rise/Fall Time
nQx
nQx
Qx
Qx
nQy
Qy
Differential Output Duty Cycle/Output Pulse Width/Period
Output Skew
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
16
©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Parameter Measurement Information, continued
Offset Voltage Setup
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
Differential Output Voltage Setup
17
©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
Crystal Inputs
LVPECL Outputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied from
XTAL_IN to ground.
All unused LVPECL output pairs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
CLK/nCLK Inputs
All unused LVDS output pairs can be either left floating or terminated
with 100 across. If they are left floating there should be no trace
attached.
LVDS Outputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK to ground.
It is recommended that CLK, nCLK be left unconnected in frequency
synthesizer mode.
LVCMOS Control Pins
All control pins have internal pullup or pulldown resistors; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
18
©2014 Integrated Device Technology, Inc.
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
IDT8T49N524I Data Sheet
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage V1= VCC/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the V1in the center of the input voltage swing. For
example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2
value should be adjusted to set V1 at 1.25V. The values below are for
when both the single ended swing and VCC are at the same voltage.
This configuration requires that the sum of the output impedance of
the driver (Ro) and the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First,
R3 and R4 in parallel should equal the transmission line impedance.
For most 50 applications, R3 and R4 can be 100. The values of
the resistors can be increased to reduce the loading for slower and
weaker LVCMOS driver. When using single-ended signaling, the
noise rejection benefits of differential signaling are reduced. Even
though the differential input can handle full rail LVCMOS signaling, it
is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger,
however VIL cannot be less than -0.3V and VIH cannot be more than
VCC + 0.3V. Though some of the recommended components might
not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal.
VCC
VCC
VCC
VCC
R3
100
Ro
RS
R1
1K
Zo = 50 Ohm
+
Driver
V1
Ro + Rs = Zo
R4
100
Receiv er
-
C1
0.1uF
R2
1K
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
19
©2014 Integrated Device Technology, Inc.
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
IDT8T49N524I Data Sheet
Overdriving the XTAL Interface
The XTAL_IN input can be overdriven by an LVCMOS driver or by one
side of a differential driver through an AC coupling capacitor. The
XTAL_OUT pin can be left floating. The amplitude of the input signal
should be between 500mV and 1.8V and the slew rate should not be
less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be
reduced from full swing to at least half the swing in order to prevent
signal interference with the power rail and to reduce internal noise.
Figure 2A shows an example of the interface diagram for a high
speed 3.3V LVCMOS driver. This configuration requires that the sum
of the output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
VCC
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50 applications,
R1 and R2 can be 100. This can also be accomplished by removing
R1 and changing R2 to 50. The values of the resistors can be increased to reduce the loading for a slower and weaker LVCMOS driver. Figure 2B shows an example of the interface diagram for an
LVPECL driver. This is a standard LVPECL termination with one side
of the driver feeding the XTAL_IN input. It is recommended that all
components in the schematics be placed in the layout. Though some
components might not be used, they can be utilized for debugging
purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input.
XTAL_OUT
R1
100
Ro
Rs
C1
Zo = 50 ohms
XTAL_IN
R2
100
Zo = Ro + Rs
.1uf
LVCMOS Driver
Figure 2A. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_OUT
C2
Zo = 50 ohms
XTAL_IN
.1uf
Zo = 50 ohms
LVPECL Driver
R1
50
R2
50
R3
50
Figure 2B. General Diagram for LVPECL Driver to XTAL Input Interface
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
20
©2014 Integrated Device Technology, Inc.
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
IDT8T49N524I Data Sheet
3.3V Differential Clock Input Interface
with the vendor of the driver component to confirm the driver
termination requirements. For example, in Figure 3A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 3A to 3E show interface examples
for the CLK/nCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. Please consult
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
Zo = 50Ω
nCLK
nCLK
Differential
Input
LVHSTL
IDT
LVHSTL Driver
R1
50Ω
R2
50Ω
Differential
Input
LVPECL
R1
50Ω
R2
50Ω
R2
50Ω
Figure 3B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 3A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
3.3V
3.3V
3.3V
3.3V
3.3V
Zo = 50Ω
CLK
CLK
R1
100Ω
nCLK
Differential
Input
LVPECL
Zo = 50Ω
nCLK
Receiver
LVDS
Figure 3D. CLK/nCLK Input Driven by a
3.3V LVDS Driver
Figure 3C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
3.3V
*R3
CLK
nCLK
HCSL
*R4
Differential
Input
Figure 3E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
21
©2014 Integrated Device Technology, Inc.
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
IDT8T49N524I Data Sheet
2.5V Differential Clock Input Interface
with the vendor of the driver component to confirm the driver
termination requirements. For example, in Figure 4A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 4A to 4E show interface examples
for the CLK/nCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. Please consult
2.5V
2.5V
2.5V
1.8V
Zo = 50
Zo = 50
CLK
CLK
Zo = 50
Zo = 50
nCLK
nCLK
Differential
Input
LVHSTL
IDT Open Emitter
LVHSTL Driver
R1
50
Differential
Input
LVPECL
R2
50
R1
50
R2
50
R3
18
Figure 4B. CLK/nCLK Input Driven by a
2.5V LVPECL Driver
Figure 4A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
2.5V
2.5V
2.5V
2.5V
2.5V
R3
250
R4
250
Zo = 50
*R3
33
Zo = 50
CLK
CLK
Zo = 50
Zo = 50
nCLK
nCLK
Differential
Input
LVPECL
R1
62.5
R2
62.5
HCSL
*R4
33
R1
50
R2
50
Differential
Input
*Optional – R3 and R4 can be 0
Figure 4D. CLK/nCLK Input Driven by a
2.5V HCSL Driver
Figure 4C. CLK/nCLK Input Driven by a
2.5V LVPECL Driver
2.5V
2.5V
Zo = 50
CLK
R1
100
Zo = 50
LVDS
nCLK
Differential
Input
Figure 4E. CLK/nCLK Input Driven by a
2.5V LVDS Driver
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
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©2014 Integrated Device Technology, Inc.
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
IDT8T49N524I Data Sheet
LVDS Driver Termination
For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90 and 132. The actual value
should be selected to match the differential impedance (Z0) of your
transmission line. A typical point-to-point LVDS design uses a 100
parallel resistor at the receiver and a 100 differential transmission-line environment. In order to avoid any transmission-line reflection issues, the components should be surface mounted and must be
placed as close to the receiver as possible. IDT offers a full line of
LVDS compliant devices with two types of output structures: current
source and voltage source. The standard termination schematic as
LVDS
Driver
shown in Figure 5A can be used with either type of output structure.
Figure 5B, which can also be used with both output types, is an optional termination with center tap capacitance to help filter common
mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is recommended to contact IDT
and confirm if the output structure is current source or voltage source
type. In addition, since these outputs are LVDS compatible, the input
receiver’s amplitude and common-mode input range should be verified for compatibility with the output.
ZO Z T
ZT
LVDS
Receiver
Figure 5A. Standard Termination
LVDS
Driver
ZO ZT
C
ZT
2 LVDS
ZT Receiver
2
Figure 5B. Optional Termination
LVDS Termination
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
23
©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are recommended only as guidelines.
functionality. These outputs are designed to drive 50 transmission
lines. Matched impedance techniques should be used to maximize
operating frequency and minimize signal distortion. Figures 6A and
6B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility
across all printed circuit and clock component process variations.
The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for
R3
125
3.3V
R4
125
3.3V
3.3V
Zo = 50
+
_
LVPECL
Input
Zo = 50
R1
84
Figure 6A. 3.3V LVPECL Output Termination
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
R2
84
Figure 6B. 3.3V LVPECL Output Termination
24
©2014 Integrated Device Technology, Inc.
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
IDT8T49N524I Data Sheet
Termination for 2.5V LVPECL Outputs
level. The R3 in Figure 7B can be eliminated and the termination is
shown in Figure 7C.
Figure 7A and Figure 7B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50
to VCCO – 2V. For VCCO = 2.5V, the VCCO – 2V is very close to ground
2.5V
VCCO = 2.5V
2.5V
2.5V
VCCO = 2.5V
R1
250
R3
250
50
+
50
+
50
–
50
2.5V LVPECL Driver
–
R1
50
2.5V LVPECL Driver
R2
62.5
R2
50
R4
62.5
R3
18
Figure 7A. 2.5V LVPECL Driver Termination Example
Figure 7B. 2.5V LVPECL Driver Termination Example
2.5V
VCCO = 2.5V
50
+
50
–
2.5V LVPECL Driver
R1
50
R2
50
Figure 7C. 2.5V LVPECL Driver Termination Example
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
25
©2014 Integrated Device Technology, Inc.
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
IDT8T49N524I Data Sheet
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 8. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed
on the PCB between the outer edges of the land pattern and the inner
edges of pad pattern for the leads to avoid any shorts.
pendent upon the package power dissipation as well as electrical
conductivity requirements. Thus, thermal and electrical analysis
and/or testing are recommended to determine the minimum number
needed. Maximum thermal and electrical performance is achieved
when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is
also recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process
which may result in voids in solder between the exposed pad/slug
and the thermal land. Precautions should be taken to eliminate any
solder voids between the exposed heat slug and the land pattern.
Note: These recommendations are to be used as a guideline only.
For further information, please refer to the Application Note on the
Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance
Lead frame Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the
surface of the PCB to the ground plane(s). The land pattern must be
connected to ground through these vias. The vias act as “heat pipes”.
The number of vias (i.e. “heat pipes”) are application specific and de-
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
LAND PATTERN
(GROUND PAD)
PIN
PIN PAD
Figure 8. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
26
©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Schematic Layout
Figure 9 (next page) shows an example IDT8T49N524I application
schematic that focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set. In this example, the input reference is LVDS and the outputs have
all been configured for LVPECL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1µF capacitor in each power pin filter and the resistor of the VDDA
power filters should be placed on the device side of the PCB and the
other components can be placed on the opposite side.
In this example a 12pF parallel resonant Fox FX325BS 25MHz
crystal is used with load caps C1 = C2 = 10pF. The load caps are
recommended for frequency accuracy, but these may be adjusted for
different board layouts. Crystals with different load capacities may be
used, but the load capacitors will have to be changed accordingly. If
different crystal types are used, please consult IDT for
recommendations.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequency. This
low-pass filter starts to attenuate noise at approximately 10kHz. If a
specific frequency noise component with high amplitude interference
is known, such as switching power supplies frequencies, it is
recommended that component values be adjusted and if required,
additional filtering be added. Additionally general design practice for
power plane voltage stability suggests adding bulk capacitances in
the general area of all devices.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The IDT8T49N524I provides
separate power supplies to isolate any high switching noise from
coupling into the internal PLL.
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
27
©2014 Integrated Device Technology, Inc.
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
IDT8T49N524I Data Sheet
3. 3V
FB2
1
2
V CCO
B L M18B B2 21 SN 1
C 23
0 .1 uF
FB 1
2
VC C
C 24
R4
10
BLM18 B B2 21SN 1
C 10
VC C A
10uF
3. 3 V
1
C9
0 .1 uF
10u F
C6
1 0uF
U1
39
17
C L K_ S EL
AD D _S EL
16
20
FS EL 0
FS EL 1
19
C LK_S EL
AD D _ S EL
V CC
38
FS EL0
FS EL1
35
26
LOC K
LOC K
RD2
1K
Zo = 50 Oh m
+
QA0
1
QA0
2
n QA0
Zo = 50 Oh m
n QA0
3 . 3V
3
QA1
4
n QA1
QA1
R1
4 . 7K
n QA1
R2
4. 7K
SD A TA
S C LK
Fox FX325BS Crystal
1
2
SD A TA
SC L K
6
QA2
n QA2
8
QA3
n QA3
XTAL _I N
X1
XTAL_ OU T
30
QB0
29
n QB0
QB0
12
XTAL _OU T
n QB0
C2
1 0pF
28
QB1
27
n QB1
25
QB2
24
n QB2
QB1
n QB1
Zo = 5 0 Ohm
14
R3
Zo = 5 0 Ohm
R6
50
R7
50
9
n QA3
11
3
R5
50
QA3
XTAL_ I N
25 MHz
(12pf)
4
n QA2
+3. 3 V PE C L R ec eiv er
7
QA2
33
32
C1
10p F
C 20
0. 1uF
36
To Logic
Input
pins
RD1
N o t In s t all
VC C O
C 22
0. 1uF
RU2
N ot I ns t all
To Logic
Input
pins
V CCO
VC C O_A
VC C O_B
RU1
1K
Place each 0.1uF bypass cap
directly ad jacent to its
correspondi ng VCC, VCCA,
VCCO_A or V CCO_B pin.
VC C A
5
Set Logic
Input t o '0'
VC C
C 11
0. 1 uF
C 14
0. 1uF
Logic C ontrol Input Examples
Set Logic
Input to '1'
VC C
C 13
0. 1uF
VC C A
VC C
VC C
V CC
100
QB2
C LK
2.5V
n QB2
15
nC LK
QB3
Z o = 50 Oh m
IN
50
0. 1u
23
QB3
22
n QB3
n QB3
L VD S D riv er
C 12
C 15
Z o = 50 Oh m
50
IN
0. 1u
R8
180
R9
18 0
41
10
13
18
21
31
34
37
40
V EE
VE E
VE E
V EE
V EE
VE E
VE E
V EE
ePAD
C ML R e c e iv e r
Opt ional 3. 3v PECL AC Ter mination
for PECL swing compliant 2. 5V CM L Receiver
Figure 9. IDT8T49N524I Application Schematic
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
28
©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
LVPECL Power Considerations
This section provides information on power dissipation and junction temperature for the IDT8T49N524I.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the IDT8T49N524I is the sum of the core power plus the power dissipated due to loading.
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading.
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 300mA = 1039.5mW
•
Power (outputs)MAX = 31.6mW/Loaded Output pair
If all outputs are loaded, the total power is 8 * 31.6mW = 252.8mW
Total Power_MAX (3.465V, with all outputs switching) = 1039.5mW + 252.8mW = 1292.3mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 27.9°C/W per Table 10 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.292W * 27.9°C/W = 121.1°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 10. Thermal Resistance JA for 40 Lead VFQFN, Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB; NOTE 1
0
1
2
27.9°C/W
21.6°C/W
19.1°C/W
NOTE 2
25.7°C/W
23.4°C/W
Multi-Layer PCB, JEDEC Standard
NOTE 1: JA simulation is performed with 4-layers, 8in. x 8in. PCB.
NOTE 2: JEDEC Standard requires air flow.
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
29
©2014 Integrated Device Technology, Inc.
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
IDT8T49N524I Data Sheet
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.
LVPECL output driver circuit and termination are shown in Figure 10.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
Figure 10. LVPECL Driver Circuit and Termination
To calculate power dissipation per output pair due to loading, use the following equations which assume a 50 load, and a termination voltage
of VCCO – 2V.
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.75V
(VCCO_MAX – VOH_MAX) = 0.75V
•
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.6V
(VCCO_MAX – VOL_MAX) = 1.6V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V – 0.75V)/50] * 0.75V = 18.75mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.6V)/50] * 1.6V = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 31.6mW
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
30
©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
LVDS Power Considerations
This section provides information on power dissipation and junction temperature for the IDT8T49N524I.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the IDT8T49N524I is the sum of the core power plus the analog power plus the power dissipated due to the load.
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
•
Power (core)MAX = VCC_MAX * (ICC_MAX + ICCA_MAX) = 3.465V * (212mA + 18mA) = 796.95mW
•
Power (outputs)MAX = VCCO_MAX * ICCO_MAX = 3.465V * 167mA = 578.66mW
Total Power_MAX = 796.95mW + 578.66mW = 1375.61mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 27.9°C/W per Table 11 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.376W * 27.9°C/W = 123.40°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 11. Thermal Resistance JA for 40 Lead VFQFN, Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB; NOTE 1
0
1
2
27.9°C/W
21.6°C/W
19.1°C/W
NOTE 2
25.7°C/W
23.4°C/W
Multi-Layer PCB, JEDEC Standard
NOTE 1: JA simulation is performed with 4-layers, 8in. x 8in. PCB.
NOTE 2: JEDEC Standard requires air flow.
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
31
©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Reliability Information
Table 12. JA vs. Air Flow Table for a 40 Lead VFQFN
JA by Velocity
Meters per Second
Multi-Layer PCB; NOTE 1
0
1
2
27.9°C/W
21.6°C/W
19.1°C/W
NOTE 2
25.7°C/W
23.4°C/W
Multi-Layer PCB, JEDEC Standard
NOTE 1: JA simulation is performed with 4-layers, 8in. x 8in. PCB.
NOTE 2: JEDEC Standard requires air flow.
Transistor Count
The transistor count for IDT8T49N524I is: 35,322
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
32
©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
40 Lead VFQFN Package Outline and Package Dimensions
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
33
©2014 Integrated Device Technology, Inc.
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
IDT8T49N524I Data Sheet
40 Lead VFQFN Package Outline and Package Dimensions, continued
40 Lead VFQFN, D2/E2 EPAD Dimensions: 4.65mm x 4.65mm
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
34
©2014 Integrated Device Technology, Inc.
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
IDT8T49N524I Data Sheet
Ordering Information
Table 13. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
8T49N524-dddNLGI
IDT8T49N524-dddNLGI
“Lead-Free” 40 Lead VFQFN
Tray
-40C to 85C
8T49N524-dddNLGI8
IDT8T49N524-dddNLGI
“Lead-Free” 40 Lead VFQFN
Tape & Reel
-40C to 85C
NOTE: For the specific -ddd order codes, refer to Programmable FemtoClock® NG Product Ordering Guide document.
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
35
©2014 Integrated Device Technology, Inc.
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
IDT8T49N524I Data Sheet
Revision History Sheet
Rev
Table
Page
A
1
A
T5D
12
T9
18
32
33
8, 35
A
T13
40
1
8
A
T13
A
35
2
Description of Change
Date
In footer, corrected year of date from 2012 to 2013.
4/2/2013
Features: Changed ‘Output frequencies from 15.5MHz - 650MHz, and 975MHz 1300MHz’ to ‘Output frequencies from 15.234MHz - 645MHz, and 975MHz - 1290MHz,
(See Table 5D for details)’
Changed fMAX column: 1300 to 1290; 650 to 645; 433.33333 to 430; 2600 to 2580;
20.635 to 20.476; NOTE 1: 325MHz to 322.5MHz.
fVCO: 1910MHz Min to 1950MHz Min; 2500MHz Max to 2580MHz Max
2nd paragraph: 18pF to 12pF
Updated Applications schematic to include Fox crystal
7/10/2013
Changed name of the IDT8T49N00xI Programmable FemtoClock® NG Product Ordering
Information document to Programmable FemtoClock® Ordering Product Information
Deleted quantity from Tape & Reel, Deleted Lead Free note.
8/21/2013
Changed title to Programmable FemtoClock® NG LVPECL/LVDS Dual 4-Output
Fractional Clock Generator.
Changed text from ‘Programmable FemtoClock® Ordering Product Information’ to
‘Programmable FemtoClock® NG Product Ordering Guide’.
Changed Note from ‘Programmable FemtoClock® Ordering Product Information’ to
‘Programmable FemtoClock® NG Product Ordering Guide’.
9/26/13
Block diagram - corrected FSELx pin names.
1/23/14
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
36
©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
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San Jose, California 95138
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800-345-7015 (inside USA)
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Fax: 408-284-2775
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Technical Support
netcom@idt.com
+480-763-2056
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product
features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in
customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or
safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners.
Copyright 2014. All rights reserved.
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