FemtoClock® NG Jitter Attenuator
and Clock Synthesizer
Description
Features
The 8V19N478 is a fully integrated FemtoClock NG jitter
attenuator and clock synthesizer designed as a high-performance
clock solution for conditioning and frequency/phase management
of 10/40/100/400 Gigabit-Ethernet line cards. The device is
optimized to deliver excellent phase noise performance as
required to drive physical layer devices, and provides the clean
clock frequencies of 625MHz, 500MHz, 312.5MHz, 250MHz,
156.25MHz, and 125MHz.
▪ High-performance clock RF-PLL:
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The 8V19N478 generates the output clock signals from the VCO
by frequency division. Four independent frequency dividers are
available; three support integer-divider ratios, and one integer as
well as fractional-divider ratios. Delay circuits can be used for
achieving alignment and controlled phase delay between clock
signals. The two redundant inputs are monitored for activity. Four
selectable clock switching modes are provided to handle clock
input failure scenarios. Auto-lock, individually programmable
output frequency dividers, and phase adjustment capabilities are
added for flexibility.
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The device is configured through an I2C interface and reports lock
and signal loss status in internal registers and via a lock detect
(LOCK) output. Internal status bit changes can also be reported
via the nINT output. The device is ideal for driving converter
circuits in wireless infrastructure, radar/imaging, and
instrumentation/medical applications. The device is a member of
the high-performance clock family from IDT.
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Typical Applications
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Sub 70fs – low phase noise clock generation
10/40/100 Gigabit-Ethernet line cards
Wireless Infrastructure
Reference clock for ADC and DAC circuits
Radar and Imaging
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Instrumentation and Medical
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©2018 Integrated Device Technology, Inc
Datasheet
• Optimized for low phase noise: -157.7dBc/Hz (1MHz offset;
A two-stage PLL architecture supports both jitter attenuation and
frequency multiplication. The first stage PLL is the jitter attenuator,
and uses an external VCXO for best possible phase noise
characteristics. The second stage PLL locks on the VCXO-PLL
output signal, and synthesizes the target frequency. This PLL has
a VCO circuit at 2500MHz.
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8V19N478
1
156.25MHz clock), design target
• Integrated phase noise, RMS (12kHz–20MHz): 73fs
(typical), design target
Dual-PLL architecture:
• 1st-PLL stage with external VCXO for clock jitter attenuation
• 2nd-PLL stage with internal FemtoClock NG PLL at
2500MHz
Four output banks with a total of 18 outputs, organized in:
• Three clock banks with one integer frequency divider and
four differential outputs
• One clock bank with one fractional divider and six
differential outputs
• One VCXO-PLL output bank with one selectable LVDS and
two LVCMOS outputs
Four output banks contain a phase delay circuit with steps of
the VCO clock period (400ps)
Supported clock output frequencies include:
• From the integer dividers: 2500MHz, 1250MHz, 625MHz,
500MHz, 312.5MHz, 250MHz, 156.25MHz, and 125MHz
• From the fractional divider: 80–300MHz
Low-power LVPECL and LVDS outputs support configurable
signal amplitude, DC and AC coupling, and LVPECL, LVDS,
and line termination techniques
Redundant input clock architecture:
• Two inputs
• Individual input signal monitor
• Digital holdover
• Manual and automatic clock selection
• Hitless switching
Status monitoring and fault reporting:
• Input signal status
• Hold-over and reference loss status
• Lock status with one status pin
• Mask-able status interrupt pin
Voltage supply:
• Device core supply voltage: 3.3V
• Output supply voltage: 3.3V, 2.5V, or 1.8V
• I/O voltage: 1.8V or 3.3V (selectable), and 3.3V tolerant
inputs when set to 1.8V
Package: 11 11 1 mm ball pitch 100-FPBGA
Temperature range: -40°C to +85°C
May 15, 2018
8V19N478 Datasheet
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Principles of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Phase-Locked Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Frequency Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VCXO-PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
FemtoClock NG PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Channel Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Redundant Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Input Re-Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Holdover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Manual Holdover Control (nHO_EN = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Automatic with Holdover (nHO_EN = 1, nM/A[1:0] = 11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Hold-off Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Revertive Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
VCXO-PLL Lock Detect (LOLV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
FemtoClock NG Loss-of-lock (LOLF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Differential Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Output Phase-Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Status Conditions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Serial Control Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Serial Control Port Configuration Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
I2C Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Device Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PLL Frequency Divider Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PLL Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Input Selection Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
General Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Clock Phase Noise Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
VCXO-PLL Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
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Step-by-step Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FemtoClock NG PLL Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVPECL-style Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVDS-Style Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Marking Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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8V19N478 Datasheet
Block Diagram
RZ
CLK_0
nCLK_0
CLK_1
nCLK_1
CP
Clock
Monitor
and
Selector
÷PV
÷MV
PFD
CP
EXT_SEL
VCXO-PLL
Loop Filter
VDD_LCF
8V19N478
CZ
BYPV
OSC
LFV
nOSC
÷PF
4.7µF
CR
FDF
x2
PFD
CP
fVCO
2400-2500MHz
LFF
Dual FemtoClockNG
÷MF
Holdover
CPF
CZF
FemtoClock NG
PLL Loop Filter
RZF
SRC
0
1
LFFR
QCLK_V
nQCLK_V
VCXO-PLL Channel
CLKA
CLKB
÷NA
(int)
÷NB
2.8k
CLKD
ADR0
ADR1
ADR2
ADR3
SCL
SDAT
I2C_A
QCLK_B[0:3]
nQCLK_B[0:3]
(int)
RES_CAL
CLKC
QCLK_A[0:3]
nQCLK_A[0:3]
÷NC
QCLK_C[0:3]
nQCLK_C[0:3]
(int)
÷ND
QCLK_D[0:5]
nQCLK_D[0:5]
(frac)
nINT
I2C
1.8V/3.3V
LOCK
Register
File
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8V19N478 Datasheet
Pin Assignments
Figure 1. Pin Assignments for 11 11 1 mm, 100-FPBGA Package (Bottom View)
A
nQCLK
_A0
QCLK
_A0
RES-CAL
VDD_CPV
nOSC
nQCLK_V
VDD_OSC
QCLK
_D0
QCLK
_D1
QCLK
_D2
B
nQCLK
_A1
QCLK_A1
EXT_SEL
LFV
OSC
QCLK_V
I2C_A
nQCLK
_D0
nQCLK
_D1
nQCLK
_D2
C
nQCLK
_A2
QCLK
_A2
GND
VDD_INP
LOCK
nINT
VDD_I2C
GND
QCLK
_D3
QCLK
_D4
D
nQCLK
_A3
QCLK
_A3
GND
CLK_0
CLK_1
ADR3
SDAT
GND
nQCLK
_D3
nQCLK
_D4
nQCLK
_D5
QCLK
_D5
E
VDDO
VDD
_QCLKA
_QCLKA
GND
nCLK_0
nCLK_1
ADR2
SCL
GND
F
GND
GND
GND
GND
GND
ADR1
ADR0
GND
G
nQCLK
_B0
QCLK
_B0
_QCLKB
VDD_CPF
GND
GND
GND
H
nQCLK
_B1
QCLK
_B1
_QCLKB
GND
CLDO
CBIAS
GND
J
nQCLK
_B2
QCLK
_B2
GND
GND
CR
VDD_LCV
K
nQCLK
_B3
QCLK
_B3
GND
LFF
LFFR
8
7
6
10
VDD
VDDO
9
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VDD
VDDO
_QCLKD
_QCLKD
GND
GND
_QCLKC
QCLK
_C0
nQCLK
_C0
GND
nQCLK
_C3
QCLK
_C1
nQCLK
_C1
VDD_LCF
GND
QCLK
_C3
QCLK
_C2
nQCLK
_C2
5
4
3
2
1
VDD
_QCLKC
VDDO
May 15, 2018
8V19N478 Datasheet
Pin Descriptions
Table 1. Pin Descriptions
[a]
Ball
Name
Type[b]
A10
nQCLK_A0
Output
A9
QCLK_A0
Output
Differential clock output A0 (Channel A). Configurable LVPECL, LVDS style and
amplitude. Output levels are determined by the VDDO_QCLKA supply voltage.
A8
RES_CAL
Analog
Connect a 2.8k (1%) resistor to GND for output current calibration.
A7
VDD_CPV
Power
Positive supply voltage (3.3V) for internal VCXO_PLL circuits.
A6
nOSC
Input (PD/ PU)
VCXO non-inverting and inverting differential clock input. Compatible with LVPECL,
LVDS and LVCMOS signals.
A5
nQCLK_V
Output
Differential VCXO-PLL clock outputs. Selectable LVPECL, LVDS (2x LVCMOS 1.8V)
style.
A4
VDD_OSC
Power
Positive supply voltage (3.3V) for the VCXO input.
A3
QCLK_D0
Output
Differential clock output D0 (Channel D). Configurable LVPECL, LVDS style and
amplitude. Output levels are determined by the VDDO_QCLKD supply voltage.
A2
QCLK_D1
Output
Differential clock output D1 (Channel D). Configurable LVPECL, LVDS style and
amplitude. Output levels are determined by the VDDO_QCLKD supply voltage.
A1
QCLK_D2
Output
Differential clock output D2 (Channel D). Configurable LVPECL, LVDS style and
amplitude. Output levels are determined by the VDDO_QCLKD supply voltage.
B10
nQCLK_A1
Output
B9
QCLK_A1
Output
Differential clock output A1 (Channel A). Configurable LVPECL, LVDS style and
amplitude. Output levels are determined by the VDDO_QCLKA supply voltage.
B8
EXT_SEL
Input (PD)
Clock reference select. 1.8V interface levels with hysteresis and 3.3V tolerance.
B7
LFV
Output
VCXO-PLL charge-pump output. Connect to the loop filter for the external VCXO.
B6
OSC
Input (PD)
VCXO non-inverting and inverting differential clock input. Compatible with LVPECL,
LVDS and LVCMOS signals.
B5
QCLK_V
Output
Differential VCXO-PLL clock outputs. Selectable LVPECL, LVDS/(2x LVCMOS 1.8V)
style.
B4
I2C_A
Input (PD/ PU)
B3
nQCLK_D0
Output
Differential clock output D0 (Channel D). Configurable LVPECL, LVDS style and
amplitude. Output levels are determined by the VDDO_QCLKD supply voltage.
B2
nQCLK_D1
Output
Differential clock output D1 (Channel D). Configurable LVPECL, LVDS style and
amplitude. Output levels are determined by the VDDO_QCLKD supply voltage.
B1
nQCLK_D2
Output
Differential clock output D2 (Channel D). Configurable LVPECL, LVDS style and
amplitude. Output levels are determined by the VDDO_QCLKD supply voltage.
C10
nQCLK_A2
Output
C9
QCLK_A2
Output
Differential clock output A2 (Channel A). Configurable LVPECL, LVDS style and
amplitude. Output levels are determined by the VDDO_QCLKA supply voltage.
C8
GND
Power
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
C7
VDD_INP
Power
Positive supply voltage (3.3V) for the differential inputs (CLK[1:0]).
C6
LOCK
Output
PLL lock detect status output for both PLLs. Selectable 1.8V/3.3V LVCMOS/LVTTL
interface levels.
C5
nINT
Output
Status output pin for signaling internal changed conditions. Selectable 1.8V/3.3V
LVCMOS/LVTTL interface levels.
©2018 Integrated Device Technology, Inc
Description
Serial Interface I2C addresses. Three-level signals (see Table 15).
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8V19N478 Datasheet
Table 1. Pin Descriptions (Cont.)[a]
Ball
Name
Type[b]
C4
VDD_I2C
Power
Positive supply voltage (3.3V) for I2C_A.
C3
GND
Power
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
C2
QCLK_D3
Output
Differential clock output D3 (Channel D). Configurable LVPECL, LVDS style and
amplitude. Output levels are determined by the VDDO_QCLKD supply voltage.
C1
QCLK_D4
Output
Differential clock output D4 (Channel D). Configurable LVPECL, LVDS style and
amplitude. Output levels are determined by the VDDO_QCLKD supply voltage.
D10
nQCLK_A3
Output
D9
QCLK_A3
Output
Differential clock output A3 (Channel A). Configurable LVPECL, LVDS style and
amplitude. Output levels are determined by the VDDO_QCLKA supply voltage.
D8
GND
Power
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
D7
CLK_0
Input (PD)
Device clock 0 inverting and non-inverting differential clock input. Inverting input is
biased to VDD_V/2 by default when left floating. Compatible with LVPECL, LVDS and
LVCMOS signals.
D6
CLK_1
Input (PD)
Device clock 1 inverting and non-inverting differential clock input. Inverting input is
biased to VDD_V/2 by default when left floating. Compatible with LVPECL, LVDS and
LVCMOS signals.
D5
ADR3
Input (PU/PD)
D4
SDAT
I/O (PU)
D3
GND
Power
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
D2
nQCLK_D3
Output
Differential clock output D3 (Channel D). Configurable LVPECL, LVDS style and
amplitude. Output levels are determined by the VDDO_QCLKD supply voltage.
D1
nQCLK_D4
Output
Differential clock output D4 (Channel D). Configurable LVPECL, LVDS style and
amplitude. Output levels are determined by the VDDO_QCLKD supply voltage.
E10
VDDO_QCLKA
Power
Output power supply voltage (3.3V, 2.5V or 1.8V) for the QCLK_A[3:0] outputs.
E9
VDD_QCLKA
Power
Positive supply voltage (3.3V) for Channel A.
E8
GND
Power
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
E7
nCLK_0
Input (PD/ PU)
Device clock 0 inverting and non-inverting differential clock input. Inverting input is
biased to VDD_V/2 by default when left floating. Compatible with LVPECL, LVDS and
LVCMOS signals.
E6
nCLK_1
Input (PD/ PU)
Device clock 1 inverting and non-inverting differential clock input. Inverting input is
biased to VDD_V/2 by default when left floating. Compatible with LVPECL, LVDS and
LVCMOS signals.
E5
ADR2
Input (PD/ PU)
Control input for output Bank D. 3-level signal (see Table 12 and Table 14).
E4
SCL
Input (PU)
E3
GND
Power
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
E2
nQCLK_D5
Output
E1
QCLK_D5
Output
Differential clock output D5 (Channel D). Configurable LVPECL, LVDS style and
amplitude. Output levels are determined by the VDDO_QCLKD supply voltage.
F10
GND
Power
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
F9
GND
Power
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
F8
GND
Power
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
©2018 Integrated Device Technology, Inc
Description
Device mode selection (see Table 12).
I2C data input/output. 1.8V interface levels with hysteresis and 3.3V tolerance
I2C clock input. 1.8V interface levels with hysteresis and 3.3V tolerance.
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8V19N478 Datasheet
Table 1. Pin Descriptions (Cont.)[a]
Ball
Name
Type[b]
F7
GND
Power
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
F6
GND
Power
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
F5
ADR1
Input (PD/ PU)
Control input for output Bank B. 3-level signal (see Table 12 and Table 14).
F4
ADR0
Input (PD/ PU)
Control input for output Bank A and Bank C. Three-level signal (see Table 12 and
Table 14).
F3
GND
Power
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
F2
VDD_QCLKD
Power
Positive supply voltage (3.3V) for Channel D.
F1
VDDO_QCLKD
Power
Output power supply voltage (3.3V, 2.5V or 1.8V) for the QCLK_D[5:0] outputs.
G10
nQCLK_B0
Output
G9
QCLK_B0
Output
Differential clock output B0 (Channel B). Configurable LVPECL, LVDS style and
amplitude. Output levels are determined by the VDDO_QCLKB supply voltage.
G8
VDD_QCLKB
Power
Positive supply voltage (3.3V) for Channel B.
G7
VDD_CPF
Power
Positive supply voltage (3.3V) for internal FemtoClock NG circuits.
G6
GND
Power
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
G5
GND
Power
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
G4
GND
Power
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
G3
VDD_QCLKC
Power
Positive supply voltage (3.3V) for Channel C.
G2
GND
Power
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
G1
GND
Power
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
H10
nQCLK_B1
Output
H9
QCLK_B1
Output
Differential clock output B1 (Channel B). Configurable LVPECL, LVDS style and
amplitude. Output levels are determined by the VDDO_QCLKB supply voltage.
H8
VDDO_QCLKB
Power
Output power supply voltage (3.3V, 2.5V or 1.8V) for the QCLK_B[3:0] outputs.
H7
GND
Power
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
H6
CLDO
Analog
Analog internal LDO bypass for VCO. Connect a 10µF capacitor to GND.
H5
CBIAS
Analog
Internal bias circuit for VCO. Connect a 4.7µF capacitor to GND.
H4
GND
Power
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
H3
VDDO_QCLKC
Power
Output power supply voltage (3.3V, 2.5V or 1.8V) for the QCLK_C[3:0] outputs.
H2
QCLK_C0
Output
H1
nQCLK_C0
Output
Differential clock output C0 (Channel C). Configurable LVPECL, LVDS style and
amplitude. Output levels are determined by the VDDO_QCLKC supply voltage.
J10
nQCLK_B2
Output
J9
QCLK_B2
Output
Differential clock output B2 (Channel B). Configurable LVPECL, LVDS style and
amplitude. Output levels are determined by the VDDO_QCLKB supply voltage.
J8
GND
Power
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
J7
GND
Power
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
J6
CR
Analog
Internal VCO regulator bypass capacitor. Use a 4.7µF capacitor between the CR and
the VDD_LCF terminals.
J5
VDD_LCV
Power
Positive supply voltage (3.3V) for the VCXO-PLL.
J4
GND
Power
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
©2018 Integrated Device Technology, Inc
Description
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8V19N478 Datasheet
Table 1. Pin Descriptions (Cont.)[a]
Ball
Name
Type[b]
J3
nQCLK_C3
Output
Differential clock output C3 (Channel C). Configurable LVPECL, LVDS style and
amplitude. Output levels are determined by the VDDO_QCLKC supply voltage.
J2
QCLK_C1
Output
J1
nQCLK_C1
Output
Differential clock output C1 (Channel C). Configurable LVPECL, LVDS style and
amplitude. Output levels are determined by the VDDO_QCLKC supply voltage.
K10
nQCLK_B3
Output
K9
QCLK_B3
Output
Differential clock output B3 (Channel B). Configurable LVPECL, LVDS style and
amplitude. Output levels are determined by the VDDO_QCLKB supply voltage.
K8
GND
Power
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
K7
LFF
Output
Loop filter/charge-pump output for the FemtoClock NG PLL. Connect to the external
loop filter.
K6
LFFR
Analog
Ground return path pin for the VCO loop filter.
K5
VDD_LCF
Power
Positive supply voltage (3.3V) for the internal oscillator of the FemtoClock NG PLL.
For essential information on power supply filtering, see Power Supply Filtering.
K4
GND
Power
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
K3
nQCLK_C3
Output
Differential clock output C3 (Channel C). Configurable LVPECL, LVDS style and
amplitude. Output levels are determined by the VDDO_QCLKC supply voltage.
K2
QCLK_C2
Output
K1
nQCLK_C2
Output
Differential clock output C2 (Channel C). Configurable LVPECL, LVDS style and
amplitude. Output levels are determined by the VDDO_QCLKC supply voltage.
Description
[a] For essential information on power supply filtering, see Power Supply Filtering.
[b] Pull-up (PU) and pull-down (PD) internal input resistors are indicated in parentheses. For typical values, see Input Characteristics, Table 41.
Principles of Operation
Overview
The device generates low-phase noise, synchronized clock output signals locked to an input reference frequency. The device contains
two PLLs with configurable frequency dividers. The first PLL (VCXO-PLL, suffix V) uses an external VCXO as the oscillator and provides
jitter attenuation. The external loop filter is used to set the VCXO-PLL bandwidth frequency in conjunction with internal parameters. The
second, low-phase noise PLL (FemtoClock NG, suffix F) multiplies the VCXO-PLL frequency to the VCO frequency of 2500MHz. The
FemtoClock NG PLL is completely internal and provides a central reference timing reference point for all output signals. From this point,
fully synchronous dividers generate the output frequencies.
The device has four output channels A – D, four channels with one integer output divider A – C and one channel with a fractional output
divider (D). The clock outputs are configurable with support for LVPECL and LVDS formats, and a variable output amplitude. In channels
A – D, the clock phase can be adjusted in phase. Individual outputs, channels, and unused circuit blocks support powered-down states
for operation at reduced power consumption. The register map, accessible through a selectable I2C interface with read-back capability
controls the main device settings and delivers device status information. For redundancy purpose, there are two selectable reference
frequency inputs and a configurable switch logic with manual, auto-selection, and holdover support.
©2018 Integrated Device Technology, Inc
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8V19N478 Datasheet
Phase-Locked Loop Operation
Frequency Generation
The 8V19N478 supports four operation modes: Dual-PLL and VCXO-PLL with jitter attenuation, frequency synthesis, and the buffer/
divider mode. Frequencies higher than the input frequency can be generated by the device by utilizing one or both PLLs. Using the
PLL(s) require(s) the user to set the frequency dividers to match input, VCXO and VCO frequency and to achieve frequency and phase
lock on the used PLLs. The frequency of the external VCXO is chosen by the user. The internal VCO frequency range is 2400–2500MHz.
Available frequency dividers for each of the four modes are displayed in Table 2. Example divider configurations are shown in Table 3 and
Table 4.
Dual-PLL Jitter Attenuation Mode: Input clock jitter is attenuated by the VCXO-PLL (1st stage PLL). The 2nd stage PLL (FemtoClock NG)
is locked to the 1st stage PLL and synthesizes a frequency in the range of 2400–2500MHz. Output dividers scale the frequency down to
the target frequency. Dividers PV, MV, PF, MF, Nx, and (optionally) ND require a user configuration. This is the main operation mode of the
device with the highest flexibility in frequency generation. Best phase noise is achieved with internal frequency doubler turned on.
VCXO-PLL Jitter Attenuation Mode: Input clock jitter is attenuated by the VCXO-PLL (1st stage PLL). The VCXO-output signal is divided
by the output dividers to the target frequency. Dividers PV, MV, and Nx require a user configuration. The VCXO sets the highest frequency
the device can achieve. The output phase noise is equivalent to the phase noise of the VCXO scaled by the output divider.
Frequency Synthesis Mode: The 1st stage PLL is bypassed. The 2nd stage PLL (FemtoClock NG) is directly locked to the input source
and synthesizes a frequency in the range of 2400–2500MHz. output dividers scale the frequency down to the target frequency. Dividers
PV, PF, MF, Nx, and (optionally) ND require a user configuration. This mode is recommend for applications with a low-jitter input source.
Divider/Buffer Mode: Both PLLs are bypassed. Output dividers scale the input frequency to the target frequency. Dividers PV and Nx
require a user configuration. In this mode, the PLL frequency specifications do not apply.
©2018 Integrated Device Technology, Inc
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8V19N478 Datasheet
Table 2. PLL Divider Values
Operation
Jitter Attenuation
Divider
Range
VCXO-PLL
Pre-Divider PV[a]
1…32767:
(15 bit)
VCXO-PLL
Feedback Divider
MV
1…32767:
(15 bit)
FemtoClock NG
Pre-Divider PF
1…63: (6 bit)
FemtoClock NG
Feedback
Dividers MF
8 …511: (9 bit)
VCXO-PLL
(BYPV 0,
SRC 1)
Dual-PLL
(BYPV 0, SRC 0)
Frequency
Synthesis
Divider/Buffer
VCXO-PLL bypassed
(BYPV 1, SRC 0)
Both PLLs bypassed
(BYPV 1, SRC 1)
Input clock frequency
f VCXO
f CLK = -------------------- P V
MV
No external VCXO required
Input clock
frequency:
VCXO frequency:
PF
f VCXO = f VCO --------MF
—
PF
f CLK = f VCO --------MF
[b]
fVCO: Note
PF: Note[c]
fVCO: Note[b]
PF: Note[c]
Output Divider Nx
(x [A:C])
1…160:
(Integer)[d]
Output frequency
Output frequency
Output frequency
f VCO
f OUT = -------------NX
f VCXO
f OUT = ------------------NX
f VCO
f OUT = -------------NX
Output Divider ND
Fractional
Divider[e]:
NINT: 4…24 – 1:
(Integer part)
Output frequency
NFRAC: 1…224 – 1:
(Fractional part)
Output frequency
f CLK
f OUT = ------------------------NX PV
f VCO
f OUT = -------------NE
—
NE
N FRAC
= 2 N INT + --------------------
224
[a] PV divider settings are in the PV0 register (for CLK_0), and in the PV1 register (for CLK_1). The PV divider is automatically loaded from PV0 or
PV1 according to the input selection (Clock Selection Settings, Table 11).
[b] fVCO 2400–2500MHz.
[c] Set PF to 0.5 in the equation if the frequency doubler is engaged (FDF 1).
[d] For a list of supported integer output dividers Nx (Table 8).
[e] Greatest ND fractional divider is 2 (14 [224 – 1] / 224) ≈ 29.99999988.
©2018 Integrated Device Technology, Inc
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8V19N478 Datasheet
VCXO-PLL
The prescaler PV and the VCXO-PLLs feedback divider MV require configuration to match the input frequency to the VCXO-frequency.
With the MV and PV divider value range of 15 bit, the device support is very flexible and supports a wide range of input and VCXOfrequencies.
In addition, the range of available inputs and feedback dividers allow to adjust the phase detector frequency independent of the used
input and VCXO frequencies (Table 3 and Table 4). The VCXO-PLL charge-pump current is controllable via internal registers, and can be
set in 50µA steps, from 50µA to 1.6mA. The VCXO-PLL can be bypassed (BYPV): when in bypass, the FemtoClock NG PLL locks to the
pre-divided input frequency.
Table 3. Example Configurations for fVCXO 125MHz
VCXO-PLL Divider Settings
Input Frequency (MHz)
PV
MV
fPFD (MHz)
19.44
486
3125
0.04
1
5
20
4
20
5
16
80
1.25
64
320
0.390625
1
1
125
5
5
25
25
25
5
125
125
1
5
4
31.25
50
40
3.125
500
400
0.3125
25
125
156.25
Table 4. Example Configurations for fVCXO 156.25MHz
VCXO- PLL Divider Settings
Input Frequency (MHz)
PV
MV
fPFD (MHz)
19.44
1944
15625
0.01
20
400
3125
0.05
4
25
6.25
40
250
0.625
400
2500
0.0625
4
5
31.25
40
50
3.125
400
500
0.3125
1
1
156.25
10
10
15.625
100
100
1.5625
25
125
156.25
©2018 Integrated Device Technology, Inc
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8V19N478 Datasheet
Table 5. VCXO-PLL Bypass Settings
BYPV
Operation
0
VCXO-PLL operation.
1
VCXO-PLL bypassed and disabled. The reference clock for the FemtoClock NG PLL is the selected input
clock. The input clock selection must be set to manual by the user. Clock switching and holdover are not
defined. The device synthesizes an output frequency, but will not attenuate input jitter. An external VCXO
component and loop filter is not required.
FemtoClock NG PLL
The FemtoClock NG PLL is the second stage PLL, and locks to the output signal of the VCXO-PLL (BYPV 0). It requires configuration from
the frequency doubler FDF, or the pre-divider PF and the feedback divider MF to match the VCXO-PLL frequency to the VCO frequency of
2500MHz. Best phase noise is typically achieved by engaging the internal frequency doubler (FDF 1, 2). If engaged, the signal from the first
PLL stage is doubled in frequency, increasing the phase detector frequency of the FemtoClock NG PLL. When the frequency doubler is
enabled, the frequency pre-divider PF is disabled. If the frequency doubler is not used (FDF 0), the PF pre-divider has to be configured.
Typically, the PF is set to 1 to keep the phase detector frequency as high as possible. Set the PF to other divider values to achieve specific
frequency ratios between the first and second PLL stage. This PLL is internally configured to high-bandwidth.
Table 6. Frequency Doubler
FDF
Operation
0
Frequency doubler off. The PF divides the clock signal from the VCXO-PLL or input (in bypass).
1
Frequency doubler on (2). A signal from the VCXO-PLL or input (in bypass) is doubled in frequency. The
PF divider has no effect.
Table 7. Example PLL Configurations
FemtoClock NG Divider Settings for VCO 2500MHz
VCXO-Frequency (MHz)
FDF
PF
MF
25
2
–
50
2
–
10
–
1
20
2
–
8
–
1
16
125
156.25
©2018 Integrated Device Technology, Inc
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8V19N478 Datasheet
Channel Frequency Divider
The device supports four independent output channels A–D. The channels A–C have one configurable integer frequency divider Nx
(x A – C), that divides the VCO frequency to the desired output frequency with very low phase noise. The integer divider values can be
selected from the range of 1 to 160 (Table 8). Channel D supports fractional divider ratios (Table 9).
Table 8. Integer Frequency Divider Settings
Channel Divider Nx[a]
Output Clock Frequency (MHz) for VCO 2500MHz
1
2500
2
1250
3
833.333
4
625
5
500
8
312.5
10
250
16
156.25
20
125
30
83.333
32
78.125
40
62.5
50
50
60
41.667
64
39.0625
80
31.25
100
25
120
20.833
128
19.53125
160
15.625
[a] x A – D.
Table 9. Typical Fractional Frequency Divider Settings
Channel Divider ND [a]
Output Clock Frequency (MHz) for VCO 2500MHz
15.51
161.1328125
18.75
133.333
[a] Greatest ND fractional divider is 2 (14 [224 – 1] / 224) ≈ 29.99999988.
Table 10. PLL Feedback Path Settings
SRC
Operation
0
The output divider input signal is the FemtoClock NG PLL.
1
The output divider input signal is the VCXO-PLL output signal. FemtoClock NG PLL is bypassed.
©2018 Integrated Device Technology, Inc
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8V19N478 Datasheet
Redundant Inputs
The two inputs are compatible with LVDS and LVPECL signal formats, and also support single-ended LVCMOS signals. For applicable
input interface circuits, see Applications Information.
Definitions
▪ Primary clock – The CLK_n input selected by the selection logic.
▪ Secondary clock – The CLK_n input not selected by the selection logic.
▪ PLL reference clock – The CLK_n input selected as the PLL reference signal by the selection logic. In automatic switching mode, the
selection can be overwritten by a state machine.
Monitoring
Loss of Input Signal (LOS)
In operation, a clock input is declared invalid (LOS) with the corresponding ST_CLK_n and LS_CLK_n indicator bits set after a specified
number of consecutive clock edges. If differential input signals are applied, the input will also detect an LOS condition in case of a zero
differential input voltage.
The device supports LOS detect circuits, one for each input. The signal detect circuits compare the signals at the CLK_0 and CLK_1
inputs to the internal frequency-divided signals from the VCXO-PLL (Figure 2). The loss-of-signal fault condition is declared upon three or
more missing clock input edges. LOS requires configuration of the N_MON[4:0] frequency divider setting to individually match the input
frequencies CLK_n to the VCXO frequency: fVCXO N_MON[4:0] fCLK_n. For instance, if one of the input frequencies is 25MHz and a
125MHz VCXO is used, set N_MON[4:0] 5. For configuration details see Table 11. Then, LOS is declared after three consecutive
missing clock edges. LOS is signaled through the ST_CLK_n (momentary) and LS_CLK_n (sticky, resettable) status bits. and can be
reported as an interrupt signal on the nINT output. The LOS circuit requires the jitter attenuation mode of the device (BYPV 0). LOS
does not detect frequency errors.
Figure 2. LOS Detect Circuit
fCLK_0
fCLK_1
CLK_0
nCLK_0
CLK_1
nCLK_1
÷PV
Input Select
N_MON[4:0]
÷1, ÷2, ..., ÷40
fVCXO
LOS
Detector 0
ST_CLK_0, LS_CLK_0
LOS
Detector 1
ST_CLK_1, LS_CLK_1
VCXO
Input Re-Validation
A clock input is declared valid and the corresponding LOS bit is reset after the clock input signal returned for user-configurable number of
consecutive input periods. This re-validation of the selected input clock is controlled by the CNTV setting (verification pulse counter).
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8V19N478 Datasheet
Clock Selection
The device supports five input selection modes: manual with and without holdover, short-term holdover, and two automatic switch modes.
Table 11. Clock Selection Settings
ST_REF
Description
ST_SEL
ST_CLKn
Name
nST_HOLD
Flags
nMA0
nMA1
nHO_EN
Mode
Application
Input selection follows user-configuration of the EXT_SEL pin or INT_SEL register bit as set by nEXT_INT with
holdover. Input selection is never changed by the internal state machine.
0
X
X
Manual
Holdover
Control
(default)
LOS on the primary reference clock:
Active reference stays selected, and the PLLs
may stall. The device will not go into holdover.
Manual change of the reference clock:
The device will go into holdover, and the
hold-off down-counter (CNTH) starts. The
device initiates a clock switch after expiration
of the hold-off counter. Duration of holdover is
set by CNTH CNTR / fVCXO. Holdover is
terminated even if the secondary clock input is
bad (LOS), (Manual Holdover Control
(nHO_EN = 0).
1
LOS
status
0[b]
Selected
input
Selected
input[c]
0[a]
LOS status
of selected
input
Startup and
external
selection
control with
holdover
Input selection follows user-configuration of the EXT_SEL pin or INT_SEL register bit as set by nEXT_INT.
Input selection is never changed by the internal state machine.
1
0
0
Manual
Control
LOS on the primary reference clock:
Active reference stays selected and the PLLs
may stall. Device will not go into holdover.
Manual change of the reference clock:
The device will not go into holdover and will
attempt to lock to the newly selected
reference.
1
LOS
status
1
Selected
input
0
Selected
input
Actual LOS
status of
selected
input
External
selection
control
Input selection follows LOS status. A failing input clock will cause an LOS event for that clock input. If the
selected clock has an LOS event, the device will immediately initiate a clock fail-over switch.
1
0
1
Automatic
LOS on the primary reference clock:
The device will switch to the secondary clock
without holdover. Input selection is
determined by a state machine and may differ
from the user’s clock selection.
No valid clock scenario: If no valid input
clocks exist, the device will not attempt to
switch, and will not enter the holdover state.
The PLL is not locked. Re-validation of all
input clocks will result in the PLL to attempt to
lock on that input clock (Revertive Switching).
Manual change of the reference clock:
The device will switch to the newly selected
clock without holdover. If the newly selected
clock is not valid, the PLL may stall.
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1
Selected
input
determined
by state
machine
Actual LOS
status of
selected
input
determined
by state
machine
1
Selected
input
Actual LOS
status of
selected
input
LOS
status
Multiple
inputs with
qualified
clock
signals
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8V19N478 Datasheet
Table 11. Clock Selection Settings (Cont.)
ST_REF
Description
ST_SEL
ST_CLKn
Name
nST_HOLD
Flags
nMA0
nMA1
nHO_EN
Mode
Application
Input selection follows user-configuration of EXT_SEL pin or INT_SEL register bit as set by nEXT_INT.
Selection is never changed by the internal state machine (see Holdover).
1
1
0
Short-term
Holdover
LOS on the primary reference clock:
A failing reference clock will cause an LOS
event. If the selected reference fails, the
device will enter holdover immediately.
Re-validation of the selected input clock is
controlled by the CNTV setting. A successful
re-validation will result in the PLL to re-lock on
that input clock.
0
LOS
status
For
holdover
duration
Selected
input
LOS status
for duration
of LOS until
revalidation
Use if a
single
reference is
occasionally
interrupted
Input selection follows LOS status. A failing input clock will cause an LOS event for that clock input. If the
selected clock has an LOS event, the device will go into holdover and switches input clocks after the hold-off
counter expires.
1
1
1
Automatic
with
Holdover
LOS on the primary reference clock, or
Manual change of the reference clock:
The device will go into holdover and the
hold-off down-counter (CNTH) starts. The
device initiates a clock fail-over switch to a
valid secondary clock input after expiration of
the hold-off counter. Duration of holdover is
set by CNTH CNTR/ fVCXO. The holdover is
terminated prior hold-off count-down if the
primary clock revalidates or is terminated by a
manual change of the reference clock. See
Automatic with Holdover (nHO_EN = 1,
nM/A[1:0] = 11), and Revertive Switching.
No valid clock scenario: The device remains
in holdover if the secondary input clock is
invalid.
0
LOS
status
For
holdover
duration
Selected
input
determined
by state
machine
Actual LOS
status of
selected
input
Multiple
inputs
[a] For the duration of an invalid input signal (LOS).
[b] For the duration of holdover.
[c] Delayed by holdover period.
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8V19N478 Datasheet
Holdover
In holdover state, the output frequency and phase is derived from an internal, digital value based on previous frequency and phase
information. Holdover characteristics are defined in Table 48.
Manual Holdover Control (nHO_EN 0)
This is the default switching mode of the device. The switch control is manual: The EXT_SEL pin or the INT_SEL bit as set by nEXT_INT
determines the selected reference clock input. If the selection is changed by the user, the device will enter holdover until the CNTH[7:0]
counter expires. Then, the new reference is selected (input switch). Application for this mode is startup and external selection control.
▪
▪
▪
▪
ST_REF – Status of selected reference clock
ST_CLK_n – Both will reflect the status of the corresponding input
ST_SEL – The new selection
nST_HOLD 0 for the duration of holdover
Automatic with Holdover (nHO_EN 1, nM/A[1:0] 11)
If an LOS event is detected on the active reference clock:
1. Holdover begins immediately
2. Corresponding ST_REF and LS_REF go low immediately
3. Hold-off countdown begins immediately
During this time, both input clocks continue to be monitored and their respective ST_CLK, LS_CLK flags are active. LOS events will be
indicated on ST_CLK, LS_CLK when they occur.
If the active reference clock resumes and is validated during the hold-off countdown:
1. Its ST_CLK status flag will return high and the LS_CLK is available to be cleared by an I 2C write of 1 to that register bit
2. No transitions will occur of the active REF clock; ST_SEL does not change
3. Revertive bit has no effect during this time (whether 0 or 1)
When the hold-off countdown reaches zero:
If the active reference has resumed and has been validated during the countdown, it will maintain being the active reference clock:
1. ST_SEL does not change
2. ST_REF returns to 1
3. LS_REF can be cleared by an I2C write of 1 to that register
4. Holdover turns off and the VCXO-PLL attempts to lock to the active reference clock
If the active reference has not resumed, but the other clock input CLK_n is validated, then:
1. ST_SEL1:0 changes to the new active reference
2. ST_REF returns to 1
3. LS_REF can be cleared by an I2C write of 1 to that register
4. Holdover turns off
If there is no validated CLK:
1. ST_SEL does not change
2. ST_REF remains low
3. LS_REF cannot be cleared by an I2C write of 1 to that register
4. Holdover remains active
Revertive capability returns if REVS 1.
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8V19N478 Datasheet
Hold-off Counter
A configurable down-counter applicable to the Automatic with Holdover and Manual with Holdover selection modes. The purpose of this
counter is a deferred, user-configurable input switch. The counter expires when a zero-transition occurs; this triggers a new reference
clock selection. The counter is clocked by the frequency-divided VCXO-PLL signal. The CNTR setting determines the hold-off counter
frequency divider and the CNTH setting the start value of the hold-off counter. For instance, set CNTR to a value of 131072 to achieve
953.67Hz (or a period of 1.048ms at fVCXO 125MHz): the 8-bit CNTH counter is clocked by 953.67Hz and the user-configurable hold-off
period range is:
0ms (CNTR 0x00) to 267ms (CNTR 0xFF). After the counter expires, it reloads automatically from the CNTH I2C register. After the
LOS status bit (LS_CLK_n) for the corresponding input CLK_n has been cleared by the user, the input is enabled for generating a new
LOS event.
The CNTR counter is only clocked if the device is configured in the clock selection modes, Automatic with Holdover and the selected
reference clock experiences an LOS event, or in the Manual with Holdover mode with manual switching. Otherwise, the counter is
automatically disabled (not clocked).
Revertive Switching
Revertive switching is only applicable to the two automatic switch modes shown in Table 11. Revertive switching enabled: Re-validation
of any non-selected input clock(s) will cause a new input selection according to the user-preset input priorities (revertive switch). An input
switch is only done if the re-validated input has a higher priority than the currently selected reference clock. Revertive switching disabled:
Re-validation of a non-selected input clock has no impact on the clock selection. The default setting is revertive switching disabled.
VCXO-PLL Lock Detect (LOLV)
The VCXO-PLL lock detect circuit uses the signal phase difference at the phase detector as Loss-of-lock criteria. Loss-of-lock is reported
if the actual phase difference is larger than a configurable phase detector window set by the LOCK_TH[14:0] configuration bits. A
Loss-of-lock state is reported through the nST_LOLV and nLS_LOLV status bits (Table 21). The VCXO-PLL lock detect function requires
to set FVCV 0.
Table 12.
ADR3 Selection Table
ADR3
Low
Device Mode
Default modes:
Outputs – disabled
Inputs – unused
Middle
Default frequency profile with 25MHz input
High
Default frequency profile with 20MHz input
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8V19N478 Datasheet
Inputs
Table 13.
Input Path Pin Configuration Table
SEL_BITS_MASTER (REG20,
D0)
X
0
0
1
ADR3
L
M
H
X
REFin
X
REF = 25MHZ
REF = 20MHZ
X
REG16[7:0], 17[6:0]
160
160
REG16[7:0], 17[6:0]
REF/ PV
156.25kHz
125kHz
REF/ PV
MV Divide
REG18[7:0], 19[6:0]
1000
1250
REG18[7:0], 19[6:0]
FB into PD
FB/ MV
156.25kHz
125kHz
FB/ MV
REG21[7:0], 22[6:0]
128
128
REG21[7:0], 22[6:0]
REG25[5:0]
X
X
REG25[5:0]
PF Doubler
REG25[7]
on
on
REG25[7]
REF into PD
0
312.5MHz
312.5MHz
0
REG26[7:0], 27[0]
8
8
REG26[7:0], 27[0]
0
312.5MHz
312.5MHz
0
BYPV
REG23[0]
off
off
REG23[0]
SRC
REG24[0]
on
on
REG24[0]
Polarity
REG28[7]
positive
positive
REG28[7]
FVCV
REG28[6]
off
off
REG28[6]
CPV
REG28[4:0]
750µA
750µA
REG28[4:0]
CPF
REG30[4:0]
5.8mA
5.8mA
REG30[4:0]
N_MON
REG32[7:3]
8
8
REG32[7:3]
0
19.5MHz
19.5MHz
0
MODE_BLOCK
REG32[2]
on
on
REG32[2]
nHO_EN
REG32[1]
off
off
REG32[1]
nEXT_INT
REG32[0]
external
external
REG32[0]
nMA[1:0]
REG33[3:2]
manual
manual
REG33[3:2]
CNTV
REG35[1:0]
2
2
REG35[1:0]
PV Divide
REF into PD
lock_th
Resulting Path Configuration
PF
MF
FB into PD
LOS Monitoring Frequency
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8V19N478 Datasheet
Table 14. Output Frequency Pin Configuration Table
Output Bank A and C
ADR0
Output Type
Divide Ratio
FOUT (MHz)
Swing Level
Total outputs per
bank: 4, with 1 integer
divider
Low
LVPECL
20
125
750mV
Middle
LVDS
16
156.25
500mV
High
LVPECL
16
156.25
750mV
Output Bank B
ADR1
Output Type
Divide Ratio
FOUT (MHz)
Swing Level
Total of 4 outputs with
1 integer divider
Low
LVPECL
20
125
750mV
Middle
LVDS
16
156.25
500mV
High
LVPECL
16
156.25
750mV
Output Bank D
ADR2
Output Type
Divide Ratio
FOUT (MHz)
Swing Level
Total of 6 outputs with
1 fractional divider
Low
LVPECL
20
125
750mV
Middle
LVDS
16
156.25
500mV
High
LVPECL
16
156.25
750mV
Table 15.
I2C Address Selection Table
I2C_A
Output Type
I2C_A[1]
I2C_A[0]
Low
Address 1
0
0
Middle
Address 2
0
1
High
Address 3
1
1
The 8V19N478 can be configured via pin or I2C. ADR3/2/1/0 provides a specific set of configuration options for input and output paths. In
addition, the initialization sequence of the device is controlled by the ADR3 pin and the synchronization of the outputs by transition from
Low to Middle or High.
Table 16. Initialization Sequence Control
Initialization
In Pin Mode, Triggered by:
init_clk
(Pin I2C_A3 = M or H) + IBM die powered up
pb_cal
(Pin I2C_A3 = M or H) + IBM die powered up
relock
Completion of init_clk sequence (above)
OE
Completion of init_clk sequence (above)
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8V19N478 Datasheet
The pin configuration is overridden by I2C programming of the register map. The I2C_A pin set the Address as shown in following table.
Table 17. I2C Address
1
I2C_A1
I2C_A0
R
W
I2C_A
D8, D9
1101
1
0
0
1
0
L
Address 1
DA, DB
1101
1
0
1
1
0
M
Address 2
DE, DF
1101
1
1
1
1
0
H
Address 3
The default values of the register map are Read back by the I2C in the Pin-Strap configuration mode.
FemtoClock NG Loss-of-lock (LOLF)
FemtoClock NG-PLL loss-of-lock is signaled through the nST_LOLF (momentary), and nLS_LOLF (sticky, resettable) status bits, and can
reported as hardware signal on the LOCK_V output as well as an interrupt signal on the nINT output.
Differential Outputs
Table 18. Output Features
Output
Style
LVPECL
QCLK_y
Disable
Power Down
Yes
LVDS
350 – 850mV
4 steps
Yes
Yes
LVCMOS[c]
1.8V
Yes
Yes
LVDS
Termination
50 to VTT[b]
350 – 850mV
4 steps
LVPECL
QCLK_V
Amplitude[a]
Yes
100 differential
—
50 to VTT
100 differential
—
[a] Amplitudes are measured single-ended.
[b] For VTT (Termination voltage) values (see Table 50).
[c] LVCMOS style: nQCLK_V and QCLK_V are complementary.
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8V19N478 Datasheet
Off
0
On
State
X
100 differential or no termination
X
Off
0
1
100 differential (LVDS)
50 to VTT[d] (LVPECL)
A[1:0]
1
Termination
Enable
Output Power
STYLE
PD[a]
Table 19. Individual Clock Output Settings
[c]
0
Disable
1
Enable
Amplitude (mV)[b]
X
X
XX
X
00
350
01
500
10
700
11
850
0
Disable
XX
X
1
Enable
00
350
01
500
10
700
11
850
[a] Power-down modes are available for the individual channels A – D and the outputs QCLK_y (A0 – D3).
[b] Output amplitudes of 700mV and 850mV require a 3.3V output supply (VDDO_V). 350mV and 500mV output amplitudes support
VDDO_V 2.5V and 1.8V.
[c] Differential output is disabled in static low/high state.
[d] For VTT (Termination voltage) values, see Table 50.
Output Phase-Delay
Output phase delay is supported in each channel. The selected VCO frequency sets the delay unit to 1/fVCO.
Table 20. Delay Circuit Settings
Delay Circuit
Clock Phase CLK_x
Unit
1
--------------f VCO
fVCO 2500MHz:
400ps
©2018 Integrated Device Technology, Inc
Steps
Range
256
0–102ns
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8V19N478 Datasheet
Status Conditions and Interrupts
The 8V19N478 has an interrupt output to signal changes in status conditions. Settings for status conditions may be accessed in the
Status registers. The device has several conditions that can indicate faults and status changes in the operation of the device. These are
shown in Table 21 and can be monitored directly in the status registers. Status bits (named: ST_condition) are read-only and reflect the
momentary device status at the time of read-access. Several status bits are also copied into latched bit positions (named: LS_condition).
The latched version is controlled by the corresponding fault and status conditions and remains set (“sticky”) until reset by the user by
writing “1” to the status register bit. The reset of the status condition has only an effect if the corresponding fault condition is removed,
otherwise, the status bit will set again. Setting a status bit on several latched registers can be programmed to generate an interrupt signal
(nINT) via settings in the Interrupt Enable bits (named: IE_condition). A setting of “0” in any of these bits will mask the corresponding
latched status bits from affecting the interrupt status pin. Setting all IE bits to 0 has the effect of disabling interrupts from the device.
Table 21. Status Bit Functions
Status Bit
Function
Status if Bit is:
1
0
Interrupt
Enable Bit
CLK 0 input status
Active
LOS
IE_CLK_0
LS_CLK_1
CLK 1 input status
Active
LOS
IE_CLK_1
nST_LOLV
nLS_LOLV
VCXO-PLL loss of lock
Locked
Loss-of-lock
IE_LOLV
nST_LOLF
nLS_LOLF
FemtoClock NG-PLL loss of lock
Locked
Loss-of-lock
IE_LOLF
nST_HOLD
nLS_HOLD
Holdover
Not in holdover
Device in holdover
IE_HOLD
ST_VCOF
—
FemtoClock NG VCO calibration
Not completed
Completed
—
ST_SEL
—
Clock input selection
ST_REF
LS_REF
PLL reference status
Momentary
Latched
ST_CLK_0
LS_CLK_0
ST_CLK_1
Description
0 CLK_0
1 CLK_1
Valid reference[a]
—
Reference lost
IE_REF
[a] Manual and short-term holdover mode: 0 indicates if the selected reference is lost, 1 if not lost.
Automatic mode: will transition to 0 while the input clock is lost and during input selection by priority.
Will transition to 1 once a new reference is selected.
Automatic with holdover mode: 0 indicates the reference is lost and still in holdover.
Interrupts are cleared by resetting the appropriate bit(s) in the latched register after the underlying fault condition has been resolved.
When all valid interrupt sources have been cleared in this manner, this will release the nINT output until the next unmasked fault.
Table 22. LOCK Function
Status Bit (PLL)
nLS_LOLV (VCXO-PLL)
nLS_LOLF (FemtoClock NG)
Status Reported on LOCK[a] Output[b]
Locked
Locked
1
Locked
Not locked
0
Not locked
Locked
0
Not locked
Not locked
0
[a] Hardware interrupts on nINT required to set the IE_LOLV, IE_LOLF bits to “enable interrupt”.
[b] SELSV1 controls the logic level 1.8V/3.3V of LOCK and nINT outputs.
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8V19N478 Datasheet
Serial Control Port
Serial Control Port Configuration Description
The 8V19N478 has a serial control port that can respond as a slave in an I2C compatible configuration at a base address of
11011[I2C_A1, I2C_A0]b, to allow access to any of the internal registers for device programming or examination of internal status. The
I2C_A[1:0] bits of the I2C interface address are set by the logic state of the three-level pin, I2C_A (see Table 17). If more than one
8V19N478 is connected to the same I2C bus, set I2C_A to a different state on each device to avoid address conflicts.
All registers are configured to have default values. For details, see the specifics for each register. Default values for registers are set after
reset by the configuration pins.
I2C Mode Operation
The I2C interface fully supports v1.2 of the I2C Specification for Normal and Fast mode operation. The interface acts as a slave device on
the I2C bus at 100kHz or 400kHz using a fixed base address of 11011[I2C_A1, I2C_A0]b.
The I2C interface accepts byte-oriented block write and block read operations (see Figure 3 and Figure 4). One address byte specifies
the register address of the byte position of the first register to write or read. Data bytes (registers) are accessed in sequential order from
the lowest to the highest byte (most significant bit first). Read and write block transfers can be stopped after any complete byte transfer.
During a write operation, data is moved into the registers byte by byte and before a STOP bit is received.
For full electrical I2C compliance, it is recommended to use external pull-up resistors for SDATA and SCLK. The internal pull-up resistors
have a size of 51k typical.
Figure 3. I2C Write Data (Master Transmit, Slave Receive) From Any Register Address
SDA
S
1 1 0 1 1 I2C_A1 I2C_A0
Slave Device Address
0
nW
A
A7 to A0
Register Address
A
D7 to D0
(Register Address)
A
D7 to D0
(Register Address+1)
A
...
A
D7 to D0
(Register Address+n)
A
P
Write to slave to the specified register address A[7:0]. The slave auto-increments the register address and data is written sequentially.
S
Start (Master)
P
Stop (Master)
A
Acknowledge (Slave to Master)
Master transmit, Slave Receive
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Slave transmit, Master Receive
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8V19N478 Datasheet
Figure 4. I2C Read Data (Slave Transmit, Master Receive) From Any Register Address
SDA
S
1 1 0 1 1 I2C_A1 I2C_A0
Slave Device Address
0
nW
A
A7 to A0
Register Address
A
Sr
1 1 0 1 1 ADR1 ADR0
Slave Device Address
1
R
A
D7 to D0
(Register Address)
A
...
A
D7 to D0
(Register Address+n)
A
P
Read from slave from the specified register address A[7:0]. Data is transmitted to the master after a change of the transfer direction with a repeated start. The
slave auto-increments the register address and transmits register data to the master sequentially.
S
Start (Master)
P
Stop (Master)
A
Acknowledge (Slave to Master)
A
Acknowledge (Master to Slave)
A
Not Acknowledge (Master to Slave)
Master transmit, Slave Receive
Sr
Repeated start (Master)
Slave transmit, Master Receive
Register Descriptions
This section contains all addressable registers, sorted by function, followed by a detailed description of each bit field for each register.
Several functional blocks with multiple instances in this device have individual registers controlling their settings, but since the registers
have an identical format and bit meaning, they are described only once, with an additional table to indicate their addresses and default
values. All writable register fields will come up with a default values as indicated in the Factory Defaults column unless altered by values
loaded from non-volatile storage during the initialization sequence.
Fixed read-only bits will have defaults as indicated in their specific register descriptions. Read-only status bits will reflect valid status of
the conditions they are designed to monitor once the internal power-up reset has been released. Unused registers and bit positions are
Reserved. Reserved bit fields may be used for an internal debug test and debug functions.
Table 23. Configuration Registers
Register Address
Register Description
0x00
SRESET
0x01
I2C Address (I2C only)
0x02–0x0F
Reserved
0x10–0x11
PLL Frequency Divider: PV
0x12–0x13
PLL Frequency Divider: MV
0x14
SEL_BITS_MASTER
0x15–0x16
LOCK_TH
0x17
PLL Control: BYPV
0x18
PLL Control: SRC
0x19
PLL Frequency Divider: PF, FDF
0x1A
PLL Frequency Divider: MF[7:0]
0x1B
PLL Frequency Divider: MF[8]
0x1C–0x1E
PLL Control
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8V19N478 Datasheet
Table 23. Configuration Registers (Cont.)
Register Address
Register Description
0x1F
I/O Voltage Select
0x20–0x23
Input Selection
0x24–0x26
Channel A
0x27
Reserved
0x28–0x2B
Output States QCLK_A0 – QCLK_A3
0x2C–0x2E
Channel B
0x2F
Reserved
0x30–0x33
Output States QCLK_B0 – QCLK_B3
0x34–0x36
Channel C
0x37
Reserved
0x38–0x3B
Output States QCLK_C0 – QCLK_C3
0x3C–0x42
Channel D
0x43
Reserved
0x44–0x49
Output States QCLK_D0 – QCLK_D5
0x4A
Reserved
0x4B
QCLKV
0x4C
Interrupt Enable
0x4D
Reserved
0x4E–0x4F
Reserved
0x50
Status (Latched)
0x51
Status (Momentary)
0x52
Reserved
0x53
Reserved
0x54
Reserved
0x55–0x57
General Control
0x58
Channel Enable A–D, QCLKV
0x59–0x5B
Reserved
0x5C–0x5E
Reserved
0x5F–0x60
Reserved
0x61–0x62
Reserved
0x63
Reserved
©2018 Integrated Device Technology, Inc
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8V19N478 Datasheet
Device Configuration Registers
Table 24. Device Configuration Register Bit Field Locations
Bit Field Location
Register Address
D7
D6
D5
D4
D3
D2
D1
D0
0x00
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SRESET
0x01
Reserved
0x1F
Reserved
Reserved
Reserved
SELSV
I2C_A[6:0]
Reserved
Reserved
Reserved
Reserved
Table 25. Device Configuration Register Descriptions
Register Description
Bit Field Name
Field Type
R/W
SRESET
Auto-Clear
Default
(Binary)
0
Value:
not reset
11011
I2C_A[6:0]
R
SELSV
Select
LOCK/nINT
voltage
level
[I2C_A1[1]]
[I2C_A0[0]]
1
Value: 3.3V
Description
Soft Reset:
0 Normal operation.
1 Register reset. The device loads the default values into the register 0x02-0xFF.
The content of the register addresses 0x00, 0x01 and the serial interface engine are
not reset.
I2C Device Address (I2C only):
This read-only register stores the binary I2C device address:
11011[I2C_A[1]][I2C_A[0]].
Bits D1 and D0 are determined by the I2C_A pin. For I2C_A[1:0] values based on
I2C_A level, see Table 15.
Selects the voltage level of the LOCK and nINT outputs:
SELSV:
0 LOCK, nINT interface pins are 1.8V
1 LOCK, nINT interface pins are 3.3V (default)
R/W
©2018 Integrated Device Technology, Inc
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8V19N478 Datasheet
PLL Frequency Divider Registers
Table 26. PLL Frequency Divider Register Bit Field Locations
Bit Field Location
Register Address
D7
D6
D5
D4
0x10
0x11
D2
D1
D0
Reserved
Reserved
SEL_BITS_
MASTER
Reserved
MF8
PV[7:0]
Reserved
PV[14:8]
0x12
MV[7:0]
0x13
Reserved
0x14
Reserved
MV[14:8]
Reserved
Reserved
Reserved
0x15
Reserved
LOCK_TH[7:0]
0x16
Reserved
0x19
FDF
LOCK_TH[14:8]
Reserved
PF[5:0]
0x1A
0x1B
D3
MF[7:0]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 27. PLL Frequency Divider Register Descriptions
Register Description
Bit Field Name
PV[14:0]
Field
Type
R/W
Default
(Binary)
000 0100
0000 0000
Description
VCXO-PLL Input Frequency Pre-Divider:
The value of the frequency divider (binary coding).
Range: ÷1 to ÷32767
Value: ÷1024
MV[14:0]
R/W
000 0100
0000 0000
VCXO-PLL Feedback-Divider:
The value of the frequency divider (binary coding).
Range: ÷1 to ÷32767
Value: ÷1024
SEL_BITS_MASTER
R/W
©2018 Integrated Device Technology, Inc
0
Input Path Configuration Control:
0 = Input path settings determined by ADR3 control pin.
1 = Input path settings determined by register settings over I2C.
For input path configurations see Table 13.
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8V19N478 Datasheet
Table 27. PLL Frequency Divider Register Descriptions
Register Description
Bit Field Name
LOCK_TH[14:0]
Field
Type
R/W
Default
(Binary)
000 0000
1000 0000
Value: 128
PF[5:0]
FDF
MF[8:0]
Description
PLL Lock Detect Phase Window Threshold:
The device reports VCXO-PLL lock when the phase difference between the internal
signals fREF and fVCXO_REF are lower than or equal to the phase difference set by
LOCK_TH[14:0] for more than 1000 fVCXO_DIV clock cycles.
Requires MV ≥ 4. Set LOCK_TH[14:0] < MV.
(fREF fCLK ÷ PV is the internal output of the PV divider,
fVCXO_DIV fVCXO ÷ MV is the internal output of the MV divider.)
00 0001
Value: ÷1
FemtoClock NG Pre-Divider:
The value of the frequency divider (binary coding)
Range: ÷1 to ÷63
00 0000: PF is bypassed
R/W
0
Value:
fVCXO ÷ PF
Frequency Doubler:
The input frequency of the FemtoClock NG PLL (2nd stage) is:
0 The output signal of the BYPV multiplexer, divided by the PF divider.
1 The output signal of the BYPV multiplexer, doubled in frequency.
Use this setting to improve phase noise. The PF divider has no effect if FDF 1.
R/W
0 0001 1000
Value: ÷24
FemtoClock NG Feedback-Divider:
The value of the frequency divider (binary coding).
Range: ÷8 to ÷511
R/W
©2018 Integrated Device Technology, Inc
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8V19N478 Datasheet
PLL Control Registers
Table 28. PLL Control Bit Field Locations
Bit Field Location
Register Address
D7
D6
D5
D4
D3
D2
D1
D0
0x17
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BYPV
0x18
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SRC
0x1C
POLV
FVCV
Reserved
CPV[4:0]
0x1D
Reserved
Reserved
OSVEN
OFFSET[4:0]
0x1E
Reserved
Reserved
Reserved
CPF[4:0]
Table 29. PLL Control Register Descriptions
Register Description
Bit Field Name
Field Type
Default
(Binary)
0
BYPV
R/W
VCXO-PLL
enabled
0
SRC
R/W
PLL
enabled
0
POLV
R/W
Value:
Positive
Polarity
1
FVCV
R/W
Value:
Value: LFV
VDD_V/2
0 1111
CPV[4:0]
R/W
Value:
0.8mA
©2018 Integrated Device Technology, Inc
Description
VCXO-PLL Bypass:
0 VCXO-PLL is enabled.
1 VCXO-PLL is disabled and bypassed.
FemtoClock NG PLL Bypass:
0 FemtoClock NG PLL is enabled.
1 FemtoClock NG PLL is disabled and bypassed. The VCXO-PLL output signal is
frequency divided by the channel dividers.
VCXO Polarity:
0 Positive polarity. Use for an external VCXO with a positive f(VC) characteristics
1 Negative polarity. Use for an external VCXO with a negative f(VC) characteristics
VCXO-PLL Force VC Control Voltage:
0 Normal operation.
1 Forces the voltage at the LFV control pin (VCXO input) to VDD_V/2. VCXO-PLL
unlocks and the VCXO is forced to its mid-point frequency. FVCV 1 is the default
setting at startup to center the VCXO frequency. FVCV should be cleared after startup to
enable the PLL to lock to the reference frequency.
VCXO-PLL Charge-Pump Current:
Controls the charge-pump current ICPV of the VCXO-PLL. Charge pump current is the
binary value of this register plus one multiplied by 50µA.
ICPV 50µA (CPV[4:0] + 1)
CPV[4:0] 00000 sets ICPV to the min. current of 50µA. Maximum charge-pump
current is 1.6 mA. Default setting is 0.8mA: ((15 + 1) 50µA).
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8V19N478 Datasheet
Table 29. PLL Control Register Descriptions (Cont.)
Register Description
Bit Field Name
OSVEN
Field Type
Default
(Binary)
R/W
0
0 0000
OFFSET[4:0]
R/W
Value: 0
1 1000
CPF[4:0]
R/W
Value:
1.4mA
©2018 Integrated Device Technology, Inc
Description
VCXO-PLL Offset Enable:
0 No offset.
1 Offset enabled. A static phase offset of OFFSET[4:0] is applied to the PFD of the
VCXO-PLL.
VCXO-PLL Static Phase Offset:
Controls the static phase detector offset of the VCXO-PLL. Phase offset is the binary
value of this register multiplied by 0.9 of the PFD input signal,
(OFFSET [4:0] fPFD ÷ 400). The maximum offset is 31 0.927.9
Setting OFFSET to 0.0 eliminates the thermal noise of an offset current. If the
VCXO-PLL input jitter period TJIT exceeds the average input period: set OFFSET to a
value larger than fPFD TJIT 400 to achieve a better charge-pump linearity and lower
in-band noise of the PLL.
FemtoClock NG PLL Charge-Pump Current:
Controls the charge-pump current ICPF of the FemtoClock NG PLL. The charge-pump
current is the binary value of this register plus one multiplied by 200µA.
ICPF 200µA (CPF[4:0] + 1)
CPV[4:0] 00000 sets ICPF to the minimum current of 200µA. Maximum charge-pump
current is 6.4 mA. Default setting is 1.4 mA: ((6 + 1) 200µA).
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8V19N478 Datasheet
Input Selection Mode Registers
Table 30. Input Selection Mode Register Bit Field Locations
Bit Field Location
Register Address
D7
D6
0x20
0x21
D5
D4
D3
VCXO_DIV[4:0]
Reserved
Reserved
Reserved
REVS
0x22
D2
D1
D0
MODE_BLOCK
nHO_EN
nEXT_INT
Reserved
INT_SEL
nM/A[1:0]
CNTH[7:0]
0x23
CNTR[1:0]
Reserved
Reserved
Reserved
CNTV[1]
CNTV[0]
Table 31. Input Selection Mode Registers
Register Description
Bit Field Name
Field Type
Default
(Binary)
00000
VCXO_DIV[4:0]
R/W
Value: ÷1
0
MODE_BLOCK
R/W
Value:
Not blocked
1
nHO_EN
R/W
Value:
Enter
Holdover
Disabled
©2018 Integrated Device Technology, Inc
Description
Clock Frequency Divider for the input activity monitor:
The clock activity monitor compares the device input frequency (fIN) to the frequency of
the VCXO divided by VCXO_DIV. For optimal operation of the activity monitor, the
frequency fVCXO ÷ VCXO_DIV should match the input frequency.
E.g. for fIN 61.44MHz and fVCXO 61.44MHz, set VCXO_DIV ÷1.
For fIN 25MHz and fVCXO 125MHz, set FCXO_DIV ÷5.
VCXO_DIV[4:0]
0XX 00
÷1
0XX 01
÷2
0XX 10
÷4
0XX 11
÷8
100 00 ÷2
100 01 ÷4
100 10 ÷8
100 11
÷16
101 00 ÷3
101 01 ÷6
101 10
÷12
101 11
÷24
110 00 ÷4
110 01 ÷8
110 10
÷16
110 11
÷32
111 00 ÷5
111 01 ÷10
111 10 ÷20
111 11 ÷40
Inactive Input Clock Block:
0 Both input clock signals CLK0 and CLK1 are routed to the input clock multiplexer.
1 The input clock that is currently not active is gated off (blocked).
Manual Holdover Control:
0 Enter holdover on a manual input reference switch.
Using the EXT_SEL control pin or the INT_SEL control bit, as defined by nEXT_INT for
manual reference switching. nMA[1:0] has no meaning.
1 The device switching and holdover modes are controlled by nMA[1:0].
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8V19N478 Datasheet
Table 31. Input Selection Mode Registers (Cont.)
Register Description
Bit Field Name
Field Type
Default
(Binary)
0
nEXT_INT
R/W
Value:
External
selection
0
REVS
R/W
Value: Off
00
nM/A[1:0]
R/W
Value:
Manual
selection
0
INT_SEL
R/W
Value:
CLK0
selected
1000 0000
CNTH[7:0]
R/W
Value:
134ms
©2018 Integrated Device Technology, Inc
Description
Input Clock Selection:
0 The EXT_SEL pin (B3) controls the input clock selection.
1 The INT_SEL bit (register 0x21, D0) controls the input clock selection.
Revertive Switching:
The revertive input switching setting is only applicable to the two automatic selection
modes shown in Table 11. If nM/A[1:0] X0, the REVS setting has no meaning.
0 Disabled: Re-validation of the non-selected input clock has no impact on the clock
selection.
1 Enabled: Re-validation of the non-selected input clock will cause a new input
selection according to the pre-set input priorities (revertive switch).
Default setting is revertive switching turned off.
Reference Input Selection Mode:
In any of the manual selection modes (nM/A[1:0] 00 or 10), the VCXO-PLL reference
input is selected by INT_SEL. In any of the automatic selection modes, the VCXO-PLL
reference input is selected by an internal state machine according to the input LOS states
and the priorities in the input priority registers.
00 Manual selection (no holdover)
01 Automatic selection (no holdover)
10 Short-term holdover
11 Automatic selection with holdover
VCXO-PLL Input Reference Selection:
Controls the selection of the VCXO-PLL reference input in internal (nEXT_INT 1), and
in manual selection mode (nHO_EN 1, nM/A[1:0] 00 or 10).
In external (nEXT_INT 0) and in automatic selection modes (nM/A[1:0] X1), INT_SEL
has no meaning.
0 CLK_0 is the selected VCXO-PLL reference clock.
1 CLK_1 is the selected VCXO-PLL reference clock.
Short-term Holdover: Hold-off counter period. The device initiates a clock fail-over switch
upon counter expiration (zero transition). The counters start to counts backwards after an
LOS event is detected. The hold-off counter period is determined by the binary number of
VCXO-PLL output pulses divided by CNTR[1:0]. With a VCXO frequency of 125MHz and
CNTR[1:0] 10, the counter has a period of
(1.048ms binary setting). After each zero-transition, the counter automatically re-loads
to the setting in this register.
The default setting is 134ms (VCXO 125MHz: 1/125MHz 217 128).
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8V19N478 Datasheet
Table 31. Input Selection Mode Registers (Cont.)
Register Description
Bit Field Name
Field Type
Default
(Binary)
Description
Short-term Holdover Reference Divider
CNTR[1:0]
10
CNTR[1:0]
R/W
Value: 217
10
CNTV[1:0]
R/W
Value: 32
©2018 Integrated Device Technology, Inc
CNTH frequency (period; range)
125MHz VCXO
156.25MHz VCXO
15
3814Hz
(0.262ms; 0ms – 66.8ms)
4768Hz
(0.209ms; 0ms – 53.4ms)
01 fVCXO ÷ 216
1907Hz
(0.524ms; 0ms – 133ms)
2384Hz
(0.419ms; 0ms – 106.9ms)
10 fVCXO ÷ 217
953Hz
(1.048ms; 0ms – 267ms)
1192Hz
(0.838ms; 0ms – 213.9ms)
00 fVCXO ÷ 2
Revalidation Counter:
Controls the number of required consecutive, valid input reference pulses for clock
re-validation on CLK_n for the number of input periods. At an LOS event, the re-validation
counter loads this setting from the register and counts down by one with every valid,
consecutive input signal period. Missing input edges (for one input period) will cause this
counter to re-load its setting. An input is re-validated when the counter transitions to zero
and the corresponding LOS flag is reset.
00 2 (shortest possible)
01 16
10 32
11 64
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8V19N478 Datasheet
Channel Registers
The content of the channel registers set the channel state, the clock divider the clock phase delay and the power-down state.
Table 32. Channel Register Bit Field Locations
Bit Field Location
Register Address
D7
D6
D5
D4
D3
0x24: Channel A
0x2C: Channel B
0x34: Channel C
0x40: Channel D
N_A[7:0]
N_B[7:0]
N_C[7:0]
N_D[7:0]
0x25: Channel A
0x2D: Channel B
0x35: Channel C
0x41: Channel D
CLK_A[7:0]
CLK_B[7:0]
CLK_C[7:0]
CLK_D[7:0]
D2
D1
D0
0x26: Channel A
0x2E: Channel B
0x36: Channel C
PD_A
PD_B
PD_C
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SEL_ BITS_A
SEL_ BITS_B
SEL_BITS_C
0x42: Channel D
PD_D
Reserved
Reserved
Reserved
D_DIV_FRAC
[1]
D_DIV_FRAC
[0]
CH_D_OUT
SEL_BITS_D
0x3C: Channel D
0x3D: Channel D
0x3E: Channel D
N_D_FRAC[7:0]
N_D_FRAC[15:8]
N_D_FRAC[23:16]
0x3F: Channel D
Reserved
Reserved
Reserved
Reserved
0x58
Reserved
Reserved
Reserved
EN_QCLK_
V
©2018 Integrated Device Technology, Inc
36
N_D_INT[3:0]
EN_QCLK_A
EN_QCLK_B
EN_QCLK_
C
EN_QCLK_D
May 15, 2018
8V19N478 Datasheet
Table 33. Channel Register Descriptions[a]
Register Description
Bit Field Name
Field Type
Default
(Binary)
Description
Output Frequency Divider N:
N_x[7:0] Divider Value
0100 0110
N_x[7:0]
R/W
Value: ÷16
N_D_FRAC[23:0]
R/W
0110 0000
0000 0000
0000 0000
Value:
6,291,456
©2018 Integrated Device Technology, Inc
1000 0000
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0110
÷1
÷2
÷3
÷4
÷5
÷6
÷8
0100 0011
0100 0100
0100 0110
÷10
÷12
÷16
0100 1011
0100 1100
÷20
÷24
0101 0011
0100 1110
0101 0100
÷30
÷32
÷36
0101 1011
0101 0110
÷40
÷48
0110 0011
÷50
0110 0100
0101 1110
÷60
÷64
0101 1111
÷72
0110 0110
÷80
0110 1110
÷96
0111 1011
÷100
0111 1100
0111 0110
÷120
÷128
0111 1110
÷160
Fractional Output Divider, Fractional Part:
Together with N_E_INT, forms the fractional output divider ND value.
N FRAC
N E = 2 N INT + --------------------
224
The default value is ND 2 (9 + 0.4371839761732) 18.8743679523.
Greatest ND fractional divider is 2 (14 + [224 – 1] / 224) ≈ 29.99999988.
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8V19N478 Datasheet
Table 33. Channel Register Descriptions[a] (Cont.)
Register Description
Bit Field Name
Field Type
N_D_INT[3:0]
R/W
Default
(Binary)
1001
Value: 9
Description
Fractional Output Divider, Integer Part:
See N_D_FRAC[23:0]
Greatest ND fractional divider is 2 (14 + [224 – 1] / 224) ≈ 29.99999988.
CLK_x Phase Delay:
CLK_x[7:0]
CLK_x[7:0]
R/W
0000 0000
fVCO 2500MHz
0000 0000
0000 0001
…
1111 1111
0
PD_x
R/W
R/W
Value:
Disabled
0
EN_QCLK_V
R/W
0ps
400ps
…
102ns
0 Channel x is powered up
1 Channel x is power down
Value:
Power-up
0
EN_x
fVCO 2500MHz:
Delay in ps CLK_x 400ps (256 steps)
CLK_x[7:0] Delay (fVCO 2500MHz)
Value:
Disabled
©2018 Integrated Device Technology, Inc
QCLK_x Channel Output Enable:
0 All outputs of channel x are disabled at the logic low state.
1 All outputs of channel x are enabled.
QCLK_V Output Enable:
0 QCLK_V is disabled at the logic low state.
1 QCLK_V is enabled.
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May 15, 2018
8V19N478 Datasheet
Table 33. Channel Register Descriptions[a] (Cont.)
Register Description
Bit Field Name
SEL_BITS_x
D_DIV_FRAC[1:0]
CH_D_OUT
Field Type
Default
(Binary)
R/W
R/W
R/W
Description
0
Bank x Configuration Control:
0 Nx[5:0], PD_X, EN_X settings determined by ADRn control pin.
1 Nx[5:0], PD_X, EN_X settings determined by register settings over I 2C.
Where:
n = 0 for Channels A and C
n = 1 for Channel B
n = 2 for Channel D
0
D_DIV_FRAC[1:0]:
Post-divider ratio for Bank D fractional divider:
00 ÷1
01 ÷2
10 ÷4
11 Reserved
0
CH_D_OUT:
Controls which the divider is used to provide output frequency for Bank D:
0 Integer divider D (ND configures this)
1 Fractional mode (ND_FINT, ND_FRAC, and ND_DIVF configure this)
[a] x A, B, C, D.
©2018 Integrated Device Technology, Inc
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8V19N478 Datasheet
Output Registers
The content of the output registers set the power-down state, the output style and amplitude.
Table 34. Output Register Bit Field Locations
Bit Field Location
Register Address
D7
D6
0x28: QCLK_A0
0x29: QCLK_A1
0x2A: QCLK_A2
0x2B: QCLK_A3
PD_A0
PD_A1
PD_A2
PD_A3
0x30: QCLK_B0
0x31: QCLK_B1
0x32: QCLK_B2
0x33: QCLK-B3
PD_B0
PD_B1
PD_B2
PD_B3
0x38: QCLK_A0
0x39: QCLK_A1
0x3A: QCLK_A2
0x3B: QCLK_A3
PD_C0
PD_C1
PD_C2
PD_C3
0x44: QCLK_D0
0x45: QCLK_D1
0x46: QCLK_D2
0x47: QCLK_D3
0x48: QCLK_D4
0x49: QCLK_D5
PD_D0
PD_D1
PD_D2
PD_D3
PD_D4
PD_D5
Reserved
Reserved
0x4B: QCLK_V
PD_V
Reserved
Reserved
Reserved
Reserved
Reserved
©2018 Integrated Device Technology, Inc
D5
Reserved
Reserved
Reserved
D4
D3
D2
D1
D0
Reserved
STYLE_A0
STYLE_A1
STYLE_A2
STYLE_A3
A_A0[1]
A_A1[1]
A_A2[1]
A_A3[1]
A_A0[0]
A_A1[0]
A_A2[0]
A_A3[0]
Reserved
STYLE_B0
STYLE_B1
STYLE_B2
STYLE_A3
A_B0[1]
A_B1[1]
A_B2[1]
A_A3[1]
A_B0[0]
A_B1[0]
A_B2[0]
A_A3[0]
Reserved
STYLE_C0
STYLE_C1
STYLE_C2
STYLE_C3
A_C0[1]
A_C1[1]
A_C2[1]
A_C3[1]
A_C0[0]
A_C1[0]
A_C2[0]
A_C3[0]
Reserved
Reserved
STYLE_D0
STYLE_D1
STYLE_D2
STYLE_D3
STYLE_D4
STYLE_D5
A_D0[1]
A_D1[1]
A_D2[1]
A_D3[1]
A_D4[1]
A_D5[1]
A_D0[0]
A_D1[0]
A_D2[0]
A_D3[0]
A_D4[0]
A_D5[0]
Reserved
STYLE__V1
STYLE__V0
A_V[1]
A_V[0]
Reserved
Reserved
Reserved
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May 15, 2018
8V19N478 Datasheet
Table 35. Output Register Descriptions[a]
Register Description
Bit Field Name
Field Type
Default
(Binary)
0
PD_y
R/W
R/W
R/W
Value:
700mV
10
A_V[1:0]
R/W
Value:
700mV
1
STYLE_y
R/W
Value:
LVPECL
01
STYLE_V[1:0]
R/W
0 Output QCLK_V is powered-up.
1 Output QCLK_V is power-down.
Value:
Power-dow
n
10
A_y[1:0]
0 Output QCLK_y is powered-up.
1 Output QCLK_y is power-down.
Value:
Power-up
1
PD_V
Description
Value:
LVPECL
QCLK_y, QCLK_V Output Amplitude
Setting for STYLE 0 (LVDS)
Setting for STYLE 1 (LVPECL)
A[1:0] 00: 350mV
A[1:0] 01: 500mV
A[1:0] 10: 700mV
A[1:0] 11: 850mV
Termination: 100 across
A[1:0] 00: 350mV
A[1:0] 01: 500mV
A[1:0] 10: 700mV
A[1:0] 11: 850mV
Termination: 50 to VTT[b]
QCLK_y Output Format:
0 Output is LVDS (Requires LVDS 100 output termination)
1 Output is LVPECL (Requires LVPECL 50 output termination of to the specified
recommended termination voltage).
QCLK_V Output Format:
00 Output is LVDS (Requires LVDS 100 output termination).
01 Output is LVPECL (Requires LVPECL 50 termination to VTT[b]).
1x Both QCLK_V and nQCLK_V are single-ended LVCMOS 1.8V outputs, QCLK_V
and nQCLK_V are complementary (180º phase difference).
[a] y A0,A1,A2,A3,B0,B1,B2,B3,C0,C1,C2,C3,D0,D1,D2,D3,D4,D5.
[b] For VTT (Termination voltage) values (Table 50).
©2018 Integrated Device Technology, Inc
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8V19N478 Datasheet
Status Registers
Table 36. Status Register Bit Field Locations
Bit Field Location
Register Address
D7
D6
D5
D4
D3
D2
D1
D0
0x4C
Reserved
Reserved
IE_LOLF
IE_LOLV
IE_REF
IE_HOLD
IE_CLK_1
IE_CLK_0
0x50
Reserved
Reserved
nLS_LOLF
nLS_LOLV
LS_REF
nLS_HOLD
LS_CLK_1
LS_CLK_0
0x51
Reserved
ST_SEL
nST_LOLF
nST_LOLV
ST_REF
nST_HOLD
ST_CLK_1
ST_CLK_0
0x53
Reserved
Reserved
Reserved
Reserved
Reserved
ST_CAL
Reserved
Reserved
Table 37. Status Register Descriptions[a]
Register Description
Bit Field Name
Field Type
Default
(Binary)
Description
IE_LOLF
R/W
0
Interrupt Enable for FemtoClock NG PLL Loss-of-lock:
0 Disabled: Setting nLS_LOLF will not cause an interrupt on nINT.
1 Enabled: Setting nLS_LOLF will assert the nINT output (nINT 0, interrupt).
IE_LOLV
R/W
0
Interrupt Enable for VCXO-PLL Loss-of-lock:
0 Disabled: Setting nLS_LOLV will not cause an interrupt on nINT.
1 Enabled: Setting nLS_LOLV will assert the nINT output (nINT 0, interrupt).
0
Interrupt Enable for CLKn input Loss-of-signal:
0 Disabled: Setting LS_CLK_n will not cause an interrupt on nINT.
1 Enabled: Setting LS_CLK_n will assert the nINT output (nINT 0, interrupt).
IE_CLK_n
R/W
IE_REF
R/W
0
Interrupt Enable for LS_REF:
0 Disabled: Any changes to LS_REF will not cause an interrupt on nINT.
1 Enabled: Any changes to LS_REF will assert the nINT output (nINT 0, interrupt).
IE_HOLD
R/W
0
Interrupt Enable for Holdover:
0 Disabled: Setting nLS_HOLD will not cause an interrupt on nINT.
1 Enabled: Setting nLS_HOLD will assert the nINT output (nINT 0, interrupt).
—
FemtoClock NG PLL Loss-of-lock (latched status of nST_LOLF):
Read 0 1 Loss-of-lock events detected after the last status latch clear.
Read 1 No Loss-of-lock detected after the last status latch clear.
Write 1 Clear status latch (clears pending nLS_LOLF interrupt).
—
VCXO-PLL Loss-of-lock (latched status of nST_LOLV):
Read 0 1 Loss-of-lock events detected after the last status latch clear.
Read 1 No Loss-of-lock detected after the last nLS_LOLV clear.
Write 1 Clear status latch (clears pending nLS_LOLV interrupt).
nLS_LOLF
nLS_LOLV
R/W
R/W
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8V19N478 Datasheet
Table 37. Status Register Descriptions[a] (Cont.)
Register Description
Bit Field Name
LS_CLK_n
ST_SEL
nST_LOLF
nST_LOLV
ST_CLK_n
LS_REF
Field Type
Default
(Binary)
R/W
R
R
R
R
R/W
Description
—
Input CLK_n Status (latched status of ST_CLK_n):
Read 0 1 LOS events detected on CLK_n after the last LS_CLK_n clear.
Read 1 No loss-of-signal detected on CLK_n input after the last LS_CLK_n clear.
Write 1 Clear LS_CLK_n status latch (clears pending LS_CLK_n interrupts on nINT).
—
Input Selection (momentary):
Reference input selection status of the state machine. In any input selection mode,
reflects the input selected by the state machine.
0 CLK_0
1 CLK_1
—
FemtoClock NG PLL Loss-of-lock (momentary):
Read 0 1 Loss-of-lock events detected
Read 1 No Loss-of-lock detected
A latched version of this status bit is available (nLS_LOLF).
—
VCXO-PLL Loss-of-lock (momentary):
Read 0 1 Loss-of-lock events detected
Read 1 No Loss-of-lock detected
A latched version of this status bits is available (nLS_LOLV).
—
Input CLK_n Status (momentary):
0 LOS detected on CLK_n.
1 No LOS detected, CLK_n input is active.
A latched version of this status bits are available (LS_CLK_n).
—
PLL Reference Status (latched status of ST_REF):
Read 0 Reference is lost since last reset of this status bit.
Read 1 Reference is valid since last reset of this status bit.
Write 1 Clear LS_REF status latch (clears pending LS_REF interrupts on nINT).
nLS_HOLD
R/W
—
Holdover Status Indicator (latched status of ST_HOLD):
Read 0 VCXO-PLL has entered holdover state 1 times after reset of this status bit.
Read 1 VCXO-PLL is (or attempts to) lock(ed) to an input clock.
Write 1 Clear status latch (clears pending nLS_HOLD interrupt).
ST_VCOF
R
—
FemtoClock NG PLL Calibration Status (momentary):
Read 0 FemtoClock NG PLL auto-calibration is completed.
Read 1 FemtoClock NG PLL calibration is active (not completed).
—
Input Reference Status.
0 No input reference present.
1 Input reference is present at the clock selected input clock.
ST_REF
R
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8V19N478 Datasheet
Table 37. Status Register Descriptions[a] (Cont.)
Register Description
Bit Field Name
Field Type
nST_HOLD
Default
(Binary)
R
ST_CAL
R
Description
—
Holdover Status Indicator (momentary):
0 VCXO-PLL in holdover state, not locked to any input clock.
1 VCXO-PLL is (or attempts to) lock(ed) to input clock.
A latched version of this status bit is available (nLS_HOLD).
—
FemtoClock NG PLL Calibration Status (momentary):
Read 0 FemtoClock NG PLL auto-calibration is completed.
Read 1 FemtoClock NG PLL calibration is active (not completed).
[a] CLKn CLK0, CLK1.
General Control Registers
Table 38. General Control Register Bit Field Locations
Bit Field Location
Register Address
D7
0x55
INIT_CLK
0x56
RELOCK
0x57
PB_CAL
D6
D5
D4
D3
D2
D1
D0
Table 39. General Control Register Descriptions
Register Description
Default
(Binary)
Bit Field Name
Field Type
INIT_CLK
W only
Auto-Clear
X
RELOCK
W only
Auto-Clear
X
PB_CAL
W only
Auto-Clear
©2018 Integrated Device Technology, Inc
X
Description
Set INIT_CLK 1 to initialize divider functions. Required as part of the startup
procedure.
Setting this bit to 1 will force the FemtoClock NG PLL to re-lock.
Precision Bias Calibration:
Setting this bit to 1 will start the calibration of an internal precision bias current source.
The bias current is used as reference for outputs configured as LVDS, and as reference
for the charge-pump currents. This bit will auto-clear after the calibration completed. Set
as part of the startup procedure.
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8V19N478 Datasheet
Electrical Characteristics
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the
device. Functional operation of the 8V19N478 at absolute maximum ratings is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 40. Absolute Maximum Ratings
Item
Rating
Supply Voltage, VDD_V and VDDO_V
3.6V
Inputs
-0.5V to VDD_V 0.5V
Outputs, VO (LVCMOS)
-0.5V to VDDO_V 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Outputs, IO (LVDS)
Continuous Current
Surge Current
50mA
100mA
Operating Junction Temperature, TJ
125C
Storage Temperature, TSTG
-65C to 150C
[a]
2000V
Model[a]
500V
ESD – Human Body Model
ESD – Charged Device
[a] According to JEDEC JS-001-2012/JESD22-C101.
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8V19N478 Datasheet
Pin Characteristics
Table 41. Input Characteristics, VDD_V 3.3V ±5%, VDDO_V (3.3V, 2.5V or 1.8V) ±5%, TA = -40°C to +85°C
Symbol
CIN[a]
RPU
RPD
ROUT
Parameter
Typical
Maximum
Units
OSC, nOSC
2
4
pF
Other inputs
2
4
pF
Input Pull-Up Resistor
nCLK_0, nCLK_1
51
k
Input Pull-Down Resistor
CLK_0, nCLK_0, CLK_1, nCLK_1,
EXT_SEL, ADR1/MISO, I2C
51
k
LVCMOS Output Impedance
nINT, LOCK
25[b]
W
Input Capacitance
Test Conditions
Minimum
[a] Guaranteed by design.
[b] Design target specifications.
DC Characteristics
The device is configured to the maximum values of register settings, all outputs enabled in LVDS mode, and amplitude of 850mV.
Process variation is included for the maximum current consumption.
Table 42. Power Supply DC Characteristics, VDD_V 3.3V ±5%, VDDO_V (3.3V, 2.5V, or 1.8V) ±5%,
TA = -40°C to +85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD_V
Core Supply Voltage
3.135
3.3
3.465
V
VDDO_V
Output Supply Voltage
1.71
1.8, 2.5, 3.3
3.465
V
IDD_V
Power Supply Current
580
1024
mA
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8V19N478 Datasheet
Table 43. Typical Power Supply DC Current Characteristics, VDD_V 3.3V ±5%, VDDO_V (3.3V, 2.5V, or
1.8V) ±5%, TA = -40°C to +85°C[a]
Test Case
Symbol
1[b]
2[b]
3[c]
4[c]
5[c]
6[c]
Units
3.3
3.3
3.3
3.3
1.8
1.8
V
Style
LVDS
LVDS
LVPECL
LVPECL
LVPECL
LVPECL
–
State
On
On
On
On
On
On
–
Amplitude
700
850
850
700
500
350
mV
VDDO_QCLKC, _QCLKD
3.3
3.3
3.3
3.3
1.8
1.8
V
Style
LVDS
LVDS
LVPECL
LVPECL
LVDS
LVDS
–
State
On
On
On
On
On
On
–
Amplitude
700
850
850
700
500
350
mV
Supply Pin Current
VDDO_QCLKA, _QCLKB
–
–
QCLK_A[3:0],
QCLK_B[3:0]
QCLK_C[3:0],
QCLK_D[5:0]
IDD_COA
Current through VDDO_QCLKA pin
0.088
0.109
0.135
0.123
0.104
0.090
A
IDD_CA
Current through VDD_QCLKA pin
0.039
0.039
0.037
0.037
0.037
0.037
A
IDD_COB
Current through VDDO_QCLKB pin
0.088
0.109
0.131
0.118
0.099
0.087
A
IDD_CB
Current through VDD_QCLKB pin
0.034
0.034
0.038
0.038
0.038
0.038
A
IDD_COC
Current through VDDO_QCLKC pin
0.088
0.109
0.135
0.122
0.139
0.119
A
IDD_CC
Current through VDD_QCLKC pin
0.039
0.039
0.036
0.036
0.036
0.036
A
IDD_COD
Current through VDDO_QCLKD pin
0.132
0.164
0.188
0.170
0.196
0.167
A
IDD_CD
Current through VDD_QCLKD pin
0.044
0.044
0.045
0.045
0.045
0.045
A
IDD_SPI
Current through VDD_I2C pin
0.009
0.009
0.009
0.009
0.009
0.009
A
IDD_INP
Current through VDD_INP pin
0.013
0.013
0.013
0.013
0.013
0.013
A
IDD_LCV
Current through VDD_LCV pin
0.077
0.081
0.080
0.080
0.080
0.080
A
IDD_LCF
Current through VDD_LCF pin
0.060
0.060
0.060
0.060
0.060
0.060
A
IDD_CPV
Current through VDD_CPV pin
0.014
0.014
0.014
0.014
0.014
0.014
A
IDD_CPF
Current through VDD_CPF pin
0.056
0.056
0.055
0.055
0.055
0.055
A
IDD_OSC
Current through VDD_OSC pin
0.006
0.006
0.006
0.006
0.006
0.006
A
IDD_TOT
Total Device Current Consumption
0.787
0.887
0.982
0.927
0.931
0.857
A
2.596
2.928
3.242
3.058
2.267
2.132
W
2.596
2.928
2.165
2.051
2.025
1.881
W
PTOT, SYS
Total System Power Consumption
PTOT
Total Device Power Consumption
[d]
[a] Design target specifications.
[b] fCLK (input) 40MHz, fVCXO 156.25MHz, fVCO 2500MHz, PV 160, MV 625, MF 8, FDF 1. Supply current is independent of the output
frequency configuration used for this table: QCLKA[3:0] 41.66MHz, QCLKB[3:0] 500MHz, QCLKC[3:0] 31.25MHz, QCLKD[5:0] 500MHz.
QCLK_y outputs terminated according to amplitude settings: LVPECL outputs terminated to VTT.
[c] fCLK (input) 125MHz, fVCXO 156.25MHz, fVCO 2500MHz, PV 1024, MV 1280, MF 8, FDF 1. Supply current is independent of the
output frequency configuration used for this table: QCLKA[3:0] 125MHz, QCLKB[3:0] 156.25MHz, QCLKC[3:0] 250MHz,
QCLKD[5:0] 312.5MHz. QCLK_y outputs terminated according to amplitude settings: LVPECL outputs terminated to VTT.
[d] Includes total device power consumption and the power dissipated in external output termination components.
©2018 Integrated Device Technology, Inc
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8V19N478 Datasheet
Table 44. LVCMOS DC Characteristics, VDD_V 3.3V ±5%, VDDO_V (3.3V, 2.5V, or 1.8V) ±5%,
TA = -40°C to +85°C[a]
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
-0.3
VDD_V
V
Control inputs, (1.8V/JESD7A-8 logic, input hysteresis and 3.3V tolerance)
VI
Input Voltage
VT
Positive-going Input Threshold Voltage
0.660
1.365
V
VT-
Negative-going Input Threshold Voltage
0.495
1.170
V
VH
Hysteresis Voltage
0.165
0.780
V
150
µA
Input High Current
IIH
VT – VTInput (PD)[b] and
Input (PD/PU)[c]
VDD_V 3.3V, VIN 3.3V
Input (PU)[d]
Input Low Current
Input (PD)
IIL
[b]
5
VDD_V 3.465V, VIN 0V
Input (PU)[d] and
Input (PD/PU)[c]
-5
µA
-150
Control outputs ADR1/MISO (when output), nINT, LOCK configured to 3.3V (SELSV0 0, SELSV1 0)
VOH
Output High Voltage
VOL
Output Low Voltage
ADR1/MISO (when
output), nINT,
LOCK
IOH -4mA
2.0
V
IOL 4mA
0.55
V
Control outputs ADR1/MISO (when output), nINT, LOCK configured to 1.8V (SELSV0 1, SELSV1 1)
VOH
Output High Voltage
IOH -4mA
VOL
Output Low Voltage
IOL 4mA
1.35
1.8
V
0.45
V
1.8
V
0.45
V
Clock outputs QCLK_V, nQCLK_V configured to LVCMOS (STYLE_V[1:0] 1)
VOH
Output High Voltage
IOH -8mA
VOL
Output Low Voltage
IOL 8mA
1.35
[a] Design target specifications.
[b] EXT_SEL.
[c] I2C_A, ADR3, ADR2, ADR1, ADR0.
[d] SDAT, SCL.
Table 45. Differential Input DC Characteristics, VDD_V 3.3V ±5%, VDDO_V (3.3V, 2.5V, or 1.8V) ±5%,
TA = -40°C to +85°C
Symbol
Parameter
IIH
Input
High Current
IIL
Input
Low Current
Pull-down inputs[a]
Test Conditions
Minimum
VDD_V VIN 3.465V
Pull-down/pull-up
inputs[b]
Pull-down inputs[a]
VDD_V 3.465V, VIN 0V
Pull-down/pull-up
inputs[b]
Typical
Maximum
Units
150
µA
150
µA
-150
µA
-150
µA
[a] Non-Inverting inputs: CLK_0, CLK_1, OSC.
[b] Inverting inputs: nCLK_0, nCLK_1, nOSC.
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8V19N478 Datasheet
Table 46. LVPECL DC Characteristics (QCLK_y, STYLE 1), VDD_V 3.3V ±5%, VDDO_V (3.3V, 2.5V, or
1.8V) ±5%, TA = -40°C to +85°C[a]
Symbol
VOH
VOL
Parameter
Output High Voltage[b][c]
Output Low Voltage[b][c]
Test Conditions
Minimum
Typical
Maximum
Units
350mV amplitude setting
VDDO_V - 1.034
VDDO_V - 0.892
VDDO_V - 0.750
V
500mV amplitude setting
VDDO_V - 1.057
VDDO_V - 0.912
VDDO_V - 0.768
V
700mV amplitude setting
VDDO_V - 1.092
VDDO_V - 0.950
VDDO_V - 0.808
V
850mV amplitude setting
VDDO_V - 1.087
VDDO_V - 0.960
VDDO_V - 0.833
V
350mV amplitude setting
VDDO_V - 1.413
VDDO_V - 1.265
VDDO_V - 1.117
V
500mV amplitude setting
VDDO_V - 1.574
VDDO_V - 1.420
VDDO_V - 1.266
V
700mV amplitude setting
VDDO_V - 1.782
VDDO_V - 1.633
VDDO_V - 1.485
V
850mV amplitude setting
VDDO_V - 1.918
VDDO_V - 1.778
VDDO_V - 1.638
V
[a] Design target specifications.
[b] Outputs terminated with 50 to VTT. For termination voltage VTT values (Table 50).
[c] 700mV and 850mV amplitude settings are only available at VDDO_V ≥ 2.5V.
Table 47. LVDS DC Characteristics (QCLK_y, STYLE = 0), VDD_V = 3.3V ± 5%, VDDO_V = (3.3V, 2.5V, or
1.8V) ±5%, TA = -40°C to +85°C[a]
Symbol
VOS
VOS
Parameter
Offset Voltage[b][c]
Test Conditions
Minimum
Typical
Maximum
Units
350mV amplitude setting
VDDO_V - 1.034
VDDO_V - 0.947
VDDO_V - 0.862
V
500mV amplitude setting
VDDO_V - 1.133
VDDO_V - 1.045
VDDO_V - 0.961
V
700mV amplitude setting
VDDO_V - 1.229
VDDO_V - 1.142
VDDO_V - 1.056
V
850mV amplitude setting
VDDO_V - 1.316
VDDO_V - 1.226
VDDO_V - 1.138
V
25
50
mV
VOS Magnitude Change
[a] Design target specifications.
[b] VOS changes with VDD.
[c] 700mV and 850mV amplitude settings are only available at VDDO_V ≥ 2.5V.
©2018 Integrated Device Technology, Inc
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8V19N478 Datasheet
AC Characteristics
Table 48. AC Characteristics, VDD_V = 3.3V ±5%, VDDO_V = (3.3V, 2.5V, or 1.8V) ±5%,
TA = -40°C to +85°C[a][b]
Symbol
Parameter
fIN
Input Frequency
fVCXO
VCXO Frequency
fPFD, F
Phase-Frequency Detector
Frequency
fVCO
fOUT
Maximum
Units
250
MHz
250
MHz
250
MHz
2400
2500
MHz
QCLK_y, N 1
2400
2500
MHz
QCLK_y, N 2
1200
1250
MHz
QCLK_y, N 4
600
625
MHz
QCLK_y, N 8
300
312.5
MHz
QCLK_y, N 10
240
250
MHz
QCLK_y, N 16
150
156.25
MHz
QCLK_y, N 20
120
125
MHz
QCLK_D, ND range: 29.99 to 8.33
80
300
MHz
Integer output divider N[A:C]
0
ppb
Fractional output divider ND,
fOUT 156.25MHz
10
ppb
CLK_n
Integer
Divider
Output Frequency Accuracy
Typical
0.008
156.25
FemtoClock NG
VCO Frequency Range
Output
Frequency
Minimum
10
Fractional
Divider
fOUT
Test Conditions
VIN
Input Voltage
Amplitude[c]
CLK_n
0.15
1.2
V
Differential
Input Voltage
Amplitude[c] [d]
CLK_n
0.3
2.4
V
VDIFF_IN
1.0
VDD_V – (VIN /
2)
V
55
%
VCMR
odc
tR / t F
Common Mode Input Voltage
Output Duty Cycle
QCLK_y
Output Rise/Fall Time,
Differential
QCLK_y (LVPECL), 20% to 80%
200
ps
QCLK_y (LVDS), 20% to 80%
300
ps
Output Rise/Fall Time
LVCMOS outputs, 20%-80%
1.2
ns
LVPECL
Output Voltage Swing,
Peak-to-peak, 156.25MHz
VO(PP)[e]
LVPECL
Differential Output Voltage
Swing, Peak-to-peak,
156.25MHz
©2018 Integrated Device Technology, Inc
45
50
350mV amplitude setting
351
388
mV
500mV amplitude setting
477
528
mV
700mV amplitude setting
645
711
mV
850mV amplitude setting
770
850
mV
350mV amplitude setting
702
776
mV
500mV amplitude setting
954
1055
mV
700mV amplitude setting
1290
1422
mV
850mV amplitude setting
1540
1700
mV
50
May 15, 2018
8V19N478 Datasheet
Table 48. AC Characteristics, VDD_V = 3.3V ±5%, VDDO_V = (3.3V, 2.5V, or 1.8V) ±5%,
TA = -40°C to +85°C[a][b] (Cont.)
Symbol
Parameter
LVDS
Output Voltage Swing,
Peak-to-peak, 156.25MHz
VOD[f]
LVDS
Differential Output Voltage
Swing, Peak-to-peak,
156.25MHz
tsk(o)
Output Skew[g] [h]
All delays set to 0
tD, LOS
LOS State Detected
(measured in input reference
periods)
Test Conditions
Minimum
Typical
Maximum
Units
350mV amplitude setting
265
340
mV
500mV amplitude setting
362
465
mV
700mV amplitude setting
611
676
mV
850mV amplitude setting
746
818
mV
350mV amplitude setting
530
680
mV
500mV amplitude setting
724
929
mV
700mV amplitude setting
1222
1351
mV
850mV amplitude setting
1492
1635
mV
QCLK_y (same N divider)
60
ps
QCLK_y (any N divider, incident rising
edge)
50
ps
fIN 125MHz
2
TIN
fIN 125MHz
3
tD, LOCK
PLL Lock Detect
PLL re-lock time after a short-term
holdover scenario. Measured from LOS
to both PLLs lock-detect asserted;
hold-off timer 200,
VCXO-PLL bandwidth 30Hz, 100Hz
initial frequency error > 20. RZ is calculated 32.2k.
The VCXO gain KVCXO used for the device reference circuit is 10kHz/V. The charge-pump current of the VCXO-PLL is configurable from
50µA to 1200µA. The charge-pump current is programmed to ICP 800uA. For α 8, CZ is calculated to be 0.99µF. CZ greater than this
value assures α > 12. For example, the actual chosen value is the standard capacitor value of 1µF. For β 5, CP is calculated 24.7nF.
The standard capacitor value of CP 27ps ensures β > 7.
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Figure 11. Third-Order Loop Filter
VCXO
Control Input
LFV Output
(charge pump)
RP2
CZ
CP
CP2
RZ
Figure 11 shows a third-order loop filter. The filter is equivalent to the 2nd order filter in Figure 12 with the addition components RP2 and
CP2. The additional components RP2 and CP2 should be calculated as shown:
RZ CP
C P2 = ------------------------R P2
R P2 1.5 R Z
is the ratio between the 1st pole and the 2nd pole. should be greater than 3.
Example calculation for the 3rd order loop filter shown in Figure 11: Equivalent to the 2nd order loop filter calculation, RZ 33k, CZ
1µF, and CP 27nF. RP2 should be in the range of 0.5·RZ < RP2 < 2.5·RZ, for instance 51k With 4, CP2 is 4.37nF (select 4.7µF).
FemtoClock NG PLL Loop Filter
Figure 12 shows a 2nd order loop filter for the FemtoClock NG PLL. This loop filter is equivalent to Figure 10 and uses the loop filter
components RZF (RZ), CZF (CZ), and CPZ (CP). The VCO frequency of the FemtoClock NG PLL is 2500MHz.
Figure 12. 2nd Order Loop Filer for FemtoClock NG PLL
LFFR
CZF
CPF
RZF
LFF
Example calculation for the 2nd order loop filter shown in Figure 12: the FemtoClock NG receives its reference frequency from the
VCXO output. With the PF pre-divider set to 1, the phase detector frequency is also 122.88MHz. The PLL feedback divider must be set to
MF 24 in order to locate the VCO frequencies in its center range. A target PLL loop bandwidth fC is 80kHz satisfies the condition in step
1. The gain of the internal VCO is 30MHz/V and the charge-pump current ICP is set to 3.6mA. Using the formula for RZ in step 2, RZF is
calculated 103 (chose the standard value of 100; using the formula for CZ in step 3, CZF is calculated 88nF for α 4. A capacitor
larger than 88nF should be used for CZF to assure that the α is greater than 4, for instance the standard component capacitor value
100nF.
With β 6, CPZ is calculated to be 3.6nF as shown in step 4. A capacitor less than 3.6nF should be used for CPZ to assure that β remains
greater than 6, for instance the standard capacitor value of 1nF is selected for CPZ. The selected 2nd order loop filter components are
RZF 100CZF 100nF and CPZ 1nF.
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Output Termination
LVPECL-style Outputs
Differential outputs configured to LVPECL-style are an open-emitter type, and require a termination with a DC current path to GND. This
section displays parallel and thevenin termination, Y-termination and source termination for various output supply (VDDO_V), and
amplitude settings. VTT is the termination voltage.
Figure 13. LVPECL Parallel Termination 1
VDD_v
Zo = 50
+
-
Zo = 50
LVPECL Dr iv er
R2
R1
50
50
H igh Impedance Input
N o Built-in T ermination
VTT
Table 50. Termination Voltage VTT (Figure 13)[a]
LVPECL Amplitude (mV)
VTT (V)
350
VDDO_V – 1.60
500
VDDO_V – 1.75
700
VDDO_V – 1.95
850
VDDO_V – 2.10
[a] Output power supplies supporting 3.3V, 2.5V and 1.8V are VDDO_QCLKA, VDDO_QCLKB, VDDO_QCLKC and
VDDO_QCLKD.
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Figure 14. LVPECL Parallel Termination 2
VD D_v
VDD_v
R1
R3
+
Zo = 50
-
Zo = 50
LVPECL Dr iv er
R2
R4
H igh Impedance Input
N o Built-in T ermination
Table 51. Termination Resistor Values (Figure 14)
VDDO_V (V)[a]
LVPECL Amplitude (mV)
R1, R3 ()
R2, R4 ()
350
97.1
103.1
500
106.5
94.3
700
122
84.6
850
137.5
78.6
350
138.8
78.1
500
166.7
71.4
700
227.3
64.1
850
312.5
59.5
350
450
56.3
500
–
50
3.3
2.5
1.8
[a] Output power supplies supporting 3.3V, 2.5V, and 1.8V are VDDO_QCLKA, VDDO_QCLKB, VDDO_QCLKC and VDDO_QCLKD.
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Figure 15. LVPECL Y-Termination
VDD_v
Zo = 50
+
-
Zo = 50
LVPECL Dr iv er
R2
R1
50
50
C1
0. 1uF (opt ional)
H igh Impedance Input
N o Built-in T ermination
R3
Table 52. Termination Resistor Values (Figure 15)
VDDO_V (V)[a]
LVPECL Amplitude (mV)
R3 ()
3.3
350, 500, 700, 850
50
2.5
350, 500, 700, 850
18
1.8
350, 500
0
[a] Output power supplies supporting 3.3V, 2.5V, and 1.8V are VDDO_QCLKA, VDDO_QCLKB, VDDO_QCLKC and VDDO_QCLKD.
Figure 16. LVPECL Source Termination
VDD_v
LVPECL Dr iv er
Z o = 50
+
R3
100
Z o = 50
R2
R1
High Impedance I nput
No Built-in Termination
Table 53. Termination Resistor Values (Figure 16)
VDDO_V (V)[a]
LVPECL Amplitude (mV)
R1, R2 ()
3.3
350, 500, 700, 850
100 – 200
2.5
350, 500, 700, 850
80 – 150
1.8
350
50 – 100
[a] Output power supplies supporting 3.3V, 2.5V, and 1.8V are VDDO_QCLKA, VDDO_QCLKB, VDDO_QCLKC and VDDO_QCLKD.
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LVDS-Style Outputs
LVDS style outputs support fully differential terminations. LVDS does not require board level pull-down resistors for DC termination.
Figure 17 and Figure 18 show typical termination examples with DC coupling for the LVDS style driver. In these examples, the receiver is
high input impedance without built-in termination. LVDS-style with a differential termination is preferred for best common-mode rejection
and lowest device power consumption.
Figure 17. LVDS Termination
VCC =3.3V
Z o = 50
+
R1
100
-
Z o = 50
LVDS St yle Driver
High Impedance I nput
No Built-in Termination
Figure 18. LVDS Termination (Alternative)
VDD_v
Zo = 50
+
-
Zo = 50
LVDS St yle Driver
R2
R1
50
50
H igh Impedance Input
N o Built- in T ermination
C1
0. 1uF (opt ional)
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Power Supply Filtering
Please refer to the document 8V19N470 Hardware Design Guide for comprehensive information about power supply and isolation, loop
filter design for VCXO and VCO, schematics, input and output interfaces/terminations and an example schematics. This document shows
a recommended power supply filter schematic in which the device is operated at VDD_V = 3.3V (the output supply voltages of VDDO_V =
3.3V, 2.5V, and 1.8V are supported). This example focuses on power supply connections and is not configuration specific. Refer to the
pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set for the application.
As with any high-speed analog circuitry, the power supply pins are vulnerable to the board supply or device generated noise. This device
requires an external voltage regulator for the VDD_V pins for isolation of board supply noise. This regulator (example component:
PS7A8300RGT) is indicated in the schematic by the power supply, VREG_3.3V. Consult the voltage regulator specification for details for
the required performance. To achieve optimum jitter performance, power supply isolation is required to minimize device generated noise.
The VDD_LCF terminal requires the cleanest power supply. The device provides separate power supplies to isolate any high switching
noise from coupling into the internal PLLs and into other outputs as shown. In order to achieve the best possible filtering, it is
recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If
space is limited, the 0.1µF and 0.01µF capacitors in each power pin filter should be placed on the device side. The other components
can be on the opposite side of the PCB. To set configuration pins, pull-up and pull-down resistors can all be placed on the PCB side,
opposite the device side, to free up device side area if necessary.
Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all devices.
Thermal Characteristics
Table 54. Thermal Characteristics for the 100-FPBGA Package[a]
Multi-Layer PCB, JEDEC Standard Test Board
Symbol
Thermal Parameter
Junction-to-ambient
JA
JC
Junction-to-case
Condition
Value[b]
Unit
0m/s air flow
24.06
°C/W
1m/s air flow
20.89
°C/W
2m/s air flow
19.07
°C/W
3m/s air flow
18.05
°C/W
4m/s air flow
17.46
°C/W
5m/s air flow
17.03
°C/W
8.54
°C/W
JB
Junction-to-board
[c]
6.43
°C/W
JB
Junction-to-board[d]
4.15
°C/W
[a] Standard JEDEC 2S2P multilayer PCB.
[b] Estimated thermal values.
[c] Thermal model where the majority (>90%) of the heat dissipated in the component is conducted through the package bottom (balls).
TB is measured on or near the component lead.
[d] Thermal model where the heat dissipated to the ambient from all directions. TB is measured on or near the component lead.
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8V19N478 Datasheet
Temperature Considerations
The device supports applications in a natural convection environment as long as the junction temperature does not exceed the specified
junction temperature TJ. In applications where the heat dissipates through the PCB, JB is the correct metric to calculate the junction
temperature. The following calculation uses the junction-to-board thermal characterization parameter JB to calculate the junction
temperature (TJ). Care must be taken to not exceed the maximum allowed junction temperature TJ of 125 °C.
The junction temperature TJ is calculated using the following equation: T J = T B + P TOT JB
where:
▪
▪
▪
▪
TJ is the junction temperature at steady state conditions in °C.
TB is the board temperature at steady state condition in °C, measured on or near the component lead.
JB is the thermal characterization parameter to report the difference between TJ and TB.
PTOT is the total device power dissipation.
Maximum power dissipation scenario: With the maximum allowed junction temperature and the maximum device power consumption and
at the maximum supply voltage of 3.3V + 5%, the maximum supported board temperature can be determined. In the device configuration
for the maximum power consumption, IDD_V is 1.024A. In this configuration, all outputs are active and configured to LVDS, the output
amplitude is set to 850mV and outputs use a 100 Ohm termination:
▪ Total system power dissipation (incl. termination resistor power): PTOT = VDD_V, MAX · IDD_V, MAX = 3.465V · 1.024A = 3.548W
In this scenario and with the Theta_JB thermal model, the maximum supported board temperature is as follows:
TB, MAX = TJ_MAX - Theta_JB · PTOT
TB, MAX = 125°C - 6.43°C/W · 3.548W = 102.2°C
Table 55. Typical Power Consumption
Device
Theta JB Thermal model
IDD_TOT
PTOT
TJ[a]
TB, MAX[b]
Test Case
A
W
C
C
1b
0.787
2.596
101.7
108.3
2b
0.887
2.928
103.8
106.2
3c
0.982
2.165
98.9
111.1
4c
0.927
2.051
98.2
111.8
5c
0.931
2.025
98.0
112.0
6c
0.857
1.881
97.1
112.9
[a] Junction temperature at board temperature TB = 85°C
[b] Maximum board temperature for junction temperature < 125°C: TB, MAX = TJ, MAX - JB x PTOT.
Package Outline Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information
is the most current data available.
www.idt.com/document/psc/bdbdg100-package-outline-110-mm-sq-body-10-mm-pitch-cabga
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8V19N478 Datasheet
Marking Diagram
1. Line 1 and Line 2 is the part number.
2. “#” denotes stepping.
3. “YYWW” denotes: “YY” is the last two digits of the year, and “WW” is a work week number
that the part was assembled.
4. “$” denotes the mark code.
Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
8V19N478BDGI
IDT8V19N478BDGI
11 11 1 mm 100-FPBGA
Tray
-40°C to +85°C
8V19N478BDGI8
IDT8V19N478BDG
11 11 1 mm 100-FPBGA
Tape and Reel
-40°C to +85°C
Glossary
Abbreviation
Description
Index n
Denominates an clock input. Range: 0 to 1.
Index x
Denominates a channel, channel frequency divider and the associated configuration bits. Range: A, B, C, D.
Index y
Denominates a QCLK output and associated configuration bits. Range: A0, A1, A2, B0, B1, B2, C0, C1, D0, D1.
VDD_v
Denominates core voltage supply pins. Range: VDD_QCLKA, VDD_QCLKB, VDD_QCLKC, VDD_QCLKD, VDD_I2C, VDD_INP,
VDD_LCV, VDD_LCF, VDD_CPV, VDD_CPF and VDD_OSC.
VDDO_v
Denominates output voltage supply pins. Range: VDDO_QCLKA, VDDO_QCLKB, VDDO_QCLKC and VDDO_QCLKD.
status_condition
Status conditions are: LOLV (Loss of VCXO-PLL lock), LOLF (Loss of FemtoClock NG-PLL lock) and LOS (Loss of
input signal).
[...]
Index brackets describe a group associated with a logical function or a bank of outputs.
{…}
List of discrete values.
Suffix V
Denominates a function associated with the VCXO-PLL.
Suffix F
Denominates a function associated with the 2nd stage PLL (FemtoClock NG).
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Revision History
Revision Date
Description of Change
May 15, 2018
Added Figure 5 (312.5MHz Output Phase Noise)
May 2, 2018
Initial release.
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without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same
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