FemtoClock® NG Jitter Attenuator
and Clock Synthesizer
8V19N490
Datasheet
Description
Features
The 8V19N490 is a fully integrated FemtoClock® NG jitter attenuator
and clock synthesizer designed as a high-performance clock solution
for conditioning and frequency/phase management of wireless base
station radio equipment boards. The device is optimized to deliver
excellent phase noise performance as required in GSM, WCDMA,
LTE, and LTE-A radio board implementations. The device supports
JESD204B subclass 0 and 1 clocks.
▪ High-performance clock RF-PLL with support for JESD204B
▪ Optimized for low-phase noise: -150dBc/Hz (800kHz offset;
245.76MHz clock)
▪ Integrated phase noise of 80fs RMS typical (12kHz–20MHz)
▪ Dual-PLL architecture
▪ First PLL stage with external VCXO for clock jitter attenuation
▪ Second PLL with internal FemtoClock NG PLL: 2949.12MHz
▪ Six output channels with a total of 19 outputs, organized in:
— Four JESD204B channels (device clock and SYSREF output)
with two, four and six outputs
— One clock channel with two outputs
— One VCXO output
▪ Configurable integer clock frequency dividers
▪ Supported clock output frequencies include: 2949.12, 1474.56,
983.04, 491.52, 245.76, and 122.88MHz
▪ Low-power LVPECL/LVDS outputs support configurable signal
amplitude, DC and AC coupling and LVPECL, LVDS line
terminations techniques
▪ Phase delay circuits:
— Clock phase delay with 256 steps of 339ps and a range of 0 to
86.466ns
— Individual SYSREF phase delay with 8 steps of 169ps
— Additional individual SYSREF fine phase delay with 25ps
steps
— Global SYSREF signal delay with 256 steps of 339ps and a
range of 0 to 86.466ns
▪ Redundant input clock architecture with four inputs, including:
— Input activity monitoring
— Manual and automatic, fault-triggered clock selection modes
— Priority controlled clock selection
— Digital holdover and hitless switching
— Differential inputs accept LVDS and LVPECL signals
▪ SYSREF generation modes include internal and external trigger
mode for JESD204B
▪ Supply voltage: 3.3V
▪ SPI and control I/O voltage: 1.8V/3.3V (selectable)
▪ Package: 11 11mm 100-CABGA
▪ Temperature range: -40°C to +85°C
A two-stage PLL architecture supports both jitter attenuation and
frequency multiplication. The first stage PLL is the jitter attenuator
and uses an external VCXO for best possible phase noise
characteristics. The second stage PLL locks on the VCXO-PLL
output signal and synthesizes the target frequency.
The device supports the clock generation of high-frequency clocks
from the selected VCO and low-frequency synchronization signals
(SYSREF). SYSREF signals are internally synchronized to the clock
signals. Delay functions exist for achieving alignment and controlled
phase delay between system reference and clock signals and to
align/delay individual output signals. The four redundant inputs are
monitored for activity. Four selectable clock switching modes are
provided to handle clock input failure scenarios. Auto-lock,
individually programmable output frequency dividers, and phase
adjustment capabilities are added for flexibility.
The device is configured through a 3-wire SPI interface and reports
lock and signal loss status in internal registers and via a lock detect
(LOCK) output. Internal status bit changes can also be reported via
the nINT output. The 8V19N490 is ideal for driving converter circuits
in wireless infrastructure, radar/imaging, and
instrumentation/medical applications. The device is a member of the
high-performance clock family from IDT.
Typical Applications
▪
▪
▪
▪
▪
▪
Wireless infrastructure applications: GSM, WCDMA, LTE, LTE-A
Ideal clock driver for jitter-sensitive ADC and DAC circuits
Low-phase noise clock generation
Ethernet line cards
Radar and imaging
Instrumentation and medical
©2017 Integrated Device Technology, Inc.
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8V19N490 Datasheet
Block Diagram
Figure 1. Block Diagram (fVCO = 2949.12MHz)
CLK_0
nCLK_0
CLK_1
nCLK_1
CLK_2
nCLK_2
Clock
Monitor
and
Selector
÷PV
PFD
CP
BYPV
OSC
÷PF
VDD_LCF
FDF
0
LFV
nOSC
÷MV0
CLK_3
nCLK_3
QOSC
nQOSC
VCXOPLL Loop
Filter
CR
PFD
CP
1
x2
fVCXO
fVCO
CR0
FemtoClockNG
LFF
BYPF
÷MF
0
FemtoClock
NG PLL
Loop Filter
÷MV1
1
LFFR
Holdover
÷NS
CLK_A
REF_S
÷NA
3
QREF_A0
nQREF_A0
0
1
REF_A0
MUX_A0
QREF_A1
nQREF_A1
0
REF_A1
SYSREF
Generator
EXT_SYS
1
MUX_A1
0
QREF_A2
nQREF_A2
1
REF_A2
QCLK_A[2:0]
nQCLK_A[2:0]
MUX_A2
Channel A
CLK_B
÷NB
2
0
QREF_B0
nQREF_B0
1
REF_B0
MUX_B0
0
REF_B1
CLK_C
QREF_B1
nQREF_B1
1
MUX_B1
Channel B
÷NC
2
0
MUX_C0
0
CLK_D
QCLKC_[1:0]
nQCLKC_[1:0]
QREF_C0
nQREF_C0
1
REF_C0
REF_C1
QCLK_B[1:0]
nQCLK_B[1:0]
QREF_C1
nQREF_C1
1
MUX_C1
Channel C
QCLK_D
nQCLK_D
÷ND
QREF_D
nQREF_D
0
1
REF_D
MUX_D
Channel D
CLK_E
÷NE
Channel E
SDAT
QCLK_E1
nQCLK_E1
SPI
SCLK
nCS
QCLK_E0
nQCLK_E0
nINT
Register
File
LOCK
SELSV
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8V19N490 Datasheet
Ball Map
Figure 2. Ball Map for 11 11 1.2mm 100-CABGA Package with 1mm Ball Pitch (Bottom View)
A
nQCLK
_A0
QCLK
_A0
GND
OSC
LFV
QREF
_B0
nQREF
_B0
VDD_
QCLKB
QCLK
_B0
nQCLK
_B0
B
nQCLK
_A1
QCLK
_A1
VDD_
OSC
nOSC
VDD_
CP
QREF
B1
nQREF
B1
VDD_
QREFB
QCLK
_B1
nQCLK
_B1
C
nQCLK
_A2
QCLK
_A2
nINT
QOSC
GND
SELSV
VDD_
QREFD
GND
GND
GND
D
VDD_
QCLKA
VDD_
QREFA
GND
nQOSC
GND
QREF
_D
nQREF
_D
VDD_
QCLKD
QCLK
_D
nQCLK
_D
E
nQREF
_A2
QREF
_A2
SDAT
GND
GND
SCLK
nCS
VDD_
SPI
GND
GND
F
nQREF
_A1
QREF
_A1
RES_
CAL
CLK0
CLK1
CLK2
CLK3
EXT_
SYS
QREF
_C0
nQREF
_C0
G
nQREF
_A0
QREF
_A0
LOCK
nCLK0
nCLK1
nCLK2
nCLK3
VDD_
INP
QREF
_C1
nQREF
_C1
H
GND
GND
GND
VDD_
SYNC
GND
GND
GND
GND
VDD_
QREFC
VDD_
QCLKC
J
nQCLK
_E1
QCLK
_E1
GND
GND
GND
CR0
VDD_
LCV
GND
QCLK
_C0
nQCLK
_C0
K
nQCLK
_E0
QCLK
_E0
VDD_
QCLKE
VDD_
CPF
LFF
LFFR
VDD_
LCF
GND
QCLK
C1
nQCLK
_C1
10
9
8
7
6
5
4
3
2
1
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8V19N490 Datasheet
Pin Descriptions
Table 1. Pin Descriptions
[a]
Ball
Name
Type[b]
F7
CLK_0
Input (PD)
G7
nCLK_0
Input PD/PU
F6
CLK_1
Input (PD)
G6
nCLK_1
Input PD/PU
F5
CLK_2
Input (PD)
G5
nCLK_2
Input PD/PU
F4
CLK_3
Input (PD)
G4
nCLK_3
Input PD/PU
A9,
Output
A10
QCLK_A0,
nQCLK_A0
Differential clock output A0 (Channel A). Configurable LVPECL/LVDS style and
amplitude.
B9,
B10
QCLK_A1,
nQCLK_A1
Output
Differential clock output A1 (Channel A). Configurable LVPECL/LVDS style and
amplitude.
C9,
Output
C10
QCLK_A2,
nQCLK_A2
Differential clock output A2 (Channel A). Configurable LVPECL/LVDS style and
amplitude.
G9,
G10
QREF_A0,
nQREF_A0
Output
Differential SYSREF/clock output REF_A0 (Channel A). LVDS style for SYSREF
operation, configurable LVPECL/LVDS style and amplitude for clock operation.
F9,
Output
F10
QREF_A1,
nQREF_A1
Differential SYSREF/clock output REF_A1 (Channel A). LVDS style for SYSREF
operation, configurable LVPECL/LVDS style and amplitude for clock operation.
E9,
E10
QREF_A2,
nQREF_A2
Output
Differential SYSREF/clock output REF_A2 (Channel A). LVDS style for SYSREF
operation, configurable LVPECL/LVDS style and amplitude for clock operation.
A2,
Output
A1
QCLK_B0,
nQCLK_B0
Differential clock output B0 (Channel B). Configurable LVPECL/LVDS style and
amplitude.
B2,
B1
QCLK_B1,
nQCLK_B1
Output
Differential clock output B1 (Channel B). Configurable LVPECL/LVDS style and
amplitude.
A5,
QREF_B0,
nQREF_B0
Output
Differential SYSREF/clock output REF_B0 (Channel B). LVDS style for SYSREF
operation, configurable LVPECL/LVDS style and amplitude for clock operation.
QREF_B1,
nQREF_B1
Output
B4
Differential SYSREF/clock output REF_B1 (Channel B). LVDS style for SYSREF
operation, configurable LVPECL/LVDS style and amplitude for clock operation.
J2,
J1
QCLK_C0,
nQCLK_C0
Output
Differential clock output C0 (Channel C). Configurable LVPECL/LVDS style and
amplitude.
K2,
QCLK_C1,
nQCLK_C1
Output
Differential clock output C1 (Channel C). Configurable LVPECL/LVDS style and
amplitude.
A4
B5,
K1
©2017 Integrated Device Technology, Inc.
Description
Device clock 0 inverting and non-inverting differential clock input. Inverting input is
biased to VDD_V /2 by default when left floating. Compatible with LVPECL, LVDS and
LVCMOS signals.
Device clock 1 inverting and non-inverting differential clock input. Inverting input is
biased to VDD_V /2 by default when left floating. Compatible with LVPECL, LVDS and
LVCMOS signals.
Device clock 2 inverting and non-inverting differential clock input. Inverting input is
biased to VDD_V /2 by default when left floating. Compatible with LVPECL, LVDS and
LVCMOS signals.
Device clock 3 inverting and non-inverting differential clock input. Inverting input is
biased to VDD_V /2 by default when left floating. Compatible with LVPECL, LVDS and
LVCMOS signals.
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8V19N490 Datasheet
Table 1. Pin Descriptions (Cont.)[a]
Ball
Name
Type[b]
F2,
F1
QREF_C0,
nQREF_C0
Output
Differential SYSREF/clock output REF_C0 (Channel C). LVDS style for SYSREF
operation, configurable LVPECL/LVDS style and amplitude for clock operation.
G2,
Output
G1
QREF_C1,
nQREF_C1
Differential SYSREF/clock output REF_C1 (Channel C). LVDS style for SYSREF
operation, configurable LVPECL/LVDS style and amplitude for clock operation.
D2,
D1
QCLK_D,
nQCLK_D
Output
Differential clock output D (Channel D). Configurable LVPECL/LVDS style and
amplitude.
D5,
Output
D4
QREF_D,
nQREF_D
Differential SYSREF/clock output REF_D (Channel D). LVDS style for SYSREF
operation, configurable LVPECL/LVDS style and amplitude for clock operation.
K9,
K10
QCLK_E0,
nQCLK_E0
Output
Differential clock output E0. Configurable LVPECL/LVDS style and amplitude.
J9,
Output
Differential clock output E1. Configurable LVPECL/LVDS style and amplitude.
J10
QCLK_E1,
nQCLK_E1
C7,
D7
QOSC,
nQOSC
Output
Differential VCXO-PLL clock outputs. Configurable LVPECL/LVDS style and amplitude.
nINT
Output
Status output pin for signaling internal changed conditions. Selectable 1.8/3.3V
LVCMOS interface levels.
LOCK
Output
PLL lock detect status output for both PLLs. Selectable 1.8/3.3V LVCMOS interface
levels.
EXT_SYS
Input (PD)
External SYSREF pulse trigger input. Selectable 1.8V/3.3V LVCMOS interface levels.
SDAT
Input/Output (PU)
Serial Control Port SPI Mode Data Input and Output. Selectable 1.8V/3.3V LVCMOS
interface levels. 3.3V tolerant when set to 1.8V and set to input.
SCLK
Input (PD)
Serial Control Port SPI Mode Clock Input. Selectable 1.8V/3.3V LVCMOS interface
levels. 3.3V tolerant when set to 1.8V.
nCS
Input (PU)
Serial Control Port SPI Chip Select Input. Selectable 1.8V/3.3V LVCMOS interface
levels. 3.3V tolerant when set to 1.8V.
SELSV
Input (PD)
SPI interface voltage select. 3.3V LVCMOS interface levels. For control input and SPI
interface voltage selection (see Table 25).
CR0
Analog
Internal VCO regulator bypass capacitor. Use a 4.7 µF capacitor between the CR0 and
the VDD_LCF (K4) terminals.
A6
LFV
Output
VCXO-PLL charge pump output. Connect to the loop filter for the external VCXO.
A7
OSC
Input (PD)
B7
nOSC
Input PD/PU
LFF
Output
Loop filter/charge pump output for the FemtoClock NG NG PLL. Connect to the
external loop filter.
K5
LFFR
Analog
Ground return path pin for the VCO loop filter.
F8
RES_CAL
Analog
Connect a 2.8 k (1%) resistor to GND for output current calibration.
C8
G8
F3
E8
E5
E4
C5
J5
K6
©2017 Integrated Device Technology, Inc.
Description
VCXO non-inverting and inverting differential clock input. Inverting input is biased to
VDD_V /2 by default when left floating. Compatible with LVPECL, LVDS and LVCMOS
signals.
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8V19N490 Datasheet
Table 1. Pin Descriptions (Cont.)[a]
Ball
Name
Type[b]
A8, C1,
C2, C3,
C6, D6,
D8, E1,
E2, E6,
E7, H3,
H4, H5,
H6, H8,
H9, H10,
J3, J6, J7,
J8, K3
GND
Power
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
D10
VDD_QCLKA
Power
Positive supply voltage (3.3V) for the QCLK_A[2:0] outputs.
D9
VDD_QREFA
Power
Positive supply voltage (3.3V) for the QREF_A[2:0] outputs.
A3
VDD_QCLKB
Power
Positive supply voltage (3.3V) for the QCLK_B[2:0] outputs.
B3
VDD_QREFB
Power
Positive supply voltage (3.3V) for the QREF_B[2:0] outputs.
H1
VDD_QCLKC
Power
Positive supply voltage (3.3V) for the QCLK_C[1:0] outputs.
H2
VDD_QREFC
Power
Positive supply voltage (3.3V) for the QREF_C[1:0] outputs.
D3
VDD_QCLKD
Power
Positive supply voltage (3.3V) for the QCLK_D outputs.
C4
VDD_QREFD
Power
Positive supply voltage (3.3V) for the QREF_D outputs.
K8
VDD_QCLKE
Power
Positive supply voltage (3.3V) for the QCLK_E[1:0] outputs.
E3
VDD_SPI
Power
Positive supply voltage (3.3V) for the SPI interface.
G3
VDD_INP
Power
Positive supply voltage (3.3V) for the differential inputs (CLK0 to CLK3).
J4
VDD_LCV
Power
Positive supply voltage (3.3V).
K4
VDD_LCF
Power
Positive supply voltage (3.3V).
K7
VDD_CPF
Power
Positive supply voltage (3.3V) for internal FemtoClock NG circuits.
B8
VDD_OSC
Power
Positive supply voltage (3.3V) for OSC, nOSC input and QOSC, nQOSC output.
B6
VDD_CP
Power
Positive supply voltage (3.3V) for internal VCXO_PLL circuits.
H7
VDD_SYNC
Power
Positive supply voltage (3.3V).
Description
[a] For essential information on power supply filtering, see Power Supply Design and Recommend Application Schematics.
[b] Pull-up (PU) and pull-down (PD) resistors are indicated in parentheses. For values, see Table 44.
©2017 Integrated Device Technology, Inc.
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8V19N490 Datasheet
Principles of Operation
Overview
The 8V19N490 generates low-phase noise, synchronized clock and SYSREF output signals locked to an input reference frequency. The
device contains two PLLs with configurable frequency dividers. The first PLL (VCXO-PLL, suffix V) uses an external VCXO as the oscillator
and provides jitter attenuation. The external loop filter is used to set the VCXO-PLL bandwidth frequency in conjunction with internal
parameters. The second, low-phase noise PLL (FemtoClock NG, suffix F) multiplies the VCXO-PL1L frequency to 2949.12MHz. The
FemtoClock NG PLL is completely internal and provides a central timing reference point for all output signals. From this point, fully
synchronous dividers generate the output frequencies and the internal timing references for JESD204B support.
The device supports the generation of SYSREF pulses m synchronous to the clock signals. There are five channels consisting of clock and/or
SYSREF outputs. The clock outputs are configurable with support for LVPECL or LVDS formats and a variable output amplitude. Clock and
SYSREF offer adjustable phase delay functionality. Individual outputs and channels and unused circuit blocks support powered-down states
for operating at lower power consumption. The register map, accessible through SPI interface with read-back capability controls the main
device settings and delivers device status information. For redundancy purpose, there are two selectable reference frequency inputs and a
configurable switch logic with priority-controlled auto-selection and holdover support.
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8V19N490 Datasheet
Phase-Locked Loop Operation
Frequency Generation
Table 2 displays the available frequency dividers for clock generation. The dividers must be set by the user to match input, VCXO and VCO
frequency, and to achieve frequency and phase lock on both PLLs. The frequency of the external VCXO is selected by the user; the internal
VCO frequency is set to 2949.12MHz. Example divider configurations for typical wireless infrastructure applications are shown in Table 3.
Table 2. PLL Operation and Divider Values
Operation for fVCO = 2949.12MHz
Divider
Range
Jitter Attenuation, Dual-PLL
with Deterministic
Input-to-Output Delay
(BYPV = 0, BYPF = 1)
VCXO-PLL
Pre-Divider PV
÷1…÷4095:(12 bit)
Input clock frequency:
VCXO-PLL
Feedback Divider
MV0
÷1…÷4095:
f VCXO
MF
f CLK = P V ---------------- ----------------------------PF
M V0 M V1
PLL Feedback
Divider[a] MV1
÷4…÷511: (9 bit)
FemtoClock NG
Pre-Divider PF
÷1…÷63: (6 bit)
FemtoClock NG
Feedback
Dividers MF
÷8 …÷511: (9 bit)
Jitter Attenuation, Dual-PLL
(BYPV = 0, BYPF = 0)
Input clock frequency:
(12 bit)
PV
f CLK = f VCXO ----------M V0
MV1 setting is not applicable
to PLL operation.
Frequency Synthesis
(VCXO-PLL Bypassed,
BYPV = 1)
Input clock frequency:
PV PF
f CLK = f VCO ------------------MF
MV0 and MV1 settings are not
applicable to the PLL
operation.
PF: Set PF to 0.5 in above
equation if the frequency
doubler is engaged by setting
FDF = 1.
VCXO frequency:
PF
f VCXO = f VCO -------MF
PF: Set PF to 0.5 in above equation if the frequency doubler is
engaged by setting FDF = 1.
Output Divider Nx ÷1…÷160
(x = A, B, C, D, E)
Output frequency:
SYSREF
Divider[b] NS
SYSREF frequency/rate:
÷16…÷5120:
{2, 4} {2, 4, 8, 16}
{2, 4, 8, 16} {2,
3, 4, 5}
f VCO
f OUT = -----------NX
f VCO
f SYSREF = -----------NS
[a] For input monitoring, configure MV1 as described in Monitoring and LOS of Input Signal.
[b] For SYSREF operation, configure SYNC[6:0] as described in Synchronizing SYSREF and Clock Output Dividers.
©2017 Integrated Device Technology, Inc.
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8V19N490 Datasheet
VCXO-PLL
The prescaler PV and the VCXO-PLLs feedback divider MV0 and MV1 require configuration to match the input frequency to the
VCXO-frequency. The BYPF setting allows to route the VCXO-PLLs feedback path through the MV0 divider. Alternatively, the feedback path is
routed through the second PLL and both the MV0 and MV1 feedback divider. MV0 has a divider value range of 12 bit; MV1 has 9 bit. The
feedback path through the second PLL, in combination with the divider setting PF = ÷1, is the preferred setting for achieving deterministic
delay from the clock input to the outputs. Multiple divider settings are available to enable support for input frequencies of e.g., 245.76MHz,
122.88MHz, 61.44MHz and 30.72MHz and the VCXO-frequencies of 122.88MHz, 61.44MHz, 38.4MHz, 30.72MHz, and 245.76MHz. In
addition, the range of available input and feedback dividers allows to adjust the phase detector frequency independent of the input and VCXO
frequencies. In general, the phase detector may be set into the range from 120kHz to the input reference frequency. The VCXO-PLL charge
pump current is controllable via registers and can be set in 50µA steps from 50µA to 1.6mA. The VCXO-PLL may be bypassed: the
FemtoClock NG PLL locks to the pre-divider input frequency.
Table 3. Example Configurations for fVCXO = 122.88MHz[a]
VCXO-PLL Divider Settings
Input Frequency (MHz)
PV
MV0
fPFD (MHz)
2
1
122.88
32
16
7.68
256
128
0.96
2048
1024
0.12
1
1
122.88
16
16
7.68
128
128
0.96
1024
1024
0.12
245.76
122.88
[a] BYPF = 0.
Table 4. Example Configurations for fVCXO = 38.4MHz[a]
VCXO- PLL Divider Settings
Input Frequency (MHz)
PV
MV0
fPFD (MHz)
32
5
7.68
128
20
1.92
512
80
0.48
2048
320
0.12
16
5
7.68
64
20
1.92
256
80
0.48
1048
320
0.12
245.76
122.88
[a] BYPF = 0.
©2017 Integrated Device Technology, Inc.
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8V19N490 Datasheet
Table 5. VCXO-PLL Bypass Settings
BYPV
Operation
0
VCXO-PLL operation.
1
VCXO-PLL bypassed and disabled. The reference clock for the FemtoClock NG PLL is the input clock divided by the pre-divider
PV. The input clock selection must be set to manual by the user. Clock switching and holdover are not defined. The device will not
attenuate input jitter. No external VCXO component and loop filter required.
Table 6. PLL Feedback Path Settings
Operation[a]
BYPF
0
VCXO-PLL feedback path through the MV0 divider. FemtoClock NG feedback path uses the MF divider.
1
VCXO-PLL feedback path through the MV1 MV0 dividers. FemtoClock NG feedback path uses the MF divider. Preferred setting
for achieving deterministic delay from input to the outputs.
[a] Regardless of the selected internal feedback path, the MV1 divider should be set to match its internal output frequency to the input reference frequency:
the MV1 output signal is the internal reference for input loss-of-signal detect.
FemtoClock NG PLL
This PLL locks to the output signal of the VCXO-PLL (BYPV = 0). It requires configuration of the frequency doubler FDF or the pre-divider PF
and the feedback divider MF to match the VCXO-PLL frequency to the VCO frequency of 2949.12MHz. This PLL is internally configured to
high-bandwidth. Best phase noise is typically achieved by engaging the internal frequency doubler (FDF = 1). If engaged, the signal from the
first PLL stage is doubled in frequency, increasing the phase detector frequency of the FemtoClock NG PLL. Enabling the frequency doubler
disables the frequency pre-divider PF. If the frequency doubler is not used (FDF = 0), the PF pre-divider has to be configured. Typically PF is
set to ÷1 to keep the phase detector frequency as high as possible. Set PF to other divider values to achieve specific frequency ratios (1 to
19.2, 1 to 76.8, etc.) between first and second PLL stage.
Table 7. Frequency Doubler
FDF
Operation
0
Frequency doubler off. PF divides clock signal from VCXO-PLL or input (in bypass).
1
Frequency doubler on. Signal from VCXO-PLL or input (in bypass) is doubled in frequency. PF divider has no effect.
Table 8. Example PLL Configurations
FemtoClock NG Divider Settings
VCXO-Frequency (MHz)
122.88
122.88
38.4
FDF
x2
–
–
PF
–
1
5
MF
Nx[a]
Output Frequency (MHz)
12
3
6
12
24
983.04
491.52
245.76
122.88
24
3
6
12
24
983.04
491.52
245.76
122.88
384
3
6
12
24
983.04
491.52
245.76
122.88
[a] x = A to E.
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8V19N490 Datasheet
Channel Frequency Divider
The device supports five independent channels A to E. Each channel has a frequency divider Nx (x = A to E) that divides the VCO frequency
to the output frequency. Each divider be individually set to a value in the range of ÷1 to ÷160. For typical divider values (see Table 9). For the
complete set of supported divider values (see Table 28).
Table 9. Integer Frequency Divider Settings
Output Clock Frequency (MHz)
Channel Divider Nx[a]
fVCO = 2949.12 (MHz)
÷1
2949.12
÷2
1474.56
÷3
983.04
÷4
737.28
÷6
491.52
÷8
368.64
÷12
245.76
÷16
184.32
÷24
122.88
÷30
98.304
÷32
92.16
÷36
81.92
÷48
61.44
÷60
49.152
÷64
46.08
÷72
40.96
÷96
30.72
÷120
24.576
÷128
23.04
[a] x = A to E.
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Redundant Inputs
The four inputs are compatible with LVDS and LVPECL signal formats, and also support single-ended LVCMOS signals. For applicable input
interface circuits, see Application Information.
Monitoring and LOS of Input Signal
The four inputs of the device are individually monitored for activity. Inactivity is defined by a static input signal.
The clock input monitors compare the device input frequency (fCLK) to the frequency of the VCO divided by MV1 (regardless of the internal
feedback path using or not using MV1). A clock input is declared invalid with the corresponding LOS (Loss-of-input signal) indicator bit set after
three consecutive missing clock edges. For correct operation of the LOS detect circuit, M V1 must be powered on by setting PD_MV1 = 0.
The MV1 divider must be set so that the LOS detect reference frequency matches the input frequency. For instance, if the input frequency is
245.76MHz, MV1 should be set to ÷12: The VCO frequency of 2949.12MHz divided by 12 equals the input frequency of 245.76MHz. For an
input frequency of 122.88MHz, set MV1 to ÷24. Failure to set MV1 to match the input frequency will result in added latency to the LOS circuit
(if, fVCO ÷ MV1 < fCLK) or false LOS indication (if, fVCO ÷ MV1 > fCLK). The minimum frequency that the circuit can monitor is:
fVCO / MV1(MAX) = 5.77MHz. In applications with a lower input frequency than 5.77MHz, disable the monitor to trigger the status flags by setting
BLOCK_LOR = 1.
If differential input signals are applied, the input will also detect an LOS condition in case of a zero differential input voltage.
Input Re-Validation
A clock input is declared valid and the corresponding LOS status bit is reset after the clock input signal returns for user-configurable number of
consecutive input periods. This re-validation of the selected input clock is controlled by the CNTV setting (verification pulse counter).
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Clock Selection
The device supports four input selection modes: manual, short-term holdover, and two automatic switch modes. The modes are described in
the following table.
Table 10. Clock Selection Settings
Mode
Description
Application
Manual
nM/A[1:0] = 00
Input selection follows user configuration of SEL[1:0]. Selection is never changed by
the internal state machine. A failing reference clock will cause an LOS event and the
PLL will unlock if the failing clock is selected. Re-validation of the selected input
clock will result in the PLL to re-lock on that input clock.
Startup and external
selection control
Automatic
Input selection follows LOS status by user preset input switch priorities. A failing
input clock will cause an LOS event for that clock input. If the selected clock has an
LOS event, the device will immediately initiate a clock fail-over switch. The switch
target is determined by pre-set input priorities.
No valid clock scenario: If no valid input clocks exist, the device will not attempt to
switch and will not enter the holdover state. The PLL is not locked. Re-validation of
any input clock that is not the selected clock will result in the PLL to attempt to lock
on that input clock.
For additional information see, Revertive Switching.
Multiple inputs with
qualified clock signals
Input selection follows user-configuration of SEL[1:0]. Selection is never changed by
the internal state machine. A failing reference clock will cause an LOS event. If the
selected reference fails, the device will enter holdover immediately. Re-validation of
the selected input clock is controlled by the CNTV setting. A successful re-validation
will result in the PLL to re-lock on that input clock.
Single reference
nM/A[1:0] = 01
Shot-term Holdover
nM/A[1:0] = 10
For additional information see, Short-Term Holdover.
Automatic with
Holdover
nM/A[1:0] = 11
Input selection follows LOS status by user preset input priorities. Each failing input
clock will cause an LOS event for that clock input. If the selected clock detects an
LOS event, the device will go into holdover and the hold-off down-counter (CNTH)
starts. The device initiates a clock fail-over switch after expiration of the hold-off
counter. The switch target is determined by the preset input priorities.
No valid clock scenario: If no valid input clocks exist, the device will not attempt to
switch and will remain in the holdover state. Re-validation of any input clock will
result in the PLL to attempt to lock on that input clock.
Multiple inputs
For additional information see, Automatic with Holdover (nM/A[1:0] = 11), and
Revertive Switching.
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Holdover
In holdover state, the output frequency and phase is derived from an internal, digital value based on previous frequency and phase
information. Holdover characteristics are defined in Table 51.
Input Priorities
Configurable settings encompass four selectable priorities with the range 0 (lowest priority) to 3 (highest priority). The user can change the
input priorities at any time. In the automatic switch modes, input priority changes may cause immediate input selection changes.
Hold-off Counter
A configurable down-counter applicable to the “Automatic with holdover” selection mode. The purpose of this counter is a deferred,
user-configurable, input switch after an LOS event. The hold-off counter is triggered by a transition of ST_REF upon detection of an LOS
event. The counter expires when a zero-transition occurs; this triggers a new reference clock selection. The counter is clocked by the
frequency-divided VCXO-PLL signal. The CNTR setting determines the hold-off counter frequency divider and the CNTH setting the start value
of the hold-off counter. For instance, set CNTR to a value of ÷131072 to achieve 937.5Hz (or a period of 1.066ms at fVCXO = 122.88MHz): the
8-bit CNTH counter is clocked by 937.5Hz and the user configurable hold-off period range is 0ms (CNTH = 0x00) to 272ms (CNTH = 0xFF).
After the counter expires, it reloads automatically from the CNTH SPI register. After the LOS status bit (LS_CLK_n) for the corresponding input
CLK_n has been cleared by the user, the input is enabled for generating a new LOS event.
The CNTR counter is only clocked if the device is configured in the clock selection mode, Automatic with holdover, and the selected reference
clock experiences an LOS event. Otherwise, the counter is automatically disabled (not clocked).
Revertive Switching
Revertive switching is applicable only to the two automatic switch modes shown in Table 10. When revertive switching is enabled, re-validation
of any non-selected input clock(s) will cause a new input selection according to the user-preset input priorities (revertive switch). An input
switch is only done if the re-validated input has a higher priority than the currently selected reference clock.
When revertive switching is disabled, re-validation of a non-selected input clock has no impact on the clock selection. Default setting is
revertive switching disabled.
Short-Term Holdover
If an LOS event is detected on the reference clock designated by the SEL[1:0] bits:
1. Holdover begins immediately.
2. ST_REF, LS_REF go low immediately.
3. No transitions will occur of the active REF clock; ST_SEL[1:0] does not change.
4. The hold-off countdown is not active.
When the designated reference clock resumes and has met the programmed validation count of consecutive rising edges:
1. Holdover turns off.
2. ST_SEL[1:0] does not change.
3. ST_REF returns to 1.
LS_REF can be cleared by an SPI write of 1 to that register.
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Automatic with Holdover (nM/A[1:0] = 11)
If an LOS event is detected on the active reference clock:
1. Holdover begins immediately.
2. Corresponding ST_REF and LS_REF go low immediately.
3. Hold-off countdown begins immediately.
During this time, all clocks continue to be monitored and their respective ST_CLK, LS_CLK flags are active. LOS events will be indicated on
ST_CLK, LS_CLK when they occur.
If the active reference clock resumes and is validated during the hold-off countdown:
1. Its ST_CLK status flag will return high and the LS_CLK is available to be cleared by an SPI write of 1 to that register bit.
2. No transitions will occur of the active REF clock; ST_SEL[1:0] does not change. LS_REF can be cleared by an SPI write of 1 to that register.
3. Revertive bit has no effect during this time (whether 0 or 1).
When the hold-off countdown reaches zero.
If the active reference has resumed and has been validated during the countdown, it will maintain being the active reference clock:
1. ST_SEL1:0 does not change.
2. ST_REF returns to 1.
3. LS_REF can be cleared by an SPI write of 1 to that register.
4. Holdover turns off and the VCXO-PLL attempts to lock to the active reference clock
If the active reference has not resumed, but another (sorted by next priority) clock input CLK_n is validated, then:
1. ST_SEL1:0 changes to the new active reference.
2. ST_REF returns to 1.
3. LS_REF can be cleared by an SPI write of 1 to that register.
4. Holdover turns off.
If there is no validated CLK:
1. ST_SEL1:0 does not change.
2. ST_REF remains low.
3. LS_REF cannot be cleared by an SPI write of 1 to that register.
4. Holdover remains active.
Revertive capability returns if REVS = 1.
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VCXO-PLL Lock Detect (LOLV)
The VCXO-PLL lock detect circuit uses the signal phase difference at the phase detector as loss-of-lock criteria. Loss-of-lock is reported if the
actual phase difference is larger than a configurable phase window set by the MV0 and PV configuration bits. Configuration of the width
window allows for a application-specific loss-of-lock reporting. A loss-of-lock state is reported through the nST_LOLV and nLS_LOLV status bit
(see Table 22).
Loss-of-Lock Window Description
The selected clock input signal is the reference signal (CLK) for lock detection. The rising edge of CLK defines the reference point t0. PV
configures the start of the lock window tB (which occurs before t0) and MV0 configures the end of the window tE (which occurs after t0). The
width of the lock window is defined by tE – tB. The VCXO-PLL declares lock when the rising edge of the feedback signal (FB) is within this
window, otherwise the PLL reports loss-of-lock.
Figure 3. Lock Detect Window
Input
CLK
FB
÷PV
PFD
CP
LFV
CLK
VCXO
÷MV0
FB
BYPF
VCXO
tB
0
1
÷MV1
VCO
t0
tE
Lock detected if FB in this window
Table 11. tB and tE Calculation
Operation
Jitter Attenuation, Dual-PLL with
deterministic Input-to-Output Delay
(BYPV = 0, BYPF = 1)
Jitter Attenuation, Dual-PLL
(BYPV = 0, BYPF = 0)
PV
tB
–1
t B = – 2--------------------f CLK
tE
MV0
MV0
2
– 1 M V1
t E = ----------------------------------------------f VCO
–1
t E = 2------------------------f VCXO
Figure 3 shows that PV configures the begin and MV0 the end of the window in integer multiples of PLL input and feedback periods. Both
PV and MV0 use three configuration bits with valid settings from 010 to 111 (2 to 7, decimal). This range allows configuring both tB and tE
from 3 to 127 periods of the input signal (TIN) and the feedback signal (TFB), respectively, is implied.
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Loss-of-Lock Window Configuration Example
With given PV, MV0, and MV1 divider values, select the corresponding PV and MV0 settings from Table 12 and apply the PV and MV0
values to the PV[1:0] and MV0[1:0] registers. Table 12 shows the lock window calculation formulas. For instance, if an input frequency of
245.76MHz and a PV divider of 128 is desired, set PV[1:0] to a binary value of 100 (decimal 4). This results in tB = -61.035ns (15 periods of
4.069ns). With a VCXO-PLL (BYPF = 0) and a VCXO frequency of 122.88MHz and MV0 = 64, select 011 (decimal 3) resulting in tE = 56.96ns
(7 periods of 8.138ns) and an overall lock detect window of tE – tB = 56.96ns + 61.035ns = 118.001ns. The user may select a smaller lock
detect window. For instance, a PV divider of 128 allows to set PV[1:0] to 010, 011 or 100 (decimal 2 to 4). Correspondingly, a MV0 divider of
64 allows MV0[1:0] settings from 010 to 011 (decimal 2 to 3). With smaller settings, the lock detect window size is reduced exponentially.
PV[1:0] = 000 will set tB to 0.5 TREF, and PV[1:0] = 001 will set tB to 1.5 TREF.
MV0[1:0] = 000 will set tE to 0.5 TREF, and MV0[1:0] = 001 will set tE to 1.5 TREF.
Table 12. Recommended Lock Detector Phase Window Settings
PV Divider Value
PV[1:0] Setting
MV0 Divider Value
MV0[1:0] Setting
1–31
N/A
1–31
N/A
32–63
010
32–63
010
64–127
≤011
64–127
≤011
128–255
≤100
128–255
≤100
256–511
≤101
256–511
≤101
512–1023
≤110
512–1023
≤110
1024 and higher
≤111
1024 and higher
≤111
FemtoClock NG Loss-of-Lock (LOLF)
FemtoClock NG-PLL loss-of-lock is signaled through the nST_LOLF (momentary) and nLS_LOLF (sticky, resettable) status bits and can
reported as hardware signal on the LOCK output as well as an interrupt signal on the nINT output.
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Channel, Output, and JESD204B Logic
Channel
Each of the four channels, A to D, consists of one to three clock outputs, and one associated to three SYSREF outputs. Each SYSREF output
in a channel can be individually configured to generate JESD204B (SYSREF) signals or copy the clock signal of that channel. The fifth channel
(E) consists of two clock outputs without SYSREF support in that channel.
If JESD204B/SYSREF operation is assigned to a QREF output, the channel logic controls the outputs: outputs automatically turn on and off in
a SYSREF sequence. QREF outputs configured to clock operation can have individually configured output states.
Table 13. Channel Configuration[a]
MUX_r
0
1
Description
Clock Configuration
JESD204B
QCLK_y
Clock signal
Clock signal
QREF_r
SYSREF/JESD204B
Frequency Divider
QCLK_y and QREF_r: Nx
QCLK_y: Nx
QREF_r: NS (Global to all QREF_r)
Phase Delay
QCLK_y and QREF_r: CLK_x
QCLK_y: CLK_x
REF_r settings do not apply
QREF_r: REF_r
Power-down
Per output
Per channel
Output Enable
Per output
Per output
[a] x = A to E
y = A0, A1, A2, B0, B1, C0, C1, D, E0, E1;
r = A0, A1, A2, B0, B1, C0, C1, D.
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Differential Outputs
Table 14. Output Features
Output
Style
QCLK_y, QREF_r
(Clock)
LVPECL
LVDS
QREF_r
QOSC
Disable
Power-down
250-1000mV
4 steps
Yes
Yes
Controlled by SYSREF[c]
A[1:0] = 01
LVPECL
250–750mV
3 steps
LVDS
Termination
50 to VT
500mV
LVDS
(SYSREF)
Amplitude[a]
Yes
Yes
100
differential[b]
100 differential[b]
50 to VT
100 differential[b]
[a] Amplitudes are measured single-endedly. Differential amplitudes supported are 500mV, 1000mV, 1500mV and 2000mV.
[b] AC coupling and DC coupling supported.
[c] State of SYSREF outputs is controlled by an internal SYSREF state machine.
Table 15. Individual Clock Output Settings[a]
PD[b]
STYLE
EN[c]
A[1:0][d]
Output
Power
1
X
X
X
Off
0
XX
Termination
100 differential or no termination
100 differential (LVDS)
State
Amplitude (mV)
Off
X
Disable (logic low)
X
00
0
1
01
0
1
1
Enable
10
11
0
250
XX
On
500
750
1000
50 to VT (LVPECL)
00
50 to VT = VDD_V – 1.50V (LVPECL)
01
50 to VT = VDD_V – 1.75V (LVPECL)
10
50 to VT = VDD_V – 2.00V (LVPECL)
11
50 to VT = VDD_V – 2.25V (LVPECL)
X
Enable
250
500
750
Enable
1000
[a] Applicable to clock outputs: QCLK_y and QREF_r outputs in clock mode (MUX_r = 0).
[b] Power-down modes are available for the individual channels A-E and the outputs QCLK_y (A0 to E1).
[c] Output enable is supported on each individual QCLK_y and QREF_r output.
[d] Output amplitude control is supported on each individual QCLK_y and QREF_r output.
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Table 16. Individual SYSREF Output Settings[a]
PD
STYLE
EN
nBIAS
A[1:0]
Output
Power
Termination
State
Amplitude (mV)
1
X
X
X
X
Off
100 differential or no termination
Off
X
0
01
Disable (logic low)
X
Enable
500
0
0
1
0
1
X
1
0
0
XX
100 differential (LVDS)
On[b]
50 to VT = VDD_V – 1.50V
(LVPECL)
01
1
Line
bias[c]
XX
Disable (logic low)
X
Enable
500
[a] Applicable QREF_r outputs when configured as SYSREF output (MUX_r = 1).
[b] Output amplitude should be set to a 500mV swing (A[1:0] to 01) by SPI. SYSREF output states are controlled by an internal state machine. An internal
SYSREF event will automatically turn SYSREF outputs on. After the event, outputs are automatically turned off. Setting nBIAS = 1 will bias powered-off
outputs to the LVDS midpoint voltage.
[c] Output (both Q, and nQ) bias the line to the differential signal cross-point voltage. Available if output is AC-coupled and set to LVDS style.
Table 17. QOSC (VCXO-PLL Output) Settings
nPD
STYLE
A[1:0]
Output Power
Termination
Amplitude (mV)
0
X
X
Off
100 differential (LVDS) or no termination
1
0
00
On
100 differential (LVDS)
250
01
500
10
11
1
X
750
00
50 to VT = VDD_V – 1.50V (LVPECL)
01
50 to VT = VDD_V – 1.75V (LVPECL)
250
500
10
11
50 to VT = VDD_V – 2.00V (LVPECL)
750
Table 18. QREF_r Setting for JESD204B Applications
QREF_r Outputs (LVDS, 500mV Amplitude)
BIAS_TYPE
nBIAS_r
Initial
During SYSREF Event
SYSREF Completed
Application
0
0
Static low
(QREF = L, nQREF_r = H)
Start switching for the
number of configured
SYSREF pulses
Released to static low
(QREF = L, nQREF_r = H)
QREF_r DC coupled
1
1
0
Static low (QREF = L, nQREF_r = H)
Static LVDS crosspoint level
(QREF = nQREF_r = VOS)
1
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Start switching for the
number of configured
SYSREF pulses
Released to static LVDS
crosspoint level
(QREF = nQREF_r = VOS)
QREF_r AC coupled
Static LVDS crosspoint level (QREF = nQREF_r = VOS)
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Output Phase-Delay
Output phase delay is independently supported on both clock and SYSREF outputs.
Table 19. Delay Circuit Settings[a]
Delay Circuit
Clock CLK_x
Unit
Steps
Range (ns)
256
0–86.466
8
0–1.187
8
0–0.160
1 = 339ps
-----------f VCO
Alignment[b]
Incident rising clock edges are
aligned, independent of the divider
N_x across channels
Coarse delay:
SYSREF REF_r
SYSREF (Global)
REF_S
1 - = 169ps
--------------2f VCO
Fine delay:
0ps, 25ps, 50ps, 75ps,
85ps, 110ps, 135ps, 160ps
256
1 = 339ps
-----------f VCO
0–86.466
SYSREF rising edge is aligned to
the incident rising clock edge across
channels
Global alignment of SYSREF
signals
[a] Supports 12 SYSREF rising edge stops within a device clock period of 1017ps (983.04MHz), 2.034ns (491.52MHz), 4.096ns (245.76MHz), and
8.137ns (122.88MHz), respectively. Clock output inversion supported by setting phase delay to a 180° setting.
[b] Default configuration (all delay settings = 0). REF_r coarse delay values are exact, fine delay value vary over PVT by ±20%.
Configuration for JESD204B Operation
Synchronizing SYSREF and Clock Output Dividers
The SYNC[6:0] divider controls the release of SYSREF pulses at coincident QCLK_y clock edges. For SYSREF operation, set the SYNC
divider value to the least common multiple of the clock divider values Nx (x = A to E). For instance, if NA = NB = ÷2, NC = ND = ÷3, NE = ÷4,
set the SYNC divider to ÷12.
SYSREF Generation
A SYSREF event is the generation of one or more consecutive pulses on the QREF outputs. An event can be triggered by SPI commands or
by a signal-transition on the EXT_SYS input. The number of SYSREF pulses generated is programmable from 1 to 255. The SYSREF signal
can also be programmed to be continuous. The SYSREF pulse rate is configurable to the frequencies shown in Table 20. SYSREF output
pulses are aligned to coincident rising clock edges of the clock outputs QCLK_y. Device settings for phase alignment between QCLK_y and
QREF_r outputs is detailed in the section, QCLK to QREF Phase Alignment. The following SYSREF pulse generation modes are available and
configurable by SPI:
▪ Counted pulse mode: 1 to 255 pulses are generated by the device. SYSREF activity stops automatically after the transmission of the
selected number of pulses and the QREF output powers down.
▪ Continuous mode. The SYSREF signal is a clock signal.
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The generation of SYSREF pulses is configured by SPI commands and is available after the initial setup of output clock divider and QREF
phase delay stages. A SYSREF event will automatically turn on the SYSREF outputs. After the event, SYSREF outputs are automatically
turned off (power-down). SYSREF outputs with the nBIAS bit set high will bias the outputs at the LVDS crosspoint voltage level (requires
BIAS_TYPE = 1).
Table 20. SYSREF Generation[a]
SYSREF Operation (fSYSREF)
SRO
NS
fVCO = 2949.12MHz
Counted pulse mode
(Use the SRPC register to configure the number of generated SYSREF pulses)
0
÷64
46.08
÷96
30.72
÷128
23.04
÷192
15.36
÷256
11.52
÷384
7.68
÷512
5.76
÷768
3.84
÷1024
2.88
÷2048
1.44
÷4096
0.72
÷5120
0.576
Continuous pulse mode
1
÷64
46.08
÷96
30.72
÷128
23.04
÷192
15.36
÷256
11.52
÷384
7.68
÷512
5.76
÷768
3.84
÷1024
2.88
÷2048
1.44
÷4096
0.72
÷5120
0.576
[a] SRO and SRPC are global settings.
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Internal SYSREF Generation
SYSREF generation is set to internal (SRG = 0). The SRO setting defines if SYSREF pulses are counted or continuous and the NS[6:0] divider
sets the frequency. In counted pulse mode, the SRPC register contains the number of pulses to generate. Any number from 1 to 255 pulses
may be generated. SYSREF pulses are generated upon completion of the SPI command RS (SYSREF release). Setting RS activates the
SYSREF outputs, loads the number of pulses from the SRPC register and starts the generation of SYSREF pulses synchronized to the
incident edge of the clock signals. After the programmed number of pulses are generated, SYSREF outputs will go into logic low state or bias
the output voltage to the static LVDS crosspoint level (see Table 18 for settings and details). In continuous mode, SYSREF is a clock signal
and the content of the SRPC signal is ignored.
External SYSREF Generation
SYSREF generation is set to external (SRG = 1): SYSREF pulses are generated in response to the detection of a rising edge at the EXT_SYS
input. The EXT_SYS input rising edge releases SYSREF pulses. Both SRO and SRPC register settings apply as in internal SYSREF
generation mode for generating single shot and repetitive SYSREF output signals. Set RS = 1 to prepare for SYSREF generation; the
generation of SYSRE pulses is triggered by a rising edge at EXT_SYS pin.
QCLK to QREF (SYSREF) Phase Alignment
Figure 4 and Table 21 show how to achieve output phase alignment between the QCLK_y clock and the QREF_r SYSREF outputs. Output
phase will be different for different Nx dividers. For a given example in Figure 4, the closest (smallest phase error) output alignment is achieved
by setting the clock phase delay register QCLK_Y to 0x00, the coarse SYSREF output phase delay register REF_r to 0x01, fine SYSREF
delay to REF_F_r = 1 and the global REF_S delay register to 0x29. With a SYSREF phase delay setting of REF_r = 0x01, REF_F_r = 0,
the QREF_r output phase is in advance of the QCLK_y phase, which is applicable in JESD204B application. Phase delay settings and
propagation delays are dependent on the clock and SYSREF frequency dividers, but independent of the SYSREF generation mode
(SRG = 0 or SRG = 1). Recommended phase delay setting for several device configurations are shown in Table 21.
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Figure 4. QCLK to QREF Phase Alignment
Output Phase
Alignment
QCLK_y
QCLK_y = 0x00
QCLK_y
QCLK_y = 0x00
QREF_r
REF_r = 0x01
REF_r_F = 1
QREF_r in advance of QCLK_y
QCLK_y
QCLK_y = 0x00
QCLK_y
QCLK_y = 0x00
QREF_r
REF_r = 0x00
REF_r_F = 1
= 169ps
QREF_r
REF_r = 0x00
REF_r_F = 1
= 338ps
Table 21. Recommended Delay Settings for Closest Clock-SYSREF Output Phase Alignment[a]
Divider Configuration
CLK_y
REF_r
REF_r_F
REF_S
NA-E = ÷3
NS = ÷384
0x00
0x01
1
0x29
0x00
0x01
1
0x29
0x00
0x03
1
0x00
NA-E = ÷3, ÷6,÷12
NS = ÷384
NA-E = ÷8
NS = ÷384
[a] QCLK and QREF outputs are aligned on the incident edge.
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Deterministic Phase Relationship and Phase Alignment
Input to output delay is deterministic when the device is configured as dual PLL with the BYPV = 0, BYPF = 1 (PLL feedback path through
MV0 MV1). Refer to the application note AN-952: 8V19N480/490 Design Guide for JESD204B Output Phase Alignment and Termination for
additional information on phase alignment, termination and coupling techniques.
Status Conditions & Interrupts
The device has an interrupt output to signal changes in status conditions. The devices have several conditions that can indicate faults and
status changes in the operation of the device. These are shown in Table 22, and can be monitored directly in the status registers. Status bits
(named: ST_condition) are read-only and reflect the momentary device status at the time of read-access. Several status bits are also copied
into latched bit positions (named: LS_condition). The latched version is controlled by the corresponding fault and status conditions and
remains set (“sticky”) until reset by the user by writing “1” to the status register bit. The reset of the status condition only has an effect if the
corresponding fault condition is removed, otherwise, the status bit will set again. Setting a status bit on several latched registers can be
programmed to generate an interrupt signal (nINT) via settings in the Interrupt Enable bits (named: IE_condition). A setting of “0” in any of
these bits will mask the corresponding latched status bits from affecting the interrupt status pin. Setting all IE bits to 0 has the effect of
disabling interrupts from the device. Interrupts are cleared by resetting the appropriate bit(s) in the latched register after the underlying fault
condition has been resolved. When all valid interrupt sources have been cleared in this manner, this will release the nINT output until the next
unmasked fault.
Table 22. Status Bit Functions
Status Bit
Function
Status if Bit is:
Momentary
Latched
ST_CLK_0
LS_CLK_0
ST_CLK_1
1
0
Interrupt Enable Bit
CLK 0 input status
Active
LOS
IE_CLK_0
LS_CLK_1
CLK 1 input status
Active
LOS
IE_CLK_1
ST_CLK_2
LS_CLK_2
CLK 2 input status
Active
LOS
IE_CLK_2
ST_CLK_3
LS_CLK_3
CLK 3 input status
Active
LOS
IE_CLK_3
nST_LOLV
nLS_LOLV
VCXO-PLL Loss-of-lock
Locked
Loss-of-lock
IE_LOLV
nLS_LOLF
FemtoClock NG-PLL Loss-of-lock
Locked
Loss-of-lock
IE_LOLF
Not in holdover
Device in
holdover
IE_HOLD
Not completed
Completed
—
nST_LOLF
[a]
nST_HOLD
nLS_HOLD
ST_VCOF
—
Description
Holdover
FemtoClock NG VCO calibration
Clock input selection
ST_SEL[1:0]
00 = CLK_0
01 = CLK_1
10 = CLK_2
—
—
11 = CLK_3
ST_REF
LS_REF
PLL reference status
Valid reference
Reference lost[b]
IE_REF
[a] If the VCXO-PLL is bypassed by setting BYPV = 1, VCXO-PLL lock status is blocked from affecting the LOCK pin.
[b] Manual and short-term holdover mode: 0 indicates if the reference selected by SEL[1:0] is lost, 1 if not lost.
Automatic with holdover mode: 0 indicates the reference is lost and while still in holdover, or no valid CLK[3:0].
Automatic mode: 0 indicates no valid CLK[3:0].
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Table 23. LOCK Output Function
Status Bit (PLL)
nST_LOLV (VCXO-PLL)
Locked[a]
Not locked
nST_LOLF (FemtoClock NG)
Status Reported on LOCK Output
Locked
1
Not locked
0
Locked
0
Not locked
0
[a] If the VCXO-PLL is bypassed by setting BYPV = 1, VCXO-PLL lock status is blocked from affecting the LOCK. pin.
Device Startup, Reset and Synchronization
At startup, an internal POR (power-on reset) resets the device and sets all register bits to their default value. The device forces the VCXO
control voltage at the LFV pin to half of the power supply voltage to center the VCXO-frequency. In the default configuration the QCLK_y and
QREF_r outputs are disabled at startup.
Recommended Configuration Sequence:
1. (Optional) set the value of the CPOL register bit to define the SPI read mode, so that SPI settings can be validated by subsequent SPI read
accesses.
2. Configure all PLL settings, output divider and delay circuits as well as other device configurations:
a. BYPF and BYPV for the desired PLL operation mode and configure the PLL dividers P V, MV0, MV1, MF and PF as required to achieve
PLL lock (see Table 2 for details).
b. VCXO-PLL lock detect window by configuring the phase settings MV0 and PV.
c. Charge pump currents for both PLLs (CPV[4:0] and CPF[4:0]) and POLV for the desired VCXO polarity.
d. (optional) OSVEN and OFFSET[4:0] for the VCXO-PLL static phase offset.
e. Channel dividers (see Table 8).
f. MUX_r for the desired operation of the QREF_r outputs.
g. QCLK_y, QREF_r and QOSC output features such as desired output power-down state, style and amplitude.
h. Desired input selection and monitoring modes: this involves nM/A[1:0] and SEL[1:0] for input selection. In any of the automatic modes,
configure PRIO[1:0]_n, and REVS. Configure the CNTH[7:0], CNTR[1:0] counters for the desired holdover characteristics and DIV4_VAL,
CNTV[1:0] for input revalidation if applicable to the operation mode.
i. Individual CLK_X and REF_r registers and the global delay REF_S register for the desired phase delay between clock and SYSREF
outputs; (see QCLK to QREF (SYSREF) Phase Alignment).
j. Interrupt enable configuration bits IE_status_condition, as desired for fault reporting on the nINT output.
3. For SYSREF operation:
a. Configure the NS and SYNC divider as described in, Synchronizing SYSREF and Clock Output Dividers.
b. Configure the SYSREF registers SRG, SRO and SRPC[7:0] according to the desired SYSREF operation.
4. Set the initialization bit INIT_CLK. This will initiate all divider and delay circuits and synchronize them to each other. The INIT_CLK bit will
self-clear.
5. Set both the RELOCK bit and PB_CAL bit. This step should not be combined with the previous step (setting INIT_CLK) in a multi SPI-byte
register access. Both bits will self-clear.
6. Clear the FVCV bit to release the VCXO control voltage and VCXO-PLL will attempt to lock to the input clock signal starting from its center
frequency.
7. Clear the status flags.
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8. At this point, the basic configuration of the registers 0x00 to 0x73 should be completed and the SPI transfer ended (set nCS to high level).
9. In a separate SPI write access, enable the outputs as desired by accessing the output-enable registers 0x74 and 0x76.
10. For SYSREF operation, see Step 9, SYSREF Frequency Divider, Delay and Starting/Re-Starting SYSREF Pulse Sequences.
Reserved registers and registers in the address range 0x78 to 0xFF should not be used. Do not write into any registers in the 0x78 to 0xFF
range.
Changing Frequency Dividers and Phase Delay Values
Clock Frequency Divider and Delay
The following procedure has to be applied for a change of a clock divider and phase delay value NA-E, and CLKA-E:
1. (Optional) set the value of the CPOL register to define the SPI read mode, so that SPI settings can be validated by subsequent SPI read
accesses.
2. (Optional) disable the outputs whose frequency divider or delay value is changed.
3. Configure the NA-E dividers and the delay circuits CLKA-E to the desired new values.
4. (Optional) configure the SYNC divider if required for synchronization between clock and SYSREF signals.
5. Set the initialization bit INIT_CLK. This will initiate all divider and delay circuits and synchronize them to each other. The INIT_CLK bit will
self-clear. During this initialization step, all QCLK_y and QREF_r outputs are reset to the logic low state.
6. Set the RELOCK bit. This step should not be combined with the setting INIT_CLK in a multi SPI-byte register access. Bit will self-clear.
7. (Optional) enable the outputs whose frequency divider was changed.
SYSREF Frequency Divider, Delay and Starting/Re-Starting SYSREF Pulse Sequences
The following procedure has to be applied for a change of a SYSREF divider and phase delay value NS and REF_S:
1. (Optional) set the value of the CPOL register to define the SPI read mode, so that SPI settings can be validated by subsequent SPI read
accesses.
2. (Optional) disable the outputs whose frequency divider or delay value is changed.
3. Configure any NS divider and any delay circuits REF_S to their desired new values.
4. Configure the SYNC divider if required for synchronization between clock and SYSREF signals.
5. Set the initialization bit INIT_CLK. This will initiate all divider and delay circuits and synchronize them to each other. The INIT_CLK bit will
self-clear. During this initialization step, all QCLK_y and QREF_r outputs are reset to the logic low state.
6. Set the RELOCK bit. This step should not be combined with the setting INIT_CLK in a multi SPI-byte register access. Bit will self-clear.
7. Set the SRO bit to counted pulse mode, or to continue pulse mode, as desired.
8. (Optional) enable the outputs whose frequency divider was changed.
9. For SYSREF operation, set the RS bit to start (or re-start) generating the configured number of SYSREF pulses.
a. In internal SYSREF generation mode (SRG = 0) the SYSREF pulses are generated as a result of setting the RS bit. Set RS for each
repeated SYSREF generation.
b. In external SYSREF mode the SYSREF pulses are generated at the next rising edge of the EXT_SYS input. Set RS before each rising
edge at the EXT_SYS input.
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SPI Interface
The device has a 3-wire serial control port capable of responding as a slave in an SPI configuration to allow read and write access to any of
the internal registers for device programming or read back. The SPI interface consists of the SCLK (clock), SDAT (serial data input and
output), and nCS (chip select) pins. A data transfer consists any integer multiple of 8 bits and is always initiated by the SPI master on the bus.
Internal register data is organized in SPI bytes of 8 bit each.
If nCS is at logic high, the SDAT data I/O is in high-impedance state and the SPI interface of the device is disabled.
In a write operation, data on SDAT will be clocked in on the rising edge of SCLK. In a read operation, data on SDAT will be clocked out on the
falling or rising edge of SCLK depending on the CPOL setting (CPOL = 0: output data changes on the falling edge, CPOL = 1: output data
changes on the rising edge).
Starting a data transfer requires nCS to set and hold at logic low level during the entire transfer. Setting nCS = 0 will enable the SPI interface
with SDAT in data input mode. The master must initiate the first 8-bit transfer. The first bit presented to the slave is the direction bit R/nW
(1 = Read, 0 = Write) and the following seven bits are the address bits A[0:6] pointing to an internal register in the address space 0 to 127.
Data is presented with the LSB (least significant bit) first.
Read operation from an internal register: A read operation starts with an 8 bit transfer from the master to the slave: SDAT is clocked on the
rising edge of SCLK. The first bit is the direction bit R/nW which must be to “1” to indicate a read transfer, followed by seven address bits
A[0:6]. After the first 8 bits are clocked into SDAT, the SDAT I/O changes to output: The register content addressed by A[0:6] is loaded into the
shift register and the next eight SCLK falling (CPOL = 1) clock cycles will then present the loaded register data on the SDAT output and
transfer these to the master. Transfers must be completed by de-asserting nCS after any multiple 8 of SCLK cycles. If nCS is de-asserted at
any other number of SCLKs, the SPI behavior is undefined. SPI byte (8 bit) and back-to-back read transfers of multiple registers are supported
with an address auto-increment. During multiple transfers, nCS must stay at logic low level and SDAT will present multiple registers (A),
(A +1), (A +2), etc. with each eight SCLK cycles. During SPI Read operations, the user may continue to hold nCS low and provide further bytes
of data for up to a total of 127 bytes in a single block read.
Write operation to a device register: During a write transfer, an SPI master transfers one or more bytes of data into the internal registers of
the device. A write transfer starts by asserting nCS to low logic level. The first bit presented by the master must set the direction bit R/nW to 0
(Write) and the seven address bits A[0:6] must contain the 7-bit register address. Bits D0 to D7 contain 8 bit of payload data, which is written
into the register addressed by A[0:6] at the end of a 8-bit write transfer. Multiple, subsequent register transfers from the master to the slave are
supported by holding nCS asserted at logic low level during write transfers. The 7 bit register address will auto-increment. Transfers must be
completed by de-asserting nCS after any multiple eight of SCLK cycles. If nCS is de-asserted at any other number of SCLKs, the SPI behavior
is undefined.
End of transfer: After nCS is de-asserted to logic “1”, the SPI bus is available to transfers to other slaves on the SPI bus.
The READ (Figure 5) and WRITE (Figure 6) diagrams display the transfer of two bytes of data from and into registers.
Registers 0x78 to 0xFF. Registers in the address range 0x78 to 0xFF should not be used. Do not write into any registers in the 0x78 to 0xFF
range.
Figure 5. Logic Diagram: READ Data from Registers for CPOL = 0 and CPOL = 1
SCLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
nCS
SDAT, CPOL=0
Hi-Imp
1 A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
SDAT, CPOL=1
Hi-Imp
1 A0 A1 A2 A3 A4 A5 A6
Input R=1, 7-bit Address
©2017 Integrated Device Technology, Inc.
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
Output Register Data
(Address)
28
Hi-Imp
Hi-Imp
Output Register Data
(Address+1)
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Figure 6. Logic Diagram: WRITE Data into Registers
SCLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
nCS
SDAT
Hi-Imp
0
A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
Input nW=0, 7-bit Address
Input Register Data (Address)
Hi-Imp
Input Register Data
(Address+1)
Table 24. SPI Read / Write Cycle Timing Parameters
Symbol
fSCLK
Parameter
Test Condition
Minimum
SCLK Frequency
Maximum
Unit
20
MHz
tS1
Setup Time, nCS (falling) to SCLK (rising)
5
ns
tS2
Setup Time, SDAT (input) to SCLK (rising)
5
ns
tS3
Setup Time, nCS (rising) to SCLK (rising)
5
ns
tH1
Hold Time, SCLK (rising) to SDAT (input)
5
ns
tH2
Hold Time, SCLK (falling) to nCS (rising)
5
ns
tPD1F
Propagation Delay, SCLK (falling) to SDAT
CPOL = 0
12
ns
tPD1R
Propagation Delay, SCLK (rising) to SDAT
CPOL = 1
12
ns
tPD2
Propagation Delay, nCS to SDAT (disable)
12
ns
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8V19N490 Datasheet
Figure 7. SPI Timing Diagram
tH2
nCS
tS3
tS1
SCLK
tS2
tH1
SDAT
(Input)
tPD1F
tPD1R
tPD2
SDAT
(Output)
High Impedance
Table 25. Serial Interface Logic Voltage
SELSV
SPI Interface (SCLK, SDAT, nCS, EXT_SYS) Logic Voltage
0 (default)
1.8V
1
3.3V
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Register Descriptions
List of Registers
Table 26. Configuration Registers
Register Address
Register Description
0x00–0x01
PLL Frequency Divider: MV, MV0
0x02–0x03
PLL Frequency Divider: MV1, BYPF
0x04–0x05
VCXO-PLL Control: Frequency Divider, PV, PV
0x06–0x07
Reserved
0x08–0x09
PLL Frequency Divider MF
0x0A
VCXO-PLL Control BYPV
0x0B
Reserved
0x0C
PLL Frequency Divider: PF, FDF
0x0D–0x0F
Reserved
0x10–0x12
VCXO-PLL Control, output state QOSC
0x13
Reserved
0x14
Input Selection Mode Priority
0x15
Input Selection Mode Switching
0x16
Input Selection Mode CNTH
0x17
Input Selection Mode: CNTR, CNTV
0x18
SYSREF Control: divider, PD
0x19
SYSREF Control SYNC
0x1A
SYSREF Control SRPC
0x1B
SYSREF Control REF_S
0x1C
SYSREF Control SRG, SRO
0x1D–0x1F
PLL Control
0x20–0x22
Channel A
0x23
Reserved
0x24
Output State QCLK_A0
0x25
Output State QCLK_A1
0x26
Output State QCLK_A2
0x27
Reserved
0x28
QREF_A0: delay, MUX
0x29
QREF_A1: delay, MUX
0x2A
QREF_A2: delay, MUX
0x2B
Reserved
0x2C
Output State QREF_A0
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Table 26. Configuration Registers (Cont.)
Register Address
Register Description
0x2D
Output State QREF_A1
0x2E
Output State QREF_A2
0x2F
Reserved
0x30–0x32
Channel B
0x33
Reserved
0x34
Output State QCLK_B0
0x35
Output State QCLK_B1
0x36–0x37
Reserved
0x38
QREF_B0: delay, MUX
0x39
QREF_B1: delay, MUX
0x3A–0x3B
Reserved
0x3C
Output State QREF_B0
0x3D
Output State QREF_B1
0x3E–0x3F
Reserved
0x40–0x42
Channel C
0x43
Reserved
0x44
Output State QCLK_C0
0x45
Output State QCLK_C1
0x46–0x47
Reserved
0x48
QREF_C0: delay, MUX
0x49
QREF_C1: delay, MUX
0x4A–0x4B
Reserved
0x4C
Output State QREF_C0
0x4D
Output State QREF_C1
0x4E–0x4F
Reserved
0x50–0x52
Channel D
0x53
Reserved
0x54
Output State QCLK_D
0x55–0x57
Reserved
0x58
QREF_D: delay, MUX
0x59–0x5B
Reserved
0x5C
Output State QREF_D
0x5D–0x5F
Reserved
0x60–0x62
Channel E
0x63
Reserved
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Table 26. Configuration Registers (Cont.)
Register Address
Register Description
0x64
Output State QCLK_E0
0x65
Output State QCLK_E1
0x66–0x67
Reserved
0x68–0x69
Interrupt Enable
0x6A–0x6B
Reserved
0x6C
Status (Latched)
0x6D
Status (Momentary)
0x6E
Status (Latched)
0x6F
Reserved
0x70
SYSREF Control RS
0x71–0x73
General Control
0x74–0x75
Output State QCLK
0x76
Output State QREF
0x77
Reserved
0x78–0x7A
Reserved
0x7B
Reserved
0x7C–0x7F
Reserved
0x80–0xFF
Reserved
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Register Descriptions
This section contains all addressable registers, sorted by function, followed for a detailed description of each bit field for each register. Several
functional blocks with multiple instances in this device have individual registers controlling their settings, but since the registers have an
identical format and bit meaning, they are described only once, with an additional table to indicate their addresses and default values. All
writable register fields will come up with a default values as indicated in the factory defaults column unless altered by values loaded from
non-volatile storage during the initialization sequence.
Fixed read-only bits will have defaults as indicated in their specific register descriptions. Read-only status bits will reflect valid status of the
conditions they are designed to monitor once the internal power-up reset has been released. Unused registers and bit positions are Reserved.
Reserved bit fields may be used for internal debug test and debug functions.
Channel and Clock Output Registers
The content of the channel register and clock output registers set the channel state, the clock divider, the QCLK output state and clock phase
delay.
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Table 27. Channel and Clock Output Register Bit Field Locations
Bit Field Location
Register Address
D7
D6
D5
D4
0x20: Channel A
0x30: Channel B
0x40: Channel C
0x50: Channel D
0x60: Channel E
0x24: QCLK_A0
0x25: QCLK_A1
0x26: QCLK_A2
0x34: QCLK_B0
0x35: QCLK_B1
0x44: QCLK_C0
0x45: QCLK_C1
0x54: QCLK_D
0x64: QCLK_E0
0x65: QCLK_E1
0x74
0x75
D2
D1
D0
Reserved
Reserved
Reserved
N_A[7:0]
N_B[7:0]
N_C[7:0]
N_D[7:0]
N_E[7:0]
0x21: Channel A
0x31: Channel B
0x41: Channel C
0x51: Channel D
0x61: Channel E
0x22: Channel A
0x32: Channel B
0x42: Channel C
0x52: Channel D
0x62: Channel E
D3
CLK_A[7:0]
CLK_B[7:0]
CLK_C[7:0]
CLK_D[7:0]
CLK_E[7:0]
PD_A
PD_B
PD_C
PD_D
PD_E
Reserved
Reserved
Reserved
Reserved
PD_A0
PD_A1
PD_A2
Reserved
Reserved
STYLE_A0
STYLE_A1
STYLE_A2
A_A0[1:0]
A_A1[1:0]
A_A2[1:0]
Reserved
PD_B0
PD_B1
Reserved
Reserved
STYLE_B0
STYLE_B1
A_B0[1:0]
A_B1[1:0]
Reserved
PD_C0
PD_C1
Reserved
Reserved
STYLE_C0
STYLE_C1
A_C0[1:0]
A_C1[1:0]
Reserved
PD_D
Reserved
Reserved
STYLE_D
A_D[1:0]
Reserved
PD_E0
PD_E1
Reserved
Reserved
STYLE_E0
STYLE_E1
A_E0[1:0]
A_E1[1:0]
Reserved
EN_QCLK_A0 EN_QCLK_A1 EN_QCLK_A2 EN_QCLK_B0 EN_QCLK_B1 EN_QCLK_C0 EN_QCLK_C1 EN_QCLK_D
Reserved
Reserved
©2017 Integrated Device Technology, Inc.
Reserved
Reserved
35
Reserved
Reserved
EN_QCLK_E1 EN_QCLK_E0
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8V19N490 Datasheet
Table 28. Channel and Clock Output Register Descriptions[a]
Bit Field Location
Bit Field Name
Field Type
Default (Binary)
N_x[7:0]
R/W
0000 0100
Value: ÷6
PD_x
R/W
0
Description
Output Frequency Divider N:
N_x[7:0]
Divider Value
1000 0000
÷1
0100 0011
÷10
0000 0000
0000 0001
÷2
÷3
0100 0100
0100 0110
÷12
÷16
0000 0010
0000 0011
÷4
÷5
0100 1011
0100 1100
÷20
÷24
0000 0100
0000 0110
÷6
÷8
0101 0011
÷30
0101 1011
÷40
0100 1110
0101 0100
÷32
÷36
0101 0110
÷48
0110 0011
÷50
0110 0100
÷60
0101 1110
÷64
0101 1111
÷72
0110 0110
÷80
0110 1110
÷96
0111 1011
÷100
0111 1100
0111 0110
÷120
÷128
0111 1110
÷160
0 = Channel x is powered-up.
1 = Channel x is powered-down.
PD_y
R/W
0
CLK_x[7:0]
R/W
0000 0000
0 = Output QCLK_y is powered-up.
1 = Output QCLK_y is powered-down.
CLK_x Phase Delay:
CLK_x[7:0]
Delay in ps = CLK_x 339ps (256 steps):
0000 0000 = 0ps
…
1111 1111 = 86.466ns
©2017 Integrated Device Technology, Inc.
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8V19N490 Datasheet
Table 28. Channel and Clock Output Register Descriptions[a] (Cont.)
Bit Field Location
Bit Field Name
Field Type
Default (Binary)
A_y[1:0]
R/W
00
STYLE_y
R/W
0
Description
QCLK_y Output Amplitude
Setting for STYLE = 0 (LVDS)
Setting for STYLE = 1 (LVPECL)
A[1:0] = 00: 250mV
A[1:0] = 01: 500mV
A[1:0] = 00: 250mV
A[1:0] = 01: 500mV
A[1:0] = 10: 750mV
A[1:0] = 11:1000mV
A[1:0] = 10: 750mV
A[1:0] = 11:1000mV
Termination: 100 across
Termination: 50 to VT
QCLK_y Output Format:
0 = Output is LVDS (requires an LVDS 100 output termination).
1 = Output is LVPECL (requires an LVPECL 50 output termination of the
specified recommended termination voltage).
EN_y
R/W
0
QCLK_y Output Enable:
0 = QCLK_y Output is disabled at the logic low state.
1 = QCLK_y Output is enabled.
[a] x = A, B, C, D, E;
y = A0, A1, A2, B0, B1, C0, C1, D, E0, E1;
r = A0, A1, A2, B0, B1, C0, C1, D.
©2017 Integrated Device Technology, Inc.
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8V19N490 Datasheet
QREF Output State Registers
The content of the output registers set the output frequency and divider, several output states, the power state, the output style and amplitude.
Table 29. QREF Output State Register Bit Field Locations[a]
Bit Field Location
Register Address
0x28: QREF_A0
0x29: QREF_A1
0x2A:QREF_A2
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
REF_F[1:0]_A0
REF_F[1:0]_A1
REF_F[1:0]_A2
MUX_A0
MUX_A1
MUX_A2
REF_A0[2:0]
REF_A1[2:0]
REF_A2[2:0]
REF_F[2]_A0
REF_F[2]_A1
REF_F[2]_A2
0x38: QREF_B0
0x39: QREF_B1
Reserved
REF_F[1:0]_B0
REF_F[1:0]_B1
MUX_B0
MUX_B1
REF_B0[2:0]
REF_B1[2:0]
REF_F[2]_B0
REF_F[2]_B1
0x48: QREF_C0
0x49: QREF_C1
Reserved
REF_F[1:0]_C0
REF_F[1:0]_C1
MUX_C0
MUX_C1
REF_C0[2:0]
REF_C1[2:0]
REF_F[2]_C0
REF_F[2]_C1
Reserved
REF_F[1:0]_D
MUX_D
REF_D[2:0]
REF_F[2]_D
0x58: QREF_D
0x2C: QREF_A0
0x2D: QREF_A1
0x2E: QREF_A2
0x3C: QREF_B0
0x3D: QREF_B1
0x4C: QREF_C0
0x4D: QREF_C1
0x5C: QREF_D
0x76
PD_A0
PD_A1
PD_A2
Reserved
nBIAS_A0
nBIAS_A1
nBIAS_A2
STYLE_A0
STYLE_A1
STYLE_A2
A_A0[1:0]
A_A1[1:0]
A_A2[1:0]
Reserved
PD_B0
PD_B1
Reserved
nBIAS_B0
nBIAS_B1
STYLE_B0
STYLE_B1
A_B0[1:0]
A_B1[1:0]
Reserved
PD_C0
PD_C1
Reserved
nBIAS_C0
nBIAS_C1
STYLE_C0
STYLE_C1
A_C0[1:0]
A_C1[1:0]
Reserved
PD_D
Reserved
nBIAS_D
STYLE_D
A_D[1:0]
Reserved
EN_QREF_A0 EN_QREF_A1 EN_QREF_A2 EN_QREF_B0 EN_QREF_B1 EN_QREF_C0 EN_QREF_C1 EN_QREF_D
[a] x = A, B, C, D, E;
y = A0, A1, A2, B0, B1, C0, C1, D, E0, E1;
r = A0, A1, A2, B0, B1, C0, C1, D.
©2017 Integrated Device Technology, Inc.
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8V19N490 Datasheet
Table 30. QREF Output State Register Descriptions[a]
Bit Field Location
Bit Field Name
Field Type
Default
(Binary)
MUX_r
R/W
1
REF_r[2:0]
R/W
000
Description
0 = QREF_r output signal source is the channel’s clock signal.
1 = QREF_r output signal source is the centrally generated SYSREF signal.
SYSREF Coarse Phase Delay:
REF_r[2:0]
Delay in ps = REF_r[2:0] 169ps (8 steps):
000 = 0ps
…
111 = 1.187ns
REF_F[2:0]_r
R/W
000
SYSREF Fine Phase Delay:
REF_F[2:0]_r
Insert a SYSREF fine phase delay in ps (8 steps) in addition to the delay value in:
REF_r[2:0]
000 = 0ps
001 = 25ps
010 = 50ps
011 = 75ps
100 = 85ps
101 = 110ps
110 = 135ps
111 = 160ps
nBIAS_r
R/W
0
QREF_r Output Bias Voltage:
0 = Output is not voltage biased.
1 = Output is biased to the LVDS cross-point voltage if BIAS_TYPE (register 0x19, bit 7)
is set to 1. Bit has no effect if BIAS_TYPE = 0.
Output bias = 1 requires AC coupling and LVDS style on the corresponding output.
©2017 Integrated Device Technology, Inc.
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July 26, 2017
8V19N490 Datasheet
Table 30. QREF Output State Register Descriptions[a] (Cont.)
Bit Field Location
Bit Field Name
Field Type
Default
(Binary)
A_r[1:0]
R/W
00
PD_r
R/W
0
Description
QREF_r Output Amplitude
Setting for STYLE_r = 0 (LVDS)
Setting for STYLE_r = 1 (LVPECL)
A[1:0] = 00: 250mV
A[1:0] = 01: 500mV
A[1:0] = 00: 250mV
A[1:0] = 01: 500mV
A[1:0] = 10: 750mV
A[1:0] = 11:1000mV
A[1:0] = 10: 750mV
A[1:0] = 11:1000mV
Termination: 100 across
Termination: 50 to VT
QREF_r Output Power-down:
0 = Output is powered-up.
1 = Output is powered-down. STYLE, EN and A[1:0] settings have no effect.
STYLE_r
R/W
0
QREF_r Output Format:
0 = Output is LVDS (requires an LVDS 100 output termination).
1 = Output is LVPECL (requires an LVPECL 50 output termination to the specified
recommended termination voltage).
EN_r
R/W
0
QREF_r Output Enable:
0 = Output is disabled at the logic low state.
1 = Output is enabled.
[a] x = A, B, C, D, E;
y = A0, A1, A2, B0, B1, C0, C1, D, E0, E1;
r = A0, A1, A2, B0, B1, C0, C1, D.
©2017 Integrated Device Technology, Inc.
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8V19N490 Datasheet
PLL Frequency Divider Registers
Table 31. PLL Frequency Divider Register Bit Field Locations
Bit Field Location
Register Address
D7
0x00
D6
D5
MV0[2:0]
D4
MV1[8]
Reserved
Reserved
PV[2:0]
Reserved
Reserved
BYPF
MV0[11:8]
Reserved
Reserved
Reserved
0x05
PV[11:8]
PV[7:0]
Reserved
Reserved
Reserved
Reserved
0x09
0x1F
D0
MV1[7:0]
0x04
0x0C
D1
MV0[7:0]
0x02
0x08
D2
PD_MV1
0x01
0x03
D3
Reserved
Reserved
Reserved
MF[8]
Reserved
VCO_SEL
MF[7:0]
FDF
Reserved
Reserved
Reserved
©2017 Integrated Device Technology, Inc.
PF[5:0]
Reserved
Reserved
41
Reserved
Reserved
July 26, 2017
8V19N490 Datasheet
Table 32. PLL Frequency Divider Register Descriptions
Bit Field Location
Bit Field Name
Field Type
Default
(Binary)
MV0[2:0]
R/W
000
Description
Phase of the MV0 feedback divider. Determines the PLL lock-detect phase window in
conjunction with PV[2:0]. Sampling clock phase is relative to the VCXO-PLL phase
detector clock edge. Set MV0[2:0] in relationship to MV0:
MV0 Divider Value
MV0[2:0] Setting
1–31
MV0[11:0]
R/W
1100
0000 0000
Value: ÷3072
MV1[8:0]
R/W
0 0110 0000
Value: ÷96
PD_MV1
R/W
0
Value:
MV1 enabled
PV[2:0]
PV[11:0]
R/W
R/W
000
1100
0000 0000
Value: ÷3072
©2017 Integrated Device Technology, Inc.
32–63
64–127
010
011
128–255
256–511
100
101
512–1023
1024+
110
111
VCXO-PLL Feedback-Divider:
The value of the frequency divider (binary coding).
Range: ÷1 to ÷4095
PLL Feedback-Divider:
The value of the frequency divider (binary coding).
Range: ÷4 to ÷511
PLL Feedback-Divider MV1 Power-down/Disabled:
0 = MV1 Divider is enabled.
1 = MV1 Divider is powered down and disabled.
Disabled MV1 to save power consumption in configurations not using the input clock
monitors.
Phase of the PV input (reference) divider. Determines the PLL lock-detect phase
window in conjunction with MV0[2:0]. Sampling clock phase is relative to the
VCXO-PLL phase detector clock edge. Set PV[2:0] in relationship to PV:
PV Divider Value
PV[2:0] Setting
1–31
32–63
010
64–127
128–255
011
100
256–511
512–1023
101
110
1024+
111
VCXO-PLL Input Frequency Pre-Divider:
The value of the frequency divider (binary coding).
Range: ÷1 to ÷4095
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8V19N490 Datasheet
Table 32. PLL Frequency Divider Register Descriptions (Cont.)
Bit Field Location
Bit Field Name
Field Type
Default
(Binary)
MF[8:0]
R/W
0 0001 1000
Value: ÷24
PF[5:0]
R/W
00 0000
Value:
Bypass
FDF
R/W
0
Value:
fVCXO ÷ PF
VCO_SEL
R/W
0
Value:
fVCO =
2949.12MHz
©2017 Integrated Device Technology, Inc.
Description
FemtoClock NG Pre-Divider:
The value of the frequency divider (binary coding).
Range: ÷8 to ÷511
FemtoClock NG Pre-Divider:
The value of the frequency divider (binary coding).
Range: ÷1 to ÷63
00 0000: PF is bypassed
Frequency Doubler:
The input frequency of the FemtoClock NG PLL (2nd stage) is:
0 = The output signal of the BYPV multiplexer, divided by the PF divider.
1 = The output signal of the BYPV multiplexer, doubled in frequency.
Use this setting to improve phase noise. The PF divider has no effect if FDF = 1.
VCO Select:
0 = Selects VCO at fVCO = 2949.12MHz.
1 = Do not use.
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8V19N490 Datasheet
VCXO-PLL Control Registers
Table 33. VCXO-PLL Control Register Bit Field Locations
Bit Field Location
Register Address
0x03
0x0A
0x10
0x11
0x12
D7
D6
D5
D4
D3
D2
D1
D0
MV1[8]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BYPF
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BYPV
POLV
FVCV
nPD_QOSC
STYLE_QOSC
Reserved
Reserved
CPV[4:0]
OSVEN
OFFSET[4:0]
A_QOSC[1:0]
CPF[4:0]
Table 34. VCXO-PLL Control Register Descriptions
Bit Field Location
Bit Field Name
Field Type
Default
(Binary)
BYPF
R/W
0
Description
PLL Feedback Bypass:
0 = VCXO-PLL feedback divider: MV0
1 = VCXO-PLL feedback divider: MV0 MV1
BYPV
R/W
0
VCXO-PLL Bypass:
0 = VCXO-PLL is enabled.
1 = VCXO-PLL is disabled and bypassed.
POLV
R/W
0
VCXO Polarity:
0 = Positive polarity. Use for an external VCXO with a positive f(VC) characteristics.
1 = Negative polarity. Use for an external VCXO with a negative f(VC) characteristics.
FVCV
R/W
1
VCXO-PLL Force VC Control Voltage:
0 = Normal operation.
1 = Forces the voltage at the LFV control pin (VCXO input) to VDD_V / 2. VCXO-PLL
unlocks and the VCXO is forced to its mid-point frequency. FVCV = 1 is the default
setting at startup to center the VCXO frequency. FVCV should be cleared after startup
to enable the PLL to lock to the reference frequency.
CPV[4:0]
R/W
1 1000
Value:
1.25mA
©2017 Integrated Device Technology, Inc.
VCXO-PLL Charge-Pump Current:
Controls the charge pump current ICPV of the VCXO-PLL. Charge pump current is the
binary value of this register plus one multiplied by 50µA.
ICPV = 50µA (CPV[4:0] + 1)
CPV[4:0] = 00000 sets ICPV to the minimum current of 50µA. Maximum charge pump
current is 1.6mA. Default setting is 1.25mA: ((24 + 1) 50µA).
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8V19N490 Datasheet
Table 34. VCXO-PLL Control Register Descriptions (Cont.)
Bit Field Location
Bit Field Name
Field Type
Default
(Binary)
nPD_QOSC
R/W
0
Description
QOSC Power State:
0 = Output QOSC is powered-down.
1 = Output QOSC is powered-up.
STYLE_QOSC
R/W
0
QOSC Output Format:
0 = Output is LVDS (requires an LVDS 100 output termination).
1 = Output is LVPECL (requires an LVPECL 50 output termination of to the specified
recommended termination voltage).
OSVEN
R/W
0
VCXO-PLL Offset Enable:
0 = No offset.
1 = Offset enabled. A static phase offset of OFFSET[4:0] is applied to the PFD of the
VCXO-PLL.
OFFSET[4:0]
R/W
0 0000
Value: 0
VCXO-PLL Static Phase Offset:
Controls the static phase detector offset of the VCXO-PLL. Phase offset is the binary
value of this register multiplied by 0.9 of the PFD input signal
(OFFSET [4:0] fPFD ÷ 400).
Maximum offset is 31 0.927.9
Setting OFFSET to 0.0 eliminates the thermal noise of an offset current. If the
VCXO-PLL input jitter period TJIT exceeds the average input period: set OFFSET to a
value larger than fPFD TJIT 400 to achieve a better charge pump linearity and
lower in-band noise of the PLL.
CPF[4:0]
R/W
1 1000
Value: 5.0mA
FemtoClock NG-PLL Charge-Pump Current:
Controls the charge pump current ICPF of the FemtoClock NG PLL. Charge pump
current is the binary value of this register plus one multiplied by 200µA.
ICPF = 200µA (CPF[4:0] + 1)
CPV[4:0] = 00000 sets ICPF to the minimum current of 200µA. Maximum charge pump
current is 6.4mA. Default setting is 5.0mA: ((24+1) 200µA).
A_QOSC[1:0]
R/W
00
Value: 250mV
©2017 Integrated Device Technology, Inc.
QOSC Output Amplitude
Setting for STYLE_r = 0 (LVDS)
Setting for STYLE_r = 1 (LVPECL)
A[1:0] = 00: 250mV
A[1:0] = 01: 500mV
A[1:0] = 00: 250mV
A[1:0] = 01: 500mV
A[1:0] = 10: 500mV
A[1:0] = 11: 750mV
A[1:0] = 10: 500mV
A[1:0] = 11: 750mV
Termination: 100 across
Termination: 50 to VT
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8V19N490 Datasheet
Input Selection Mode Registers
Table 35. Input Selection Mode Register Bit Field Locations
Bit Field Location
Register Address
0x14
0x15
D7
D6
PRIO_0[1:0]
Reserved
BLOCK_LOR
D5
D4
PRIO_1[1:0]
DIV4_VAL
REVS
0x16
0x17
D3
D2
D1
D0
PRIO_2[1:0]
PRIO_3[1:0]
nM/A[1:0]
SEL[1:0]
CNTH[7:0]
CNTR[1:0]
©2017 Integrated Device Technology, Inc.
PD_CLK3
PD_CLK2
46
PD_CLK1
PD_CLK0
CNTV[1:0]
July 26, 2017
8V19N490 Datasheet
Table 36. Input Selection Mode Register Descriptions
Bit Field Location
Bit Field Name
Field Type
PRIO_n[1:0]
R/W
Default
(Binary)
Description
CLK_0: 11
CLK_1: 10
CLK_2: 01
CLK_3: 00
Controls the auto-selection priority of the clock input CLK_n (n = 0…3). If multiple
inputs have equal priority, the order within that priority is from CLK0 (highest) to CLK3
(lowest):
00 = Priority 0 (lowest)
01 = Priority 1
10 = Priority 2
11 = Priority 3 (highest)
DIV4_VAL
R/W
0
Value: ÷1
REVS
R/W
0
Value: off
Pre-divider for CNTV[1:0]. Use the ÷4 pre-divider for input frequencies >250MHz:
0 = ÷1
1 = ÷4
Revertive Switching:
The revertive input switching setting is only applicable to the two automatic selection
modes shown in Table 10. If nM/A[1:0] = X0, the REVS setting has no meaning.
0 = Disabled: Re-validation of a non-selected input clock has no impact on the clock
selection.
1 = Enabled: Re-validation of any non-selected input clock(s) will cause a new input
selection according to the pre-set input priorities (revertive switch). An input switch is
only done if the re-validated input has a higher priority than the current VCXO-PLL
reference clock.
Default setting is revertive switching turned off.
nM/A[1:0]
R/W
00
Value:
Manual
Selection
Reference Input Selection Mode:
In any of the manual selection modes (nM/A[1:0] = 00 or 10), the VCXO-PLL reference
input is selected by SEL[1:0]. In any of the automatic selection modes, the VCXO-PLL
reference input is selected by an internal state machine according to the input LOS
states and the priorities in the input priority registers.
00 = Manual selection
01 = Automatic selection (no holdover)
10 = Short-term holdover
11 = Automatic selection with holdover
SEL[1:0]
R/W
00
Value:
CLK0
selected
VCXO-PLL Input Reference Selection:
Controls the selection of the VCXO-PLL reference input in the manual selection modes.
In automatic selection modes (nM/A[1:0] = X1), SEL[1:0] has no meaning.
00 = CLK_0
01 = CLK_1
10 = CLK_2
11 = CLK_3
©2017 Integrated Device Technology, Inc.
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8V19N490 Datasheet
Table 36. Input Selection Mode Register Descriptions (Cont.)
Bit Field Location
Bit Field Name
Field Type
Default
(Binary)
CNTH[7:0]
R/W
1000 0000
Value:
136ms
Description
nMA[1:0] = 11 Automatic with holdover: Hold-off counter period. The device initiates a
clock fail-over switch upon counter expiration (zero transition). The counters start to
counts backwards after an LOS event is detected. The hold-off counter period is
determined by the binary number of VCXO-PLL output pulses divided by CNTR[1:0].
With a VCXO frequency of 122.88MHz and CNTR[1:0] = 10, the counter has a period of
(1.066 ms binary setting). After each zero-transition, the counter automatically
re-loads to the setting in this register. The default setting is 136ms (VCXO =
122.88MHz: 1/122.88MHz 217 128).
CNTR[1:0]
R/W
10
Value: 217
nMA[1:0] = 11 Automatic with Holdover: Reference Divider
CNTR[1:0]
122.88MHz VCXO
38.4MHz VCXO
—
1171Hz (0.853ms; 0–217.6ms)
01 = fVCXO ÷216
1875Hz (0.533ms; 0–136ms)
—
÷217
937.5Hz (1.066ms; 0–272ms)
—
00 = fVCXO
10 = fVCXO
CNTV[1:0]
R/W
10
Value: 32
PD_CLK_3
PD_CLK_2
PD_CLK_1
PD_CLK_0
R/W
BLOCK_LOR
R/W
0
Powered-up/
Enabled
0
Value:
Not blocked
CNTH frequency (period; range)
÷215
Controls the number of required consecutive, valid input reference pulses for clock
re-validation on CLK_n (n = 0…3), in number of input periods. At an LOS event, the
re-validation counter loads this setting from the register and counts down by one with
every valid, consecutive input signal period. Missing input edges (for one input period)
will cause this counter to re-load its setting. An input is re-validated when the counter
transitions to zero and the corresponding LOS flag is reset.
DIV4_VAL = 0
DIV4_VAL = 1
00 = 2 (shortest possible)
01 = 16
00 = 8 (shortest possible)
01 = 64
10 = 32
11 = 64
10 = 128
11 = 256
Input CLK_n Power-down/ Disable:
0 = Input CLK_n is enabled.
1 = Input CLK_n is powered-down and disabled.
Disable individual Input CLK_n input to save power consumption in configurations not
using the respective input and in manual switching or short-term holdover mode.
Enable inputs CLK_n in configurations with automatic switching.
Block Loss-of-reference (input activity) Indicator:
VCXO-PLL Loss-of-lock signals nST_LOLV and nLS_LOLV are triggered by:
0 = VCXO-PLL Loss-of-lock or by inactivity of the selected reference clock.
1 = Only VCXO-PLL loss-of-lock.
BLOCK_LOR = 1 will also block loss-of-reference from triggering a failure on the LOCK
output pin.
©2017 Integrated Device Technology, Inc.
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8V19N490 Datasheet
SYSREF Control Registers
Table 37. SYSREF Control Register Bit Field Locations
Bit Field Location
Register Address
0x18
0x19
D7
D6
D5
D4
PD_S
NS[6:0]
BIAS_TYPE
SYNC[6:0]
0x1A
0x70
D2
D1
D0
SRPC[7:0]
0x1B
0x1C
D3
REF_S[7:0]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SRG
SRO
RS
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 38. SYSREF Control Register Descriptions
Bit Field Location
Bit Field Name
Field Type
Default
(Binary)
PD_S
R/W
0
Description
SYSREF Global Power-down (including. global delay S, SYSREF frequency divider
NS):
0 = SYSREF functional blocks are powered-up.
1 = SYSREF functional blocks are powered-down.
NS[6:0]
R/W
010 11 11
Value:
÷1280
SYSREF Frequency Divider:
The value of the frequency divider is set by the product of:
NS[6] NS[5:4] NS[3:2] NS[1:0].
NS[6]
NS[5:4]
NS[3:2]
NS[1:0]
0 = ÷2
1 = ÷4
00 = ÷2
01 = ÷4
00 = ÷2
01 = ÷4
00 = ÷2
01 = ÷3
10 = ÷8
11 = ÷16
10 = ÷8
11 = ÷16
10 = ÷4
11 = ÷5
The SYSREF contains four serial dividers that can be individually controlled by NS[6],
NS[5:4], NS[3:2] and NS[1:0], respectively. The total NS divider is the product of the four
serial dividers. Example: to achieve a SYSREF divider value of ÷384 = {2} {4} {16}
{3}, set NS[6] = 0, NS[5:4] = 01, NS[3:2] = 11 and NS[1:0] = 01.
If a given output divider can be achieved by multiple NS[6:0] settings, use the highest
possible divider in NS[1:0], then in NS[3:2], followed by NS[5:4] = 11 and then NS[6].
©2017 Integrated Device Technology, Inc.
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8V19N490 Datasheet
Table 38. SYSREF Control Register Descriptions (Cont.)
Bit Field Location
Bit Field Name
Field Type
Default
(Binary)
BIAS_TYPE
R/W
1
SYSREF Output Voltage Bias:
0 = QREF_r outputs are in a low/high state when nBIAS_r is set to 1 or during a SYSREF
event.
1 = QREF_r outputs are in a cross-point biased state when nBIAS_r is set to 1 or during
a SYSREF event.
SYNC[6:0]
R/W
00 00 001
SYSREF Synchronizer divider value. This divider controls the release of SYSREF pulses
at coincident QCLK clock edges. For SYSREF operation, set this divider value to the
least common multiple of the clock divider values Nx (x = A to E).
For instance, if NA = NB = ÷2, NC = ND = ÷3, NE = ÷4 set the SYNC divider to ÷12.
Description
SYNC6 Description:
0: SYNC[6] = 0: output frequency divider set by SYNC[2:0].
1: SYNC[6] = 1: output frequency divider set by the product of SYNC[5:3] SYNC[2:0].
SYNC[5:3]
SYNC[2:0]
000 = ÷2
001 = ÷4
000 = ÷2
001 = ÷3
010 = ÷6
010 = ÷4
011 = ÷8
100 = ÷4
011 = ÷5
100 = ÷6
101 = ÷8
110 = ÷12
101 = ÷7
110 = ÷8
111 = ÷16
111 = ÷9
The frequency divider SYNC is composed of 2 serial dividers that can be individually
controlled by the bit fields SYNC[5:3] and SYNC[2:0].
Set SYNC[6] = 0 to achieve an output divider in the range of {2, 3, 4, 5, 6, 7, 8, 9}.
Set SYNC[6] = 1 to achieve an output divider value of {2, 4, 6, 8, 12,16} {2, 3, 4, 5, 6,
7, 8, 9}.
For instance, the output divider of ÷32 = {4} {8} is set by SYNC[6:0] = 1001110.
If a given output divider can be achieved by multiple SYNC[6:0] settings, a setting with
SYNC[6] = 0 is preferred. If SNYC[6] = 1, the higher divider value should be configured
with SYNC[2:0].
SRPC[7:0]
R/W
0000 0010
Value: 2
©2017 Integrated Device Technology, Inc.
SYSREF Pulse Count:
Binary value of the number of SYSREF pulses generated and output at all enabled
QREF outputs.
Allows the generation of 1 to 255 pulses after each write access.
Requires setting SRG = 0, and SRO = 0.
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8V19N490 Datasheet
Table 38. SYSREF Control Register Descriptions (Cont.)
Bit Field Location
Bit Field Name
Field Type
Default
(Binary)
REF_S[7:0]
R/W
0000 0000
Description
REF_S global SYSREF phase delay. This setting affects all QREF_r outputs
configured as SYSREF:
REF_S[7:0]
Delay in ps = REF_S 339ps (256 steps):
0000 0000 = 0ps
…
1111 1111 = 86.466ns
SRG
R/W
0
SYSREF Pulse Generation:
0 = Internal SPI controlled SYSREF generation triggered by the RS bit.
1 = External controlled SYSREF generation using the EXT_SYS pin.
SRO
R/W
0
SYSREF Pulse Mode:
0 = Counted SYSREF pulse generation mode.
Number of pulses is controlled by SRPC[7:0].
1 = Continuous SYSREF pulse generation.
RS
W only
Auto-Clear
X
Set RS = 1 to initiate the SYSREF pulse generation of SRPC-number of pulses. Powers
up the SYSREF circuitry and releases the SYSREF pulse(s) as configured. RS = 1 also
phase-aligns the QREF outputs to the QCLK outputs and adds the programmed delay
values into the QREF paths. RS auto-clears in SYSREF counted pulse mode
(if SRO = 0):
SRG = 0 (internal generation): Each setting of RS initiates SYSREF pulse(s).
SRG = 1 (external generation): Set RS = 1 to prepare SYSREF generation triggered by a
rising edge at the EXT_SYS pin.
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8V19N490 Datasheet
Status Registers
Table 39. Status Register Bit Field Locations
Bit Field Location
Register Address
0x68
0x69
0x6C
0x6D
0x6E
0x6F
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
Reserved
IE_LOLF
IE_LOLV
IE_CLK_3
IE_CLK_2
IE_CLK_1
IE_CLK_0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IE_REF
IE_HOLD
Reserved
Reserved
nLS_LOLF
nLS_LOLV
LS_CLK_3
LS_CLK_2
LS_CLK_1
LS_CLK_0
nST_LOLF
nST_LOLV
ST_CLK_3
ST_CLK_2
ST_CLK_1
ST_CLK_0
ST_SEL[1:0]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
LS_REF
nLS_HOLD
Reserved
Reserved
Reserved
Reserved
Reserved
ST_VCOF
ST_REF
nST_HOLD
Table 40. Status Register Descriptions[a]
Bit Field Location
Bit Field Name
Field Type
Default
(Binary)
IE_LOLF
R/W
0
Description
Interrupt Enable for FemtoClock NG-PLL Loss-of-lock:
0 = Disabled: Setting nLS_LOLF will not cause an interrupt on nINT
1 = Enabled: Setting nLS_LOLF will assert the nINT output (nINT = 0, interrupt)
IE_LOLV
R/W
0
Interrupt Enable for VCXO-PLL Loss-of-lock:
0 = Disabled: Setting nLS_LOLV will not cause an interrupt on nINT.
1 = Enabled: Setting nLS_LOLV will assert the nINT output (nINT = 0, interrupt).
IE_CLK_n
R/W
0
Interrupt Enable for CLKn input Loss-of-signal:
0 = Disabled: Setting LS_CLK_n will not cause an interrupt on nINT.
1 = Enabled: Setting LS_CLK_n will assert the nINT output (nINT = 0, interrupt).
IE_REF
R/W
0
Interrupt Enable for LS_REF:
0 = Disabled: any changes to LS_REF will not cause an interrupt on nINT.
1 = Enabled: any changes to LS_REF will assert the nINT output (nINT = 0, interrupt).
IE_HOLD
R/W
0
Interrupt Enable for Holdover:
0 = Disabled: Setting nLS_HOLD will not cause an interrupt on nINT.
1 = Enabled: Setting nLS_HOLD will assert the nINT output (nINT = 0, interrupt).
nLS_LOLF
R/W
—
FemtoClock NG-PLL Loss-of-lock (latched status of nST_LOLF):
Read 0 = 1 Loss-of-lock events detected after the last nLS_LOLF status latch clear.
Read 1 = No Loss-of-lock detected after the last nLS_LOLF status latch clear.
Write 1 = Clear status latch (clears pending nLS_LOLF interrupt).
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8V19N490 Datasheet
Table 40. Status Register Descriptions[a] (Cont.)
Bit Field Location
Bit Field Name
Field Type
Default
(Binary)
nLS_LOLV
R/W
—
Description
VCXO-PLL Loss-of-lock (latched status of nST_LOLV):
Read 0 = 1 Loss-of-lock events detected after the last nLS_LOLV status latch clear.
Read 1 = No Loss-of-lock detected after the last nLS_LOLF status latch clear.
Write 1 = Clear status latch (clears pending nLS_LOLV interrupt).
LS_CLK_n
R/W
—
Input CLK_n Status (latched status of ST_CLK_n):
Read 0 = 1 LOS events detected on CLK_n after the last LS_CLK_n status latch clear.
Read 1 = No Loss-of-signal detected on CLK_n input after the last LS_CLK_n status
latch clear.
Write 1 = Clear LS_CLK_n status latch (clears pending LS_CLK_n interrupts on nINT).
ST_SEL[1:0]
R
—
Input Selection (momentary):
Reference Input Selection Status of the state machine. In any input selection mode,
reflects the input selected by the state machine:
00 = CLK_0
01 = CLK_1
10 = CLK_2
11 = CLK_3
nST_LOLF
R
—
FemtoClock NG-PLL Loss-of-lock (momentary):
Read 0 = Loss-of-lock event detected.
Read 1 = No Loss-of-lock detected.
A latched version of this status bit is available (nLS_LOLF).
nST_LOLV
R
—
VCXO-PLL Loss-of-lock (momentary):
Read 0 = Loss-of-lock event detected.
Read 1 = No Loss-of-lock detected.
A latched version of this status bit is available (nLS_LOLV).
ST_CLK_n
R
—
Input CLK_n Status (momentary):
0 = LOS detected on CLK_n.
1 = No LOS detected, CLK_n input is active.
Latched versions of these status bits are available (LS_CLK_n).
LS_REF
R/W
—
PLL Reference Status (latched status of ST_REF):
Read 0 = Reference is lost after the last LS_REF status latch clear.
Read 1 = Reference is valid after the last LS_REF status latch clear.
Write 1 = Clear LS_REF status latch (clears pending LS_REF interrupts on nINT).
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8V19N490 Datasheet
Table 40. Status Register Descriptions[a] (Cont.)
Bit Field Location
Bit Field Name
Field Type
Default
(Binary)
nLS_HOLD
R/W
—
Description
Holdover Status Indicator (latched status of nST_HOLD):
Read 0 = VCXO-PLL has entered holdover state at least 1 time after the last
nLS_HOLD status latch clear.
Read 1 = VCXO-PLL is (or attempts to) lock(ed) to an input clock.
Write 1 = Clear status latch (clears pending nLS_HOLD interrupt).
ST_VCOF
R
—
FemtoClock NG-PLL Calibration Status (momentary):
Read 0 = FemtoClock NG PLL auto-calibration is completed.
Read 1 = FemtoClock NG PLL calibration is active (not completed).
ST_REF
R
—
Input Reference Status:
0 = No input reference present.
1 = Input reference is present.
nST_HOLD
R
—
Holdover Status Indicator (momentary):
0 = VCXO-PLL in holdover state, not locked to any input clock.
1 = VCXO-PLL is (or attempts to) lock(ed) to input clock.
A latched version of this status bit is available (nLS_HOLD).
[a] CLKn = CLK0, CLK1, CLK2, CLK3.
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8V19N490 Datasheet
General Control Registers
Table 41. General Control Register Bit Field Locations
Bit Field Location
Register Address
0x71
0x72
0x73
D7
D6
D5
D4
D3
D2
D1
D0
INIT_CLK
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RELOCK
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PB_CAL
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CPOL
Table 42. General Control Register Descriptions
Bit Field Location
Default
(Binary)
Bit Field Name
Field Type
Description
INIT_CLK
W only
Auto-Clear
X
Set INIT_CLK = 1 to initialize divider functions. Required as part of the startup
procedure.
RELOCK
W only
Auto-Clear
X
Setting this bit to 1 will force the FemtoClock NG PLL to re-lock.
PB_CAL
W only
Auto-Clear
X
Precision Bias Calibration:
Setting this bit to 1 will start the calibration of an internal precision bias current source.
The bias current is used as a reference for outputs configured as LVDS and as a
reference for the charge pump currents. This bit will auto-clear after the calibration is
completed. Set as part of the startup procedure.
CPOL
R/W
0
SPI Read Operation SCLK Polarity:
0 = Data bits on SDAT are output at the falling edge of SCLK edge.
1 = Data bits on SDAT are output at the rising edge of SCLK edge.
©2017 Integrated Device Technology, Inc.
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8V19N490 Datasheet
Electrical Characteristics
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device.
Functional operation of the 8V19N490 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Table 43. Absolute Maximum Ratings
Item
Rating
Supply Voltage, VDD_V
3.6V
Inputs
-0.5V to VDD_V +0.5V
Outputs, VO (LVCMOS)
-0.5V to VDD_V +0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Outputs, IO (LVDS)
Continuous Current
Surge Current
50mA
100mA
Input Termination Current, IVT
±35mA
Operating Junction Temperature, TJ
125C
Storage Temperature, TSTG
-65C to 150C
ESD - Human Body Model[a]
ESD - Charged Device Model
2000V
[a]
500V
[a] According to JEDEC JS-001-2012/JESD22-C101.
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8V19N490 Datasheet
Input Characteristics
Table 44. Input Characteristics, VDD_V = 3.3V ±5%, TA = -40°C to +85°C
Symbol
CIN[a]
Parameter
Input Capacitance
Test Conditions
Minimum
Typical
Maximum
Units
OSC, nOSC
2
4
pF
Other inputs
2
4
pF
RPU
Input
Pull-up Resistor
nOSC,
SDAT, nCS,
nCLK_[0:3]
51
k
RPD
Input
Pull-down Resistor
EXT_SYS,
CLK_[0:3],
nCLK_[0:3],
OSC, nOSC,
SCLK, SELSV
51
k
ROUT
LVCMOS
Output Impedance
nINT, LOCK
25
[a] Guaranteed by design.
DC Characteristics
Table 45. Power Supply DC Characteristics, VDD_V = 3.3V ±5%, TA = -40°C to +85°C
Symbol
Parameter
VDD_V
Core Supply Voltage
IDD_V
Total Power Supply Current
©2017 Integrated Device Technology, Inc.
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
1395
57
mA
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8V19N490 Datasheet
Table 46. Typical Power Supply DC Current Characteristics, VDD_V = 3.3V ±5%, TA = -40°C to +85°C[a]
Test Case
Symbol
—
—
Supply Pin Current
QCLK_y
QREF_r
1
2
3
4
5
6
Unit
Style
LVPECL
LVPECL
LVPECL
LVPECL
LVDS
LVDS
—
State
On
On
On
On
On
On
—
Amplitude
500
750
1000
250
500
750
mV
Style
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
—
State
On
On
Off
On
Off
Off
—
Amplitude
500
500
—
250
—
—
mV
IDD_CA
Current through VDD_QCLKA pin
101.1
115.7
135.5
86.6
78.6
102.2
mA
IDD_CB
Current through VDD_QCLKB pin
81.7
93.2
96.6
70.6
58.0
73.0
mA
IDD_CC
Current through VDD_QCLKC pin
82.2
93.3
101.4
71.1
58.3
73.5
mA
IDD_CD
Current through VDD_QCLKD pin
51.1
56.7
61.4
45.5
38.0
46.8
mA
IDD_CE
Current through VDD_QCLKE pin
70.5
79.4
88.7
61.4
59.4
75.3
mA
IDD_RA
Current through VDD_QREFA pin
77.3
77.1
2.3
55.7
2.3
2.3
mA
IDD_RB
Current through VDD_QREFB pin
51.2
51.3
1.5
36.9
1.5
1.6
mA
IDD_RC
Current through VDD_QREFC pin
51.3
51.3
1.6
36.9
1.6
1.6
mA
IDD_RD
Current through VDD_QREFD pin
26.1
25.9
0.8
18.7
0.8
0.8
mA
IDD_INP
Current through VDD_INP pin
80.5
81.0
81.8
80.1
82.6
83.3
mA
IDD_SPI
Current through VDD_SPI pin
6.0
6.5
6.4
4.4
5.9
6.0
mA
IDD_OSC
Current through VDD_OSC and
VDD_CP pins
38.7
38.8
38.9
38.6
39.3
39.0
mA
IDD_SYNC
Current through VDD_SYNC pin
82.6
82.6
1.9
82.8
1.9
1.9
mA
IDD_CPF
Current through VDD_CPF pin
59.4
59.5
59.4
59.4
59.4
60.2
mA
IDD_LCV
Current through VDD_LCV pin
72.3
72.3
72.2
72.3
74.4
76.9
mA
IDD_LCF
Current through VDD_LCF pin
52.2
52.0
52.5
52.5
52.4
52.4
mA
2.76
2.87
2.06
2.46
2.03
2.3
W
3.25
3.43
2.65
2.89
2.03
2.30
W
PTOT
PTOT, SYS
Total Device Power Consumption
Total System Power Consumption
[b]
[a] Configuration: fCLK (input) = 122.88MHz, fSYSREF=7.68MHz, internal SYSREF generation (continuous), QA[2:0] = 1474.56MHz, QB[1:0] = 245.76MHz,
QC[1:0] = 245.76MHz, QD = 491.52MHz, QE[1:0] = 122.88MHz). QCLK_y outputs terminated according to amplitude settings. QREF_r outputs
unterminated when SYSREF is turned off.
[b] Includes total device power consumption and the power dissipated in external output termination components.
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8V19N490 Datasheet
Table 47. LVCMOS DC Characteristics, VDD_V = 3.3V ±5%, TA = -40°C to +85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Control Input SELSV (3.3V logic)
VIH
Input High Voltage
2.0
VDD_V
V
VIL
Input Low Voltage
-0.3
0.8
V
IIH
Input
High Current
150
µA
IIL
Input
Low Current
VDD_V = 3.3V, VIN = 3.3V
Input with
pull-down resistor
VDD_V = 3.3V, VIN = 0V
-5
µA
SYSREF Trigger Input EXT_SYS (1.8V/3.3V selectable logic)
VIH
VIL
IIH
IIL
Input High Voltage
Input Low Voltage
Input
High Current
Input
Low Current
Input with
pull-down resistor
1.8V logic (SELSV = 0)
1.17
VDD_V
V
3.3V logic (SELSV = 1)
2.0
VDD_V
V
1.8V logic (SELSV = 0)
-0.3
0.63
V
3.3V logic (SELSV = 1)
-0.3
0.8
V
150
µA
VDD_V = 3.3V, VIN = 1.8V or
3.3V
VDD_V = 3.3V, VIN = 0V
-5
µA
SPI Inputs SDAT (when input), SCLK, nCS (1.8V/3.3V selectable logic with input hysteresis)
VI
VT+
VTVH
Input Voltage
Positive-going Input Threshold Voltage
Negative-going Input Threshold Voltage
Hysteresis Voltage
1.8V logic (SELSV = 0)
-0.3
VDD_V
V
0.660
1.350
V
3.3V logic (SELSV = 1)
1.8V logic (SELSV = 0)
1.8–2.1
0.495
3.3V logic (SELSV = 1)
V T+ – VT-
V
1.170
0.75–0.97
0.165
V
V
0.780
V
SPI output DAT (when output), nINT, LOCK (1.8V/3.3V selectable logic)
VOH
Output High Voltage
1.8V logic (SELSV = 0)
1.35
V
2.4
V
IOH = -4mA
3.3V logic (SELSV = 1)
IOH = -4mA
VOL
Output Low Voltage
1.8V logic (SELSV = 0)
0.45
V
0.4
V
IOL = 4mA
3.3V logic (SELSV = 1)
IOL = 4mA
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8V19N490 Datasheet
Table 48. Differential Input DC Characteristics, VDD_V = 3.3V ±5%, TA = -40°C to +85°C
Symbol
IIH
Parameter
Input
High Current
Test Conditions
Inputs with pull-down
resistor[a]
Minimum
Typical
Maximum
Units
150
µA
150
µA
VDD_V = VIN = 3.465V
Pull-down/pull-up
inputs[b]
IIL
Input
Low Current
Inputs with
pull-down resistor
VDD_V = 3.465V, VIN = 0V
Pull-down/pull-up
inputs[b]
-150
µA
-150
µA
[a] Non-Inverting inputs: CLK_n, OSC.
[b] Inverting inputs: nCLK_n, nOSC.
Table 49. LVPECL DC Characteristics (QCLK_y, QREF_r, STYLE = 1), VDD_V = 3.3V ±5%, TA = -40°C to +85°C
Symbol
VOH
VOL
Parameter
Output High Voltage[a]
Output Low Voltage
Test Conditions
Minimum
Typical
Maximum
Units
250mV amplitude setting
VDD_V – 0.975
VDD_V – 0.875
VDD_V – 0.774
V
500mV amplitude setting
VDD_V – 1.000
VDD_V – 0.904
VDD_V – 0.805
V
750mV amplitude setting
VDD_V – 1.100
VDD_V – 0.937
VDD_V – 0.829
V
1000mV amplitude setting
VDD_V – 1.100
VDD_V – 0.962
VDD_V – 0.861
V
250mV amplitude setting
VDD_V – 1.250
VDD_V – 1.150
VDD_V – 1.040
V
500mV amplitude setting
VDD_V – 1.540
VDD_V – 1.420
VDD_V – 1.131
V
750mV amplitude setting
VDD_V – 1.810
VDD_V – 1.690
VDD_V – 1.580
V
1000mV amplitude setting
VDD_V – 2.090
VDD_V – 1.960
VDD_V – 1.840
V
[a] Outputs terminated with 50 to VDD_V – 1.5V (250mV amplitude setting), VDD_V – 1.75V (500mV amplitude setting), VDD_V – 2.0V (750mV amplitude
setting), VDD_V – 2.25V (1000mV amplitude setting).
Table 50. LVDS DC Characteristics (QCLK_y, QREF_r, STYLE = 0), VDD_V = 3.3V ±5%, TA = -40°C to +85°C
Symbol
VOS
VOS
Parameter
Offset Voltage[a]
Test Conditions
Minimum
Typical
Maximum
Units
250mV amplitude setting
2.10
2.40
2.70
V
500mV amplitude setting
1.90
2.23
2.60
V
750mV amplitude setting
1.80
2.08
2.4
V
1000mV amplitude setting
1.60
1.93
2.20
V
80
mV
VOS Magnitude Change
[a] VOS changes with VDD_V.
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AC Characteristics
Table 51. AC Characteristics, VDD_V = 3.3V ±5%, TA = -40°C to +85°C[a]
Symbol
Parameter
fVCO
VCO Frequency
fOUT
Output
Frequency
Test Conditions
Input
Frequency
fVCXO
VCXO Frequency
fp
frms
Minimum
Typical
Maximum
Units
2920
2949.12
3000
MHz
QCLK_y, QREF_r
(lock)
N = ÷1
2949.12
MHz
QCLK_y, QREF_r
(lock)
N = ÷2
1474.56
MHz
QCLK_y, QREF_r
(clock)
N = ÷3
983.04
MHz
QCLK_y, QREF_r
(clock)
N = ÷6
491.52
MHz
QCLK_y, QREF_r
(clock)
N = ÷12
245.76
MHz
QCLK_y, QREF_r
(clock)
N = ÷24
122.88
MHz
QREF_r (SYSREF)
fCLK
[b]
0.576
CLK_n
Static Frequency Error
Dynamic Frequency Error
RMS[d]
1.92[c]
245.76
30.72
122.88
30.72
MHz
2000
MHz
MHz
fCLK = 0ppb frequency deviation
0
ppb
fCLK = 0ppb frequency deviation
0.5
ppb
VIN
Input Voltage
Amplitude[e]
CLK_n, OSC/nOSC
0.15
1.2
V
VDIFF_IN
Differential
Input Voltage
Amplitude[e], [f]
CLK_n, OSC/nOSC
0.3
2.4
V
1.0
VDD_V – (VIN / 2)
V
55
%
VCMR
odc
tR / tF
Common Mode Input Voltage
Output Duty Cycle
Output
Rise/Fall Time,
Differential
Output
Rise/Fall Time
QCLK_y, QREF_r (clock)
45
50
LVPECL
QCLK_y, QREF_r
20% to 80%
250
ps
LVDS
QCLK_y, QREF_r
20% to 80%
250
ps
SYSREF, LVDS
QREF_r
20% to 80%
250
ps
LVCMOS outputs
20% – 80%
1
ns
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Table 51. AC Characteristics, VDD_V = 3.3V ±5%, TA = -40°C to +85°C[a]
Symbol
VO(PP)[g]
Parameter
LVPECL Output
Voltage Swing,
Peak-to-peak;
(see Table 54)
LVPECL
Differential
Output Voltage
Swing,
Peak-to-peak;
1474.56MHz;
(see Table 54)
Test Conditions
VOD
LVDS Output
Voltage Swing,
Peak-to-peak;
1474.56MHz;
(see Table 54)
LVDS
Differential
Output Voltage
Swing,
Peak-to-peak;
1474.56MHz;
(see Table 54)
Minimum
Typical
Maximum
Units
1474.56MHz
491.52MHz
190
211
272
265
367
327
mV
500mV amplitude
1474.56MHz
505
499
634
581
mV
491.52MHz
394
422
750mV amplitude
1474.56MHz
491.52MHz
598
629
733
734
875
841
mV
1000mV amplitude
1474.56MHz
946
970
1090
1110
mV
491.52MHz
784
837
250mV amplitude
1474.56MHz
491.52MHz
380
422
544
530
734
654
mV
500mV amplitude
1474.56MHz
1010
998
1268
1162
mV
491.52MHz
788
844
750mV amplitude
1474.56MHz
491.52MHz
1196
1258
1466
1468
1750
1682
mV
1000mV amplitude
1474.56MHz
1586
1674
1892
1940
2180
2220
mV
193
219
273
290
mV
491.52MHz
128
162
500mV amplitude
1474.56MHz
491.52MHz
312
385
404
456
512
536
mV
750mV amplitude
1474.56MHz
615
697
757
795
mV
491.52MHz
490
605
1000mV amplitude
1474.56MHz
491.52MHz
676
827
822
938
992
1060
mV
250mV amplitude
1474.56MHz
386
438
546
580
mV
491.52MHz
256
324
500mV amplitude
1474.56MHz
491.52MHz
624
770
808
912
1024
1072
mV
750mV amplitude
1474.56MHz
1230
1394
1514
1590
mV
491.52MHz
980
1210
1474.56MHz
491.52MHz
1352
1654
1644
1876
1984
2120
mV
+200
ps
250mV amplitude
1000mV amplitude
tPD
(Cont.)
250mV amplitude
491.52MHz
[h]
[b]
1474.56MHz
-200
Propagation Delay Variation between
Reference Input and any QCLK_y
Output
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Table 51. AC Characteristics, VDD_V = 3.3V ±5%, TA = -40°C to +85°C[a]
Symbol
tsk(o)
Parameter
Output Skew;
NOTE[i], [j], [k]
Test Conditions
[b]
(Cont.)
Minimum
Typical
Same N divider
100
ps
QCLK_y
Any N divider, incident rising
edge
100
ps
100
ps
100
150
ps
QREF_r (SYSREF)
Units
QCLK_y
QREF_r (clock)
Maximum
QREF_r (clock) to
QCLK_y
Any divider,
incident rising QCLK edge
100
150
ps
QREF_r (SYSREF)
to QCLK_y
Any divider,
incident rising QCLK edge
100
150
ps
fOUT = 983.04MHz
75
dB
Output Isolation between any
Neighboring Clock Output
fOUT = 491.52MHz
65
75
dB
fOUT = 245.76MHz
70
80
dB
50
75
dB
Output Isolation between any
Both SYSREF and clock signals
QCLK_y, QREF_r (SYSREF[l]) Output active
tD, LOS
LOS State Detected (measured in
input reference periods)
fCLK = 122.88MHz
fCLK = 245.76MHz
tD, LOCK
PLL Lock Detect
tD, RES
fHOLD
2
3
TIN
TIN
PLL re-lock time after a
short-term holdover scenario.
Measured from LOS to both
PLLs lock-detect asserted;
hold-off timer = 200
(CNTR = 217,
fVCXO = 122.88MHz,
fIN = 245.76MHz or
122.88MHz), VCXO-PLL
bandwidth = 100Hz,
initial frequency error 500Hz
-60
-56
dBc
15.36MHz
>500Hz
-60
-56
dBc
7.68MHz
>500Hz
-60
-56
dBc
[a] Phase noise is measured as additive phase noise contribution by the device on all SYSREF outputs, dividers and channel logic. SYSREF signals
measured as continued clock signal. Clock signals (QCLK) are turned on.
[b] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a
test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equilibrium has been reached
under these conditions.
[c] Measured as sum of all spurious amplitudes in one side band in the offset frequency range above 500Hz, excluding the harmonics of the fundamental
frequency of n fSYSREF (e.g. n 7.68MHz).
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Table 54. 8V19N490AC Characteristics: Typical QCLK_y Output Amplitude, VDD_V = 3.3V, TA = 85°C[a]
QCLK_y Output Frequency in MHz
Symbol
Parameter
VO(PP)[b] LVPECL
Output Voltage
Swing,
Peak-to-peak
VOD[c]
LVDS Output
Voltage Swing,
Peak-to-peak
Test Conditions
2949.12
1474.56
983.04
737.28
491.52
245.76
Units
250mV amplitude setting
214
283
260
262
264
281
mV
500mV amplitude setting
376
520
492
484
508
520
mV
750mV amplitude setting
512
748
740
716
730
768
mV
1000mV amplitude
setting
628
960
984
944
968
1008
mV
250mV amplitude setting
120
190
200
210
215
225
mV
500mV amplitude setting
250
390
410
430
440
470
mV
750mV amplitude setting
370
592
650
670
682
710
mV
1000mV amplitude
setting
475
790
870
900
920
980
mV
[a] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a
test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equilibrium has been reached
under these conditions.
[b] LVPECL outputs terminated with 50 to VDD_V – 1.5V (250mV amplitude setting), VDD_V – 1.75V (500mV amplitude setting),
VDD_V – 2.0V (750mV amplitude setting), VDD_V – 2.25V (1000mV amplitude setting).
[c] LVDS outputs terminated 100 across terminals.
Figure 8. EXT_SYS Input Timing Diagram
CLK_n
tS
EXT_SYS
QREF_r
tH
tW
Valid EXT_SYS
High Impedance
Clock Phase Noise Characteristics
Measurement conditions for phase noise characteristics:
▪ VCXO characteristics: f = 122.88MHz; phase noise: -80dBc/Hz(10Hz), -113dBc/Hz(100Hz), -141dBc/Hz(1kHz),-157dBc/Hz(10kHz),
-160dBc/Hz(100kHz):Input frequency: 245.76MHz
▪ ICPV VCXO-PLL charge pump current: 0.2mA
▪ VCXO-PLL bandwidth: 6Hz
▪ ICPF FemtoClock NG charge pump current: 1.6mA
▪ FemtoClock NG PLL bandwidth: 127kHz
▪ VDD_V = 3.3V, TA = 25oC
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Figure 9. 1474.56MHz Output Phase Noise
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Figure 10. 983.04MHz Output Phase Noise
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Figure 11. 491.52MHz Output Phase Noise
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Figure 12. 245.76MHz Output Phase Noise
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Application Information
Power Supply Design and Recommend Application Schematics
Careful power supply and board design is required for best possible AC performance including phase noise and spurious suppression. The
analog power supply pins VDD_OSC, VDD_CP, VDD_CPF, VDD_LCF and VDD_LCV require a very clean power supply isolated from the
output power supply (VDD_QCLK_y and VDD_QREF_r). Output power supplies should be isolated from each other. The VDD_LCF power
supply pin must be supplied by a low-noise LDO with a noise voltage of