954101DGLFT

ICS954101 Integrated Circuit Systems, Inc. Programmable Timing Control Hub™ for Desktop P4™ Systems Recommended Application: CK410 clock, Intel Yellow Cover part Output Features: • 2 - 0.7V current-mode differential CPU pairs • 6 - 0.7V current-mode differential SRC pair for SATA and PCI-E • 1 - 0.7V current-mode differential CPU/SRC selectable pair • 6 - PCI (33MHz) • 3 - PCICLK_F, (33MHz) free-running • 1 - USB, 48MHz • 1 - DOT, 96MHz, 0.7V current differential pair • 1 - REF, 14.318MHz Features/Benefits: • Supports tight ppm accuracy clocks for Serial-ATA and PCI-Express • Supports spread spectrum modulation, 0 to -0.5% down spread • Supports CPU clks up to 400MHz • Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning • Supports undriven differential CPU, SRC pair in PD# for power management. Key Specifications: • CPU outputs cycle-cycle jitter < 85ps • SRC output cycle-cycle jitter = 2.0V to select TEST o Power-up w/ V < 2.0V to have pin function as FS_C. · When pin is FS_C, VIH_FS and VIL_FS levels apply. · FS_B/TEST_MODE is a low-threshold input o VIH_FS and VIL_FS levels apply. o TEST_MODE is a real time input · TEST_SEL can be invoked after power up through SMBus B6b6. o If TEST is selected by B6b6, only B6b7 controls TEST_MODE. The FS_B/TEST_Mode pin is not used. · Power must be cycled to exit TEST. SW TEST FS_C/TEST_ FS_B/TEST_ ENTRY BIT SEL MODE B6b6 HW PIN HW PIN 0 X 0 1 0 X 1 0 X 1 1 X 1 1 X 1 REF/N 0 X 1 0 HI-Z 0 X 1 1 REF/N B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION) B6b7: 1= REF/N, Default = 0 (HI-Z) 0815G—12/02/08 14 REF/N or HI-Z B6b7 OUTPUT X NORMAL 0 HI-Z 1 REF/N 0 REF/N ICS954101 Integrated Circuit Systems, Inc. c N 56-Lead, 300 mil Body, 25 mil, SSOP L E1 INDEX AREA E 1 2 α h x 45° D A A1 b A A1 b c D E E1 e h L N a In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° VARIATIONS -C- e SYMBOL SEATING PLANE N 56 D mm. MIN 18.31 D (inch) MAX 18.55 .10 (.004) C Reference Doc.: JEDEC Publication 95, MO-118 10-0034 Ordering Information 954101yFLFT Example: XXXX y F LF T Designation for tape and reel packaging RoHS Compliant (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type 0815G—12/02/08 15 MIN .720 MAX .730 ICS954101 Integrated Circuit Systems, Inc. c N L E1 INDEX AREA E 1 2 a D A A2 A1 56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS a 0° 8° 0° 8° aaa -0.10 -.004 -Ce SEATING PLANE b VARIATIONS N aaa C 56 D mm. MIN MAX 13.90 14.10 Reference Doc.: JEDEC Publicat ion 95, M O-153 10-0039 Ordering Information 954101yGLFT Example: XXXX y G LF T Designation for tape and reel packaging RoHS Compliant (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) 0815G—12/02/08 Device Type 16 D (inch) MIN .547 MAX .555 ICS954101 Integrated Circuit Systems, Inc. Revision History Rev. E F G Issue Date Description 1. Updated Block Diagram. 6/1/2005 2. Update LF Ordering Information to RoHS Compliant. 1. Removed Skew from REF Electrical Characteristics Table 8/15/2005 only 1 REF output. 12/2/2008 Rremoved ICS prefix from ordering information 0815G—12/02/08 17 Page # 4,15-16 11 15-16 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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